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Description
Summary
The ALICE [1] Silicon Pixel Detector [2] data stream includes 1200 Fast-
OR signals indicating the presence of at least one pixel hit in each of the
detector readout chips [3]. This information is used in the ALICE Level 0
trigger decision to improve background rejection in pp interactions and event
selection in heavy ions runs [4].
A Pixel Trigger System has been designed to extract the Fast-OR signals
from the optical data lines and process them to provide an input signal for
the Level 0 trigger decision in the ALICE Central Trigger Processor. The
modular electronic system satisfying the requirements is described in this
paper.
The input to the Central Trigger Processor is to be provided in about
800 ns from the interaction time. This latency budget is largely used for
the Fast-OR generation, the serialization-deserialization of the data and the
optical transmission from the detector to the trigger system. Only a small
fraction of the latency is available for the extraction and processing of the
signals. A careful choice of the degree of the parallelism of the data flow
is required to comply with the short latency budget while maintaining a
reasonably limited number of data lines.
The Pixel Trigger System does not affect the Silicon Pixel Detector readout
system. The detector data stream is divided into two optical readout lines by passive
optical splitters. One output is sent to the data readout
modules in the counting room. The other one is connected to the optical
inputs of the Pixel Trigger System, located in the vicinity of the Central
Trigger Processor.
Ten optical input boards extract the Fast-OR signals, each one receiving
120 Fast-OR bits from twelve detector modules every 100 ns. The input
boards are based on optical receivers, dedicated G-Link ASIC decoders and
one FPGA. Prototype G-Link receivers using only FPGAs containing on
chip decoders have also been realized and tested. They did not satisfy the
latency constraint.
The 1200 extracted signals are transferred to a processing board by time
division multiplexing on 600 dedicated lines. Optional high speed serial
output links are provided on the optical input boards. The Fast-OR signals
are processed in a FPGA with a large number of input-output pins. The
output of the processing unit is then transmitted to the Central Trigger
Processor.
The system architecture is independent of the processing algorithm. A
set of different algorithms for the generation of the input to the Level 0
trigger is foreseen. They are based on the topology of the event or on the
occupancy. The system allows remote configuration of the processing FPGA
to enable the definition and implementation of the algorithms by the user.
Remote control, monitoring and configuration of the system are provided
by a dedicated processor on the processing board. Communication with the
control room is via an Ethernet link.
References
[1] ALICE Collaboration, ALICE Physics Performance Report, CERN-LHCC-2003-049, J.
Phys., G 30 (2004) 1517-1763.
[2] P. Riedler et al., Overview and status of the ALICE Silicon Pixel Detector,
Proceedings of the Pixel 2005 Conference, Bonn, Germany.
[3] A. Kluge, The ALICE silicon pixel detector front-end and read-out
electronics, Nucl. Instr. and Meth. A 560 (2006) 67-70.
[4] J. Conrad et al., Minimum Bias Triggers in Proton-Proton Collisions
with the VZERO and Silicon Pixel Detectors, ALICE-INT-2005-025.
