Jean-Francois Genat
(CNRS/IN2P3/LPNHE)
28/09/2006, 10:55
Oral
For the years to come, Silicon strips detectors will be read using the smallest
available integrated technologies for room, transparency, and power considerations.
CMOS, Bipolar-CMOS and Silicon-Germanium are presently offered in deep-submicron
(250 down to 90nm) at affordable cost through worldwide integrated circuits
multiproject centers. As an example, a 180nm CMOS readout prototype...
Vladimir Gromov
(NIKHEF)
28/09/2006, 11:20
Oral
Abstract.
Owing to a novel concept of the detection of the single electrons in gas, the GOSSIP
chip will hold certain advantages over an ordinary silicon pixel readout chip. Of
these, no need for silicon sensor at all, low detector parasitic capacitance and none
of the bias current at the pixel are the attractive features to design a compact
low-noise and low-power integrated front-end...
Maurice Garcia-Sciveres
(Lawrence Berkeley National Lab),
Robert Ely
(Lawrence Berkeley National Lab)
28/09/2006, 11:45
Oral
We present the results of irradiation tests of a 0.13um test chip containing ATLAS
pixel analog front end circuits and various types of memory cells. The irradiations
were carried out at the LBNL 88” cyclotron with 50 MeV/c protons and 16 MeV/c light
ions for SEU studies. The front end circuits perform well up to the highest dose
achieved at the moment, which is 1E15 p/cm^2. The linear...
Giulia Papotti
(CERN (PH-MIC) and Universita degli Studi di Parma)
28/09/2006, 12:10
Oral
This paper presents an ASIC implementing the line
encoding scheme to be used in the
GBT system, a multi-gigabit optical link designed for use
in future luminosity
improvements of the LHC. A general overview of issues
specific to optical links
placed in radiation environments is given, and the
required properties of the line
encoding discussed. A scheme that preserves the...
Hirokazu Ishino
(Tokyo Institute of Technology)
28/09/2006, 12:35
Oral
We are developing a monolithic radiation pixel detector using
silicon on insulator (SOI) with a commercial
0.15um fully-depleted-SOI technology
and a Czochralski high resistivity silicon substrate in place of a
handle wafer.
Nine types of SOI TEG chips
with a size of 2.5 x 2.5 mm^2 consisting of 20um pixels
have been designed and manufactured.
The I-V measurement, a laser light...