The aim of this work is to develop an internal PLL for ASIC developments which integrates time measurement or which requires an internal clock in the range of GigaHertz. For future upgrades in High Energy Physic detectors experiments, time measurement becomes a decisive element, which will make it possible to reduce the data flow and improve the spatial accuracy of the interaction point. This...
2.56 Gbps CMOS CML-transceiver is presented. The key feature of the design is capability of working with a specific inductive load at both power consumption and radiation tolerance constraints. The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron (Dubna).
While the potential of PAM4 is becoming more practical, many designs still choose the NRZ approach. This paper presents a customisable dual-mode PAM4/NRZ transmitter IP (with 4/2-tap channel equalisation) deployable in multiple CMOS technologies. IP has been fabricated in 65nm (28Gbps/14Gbps), 180nm (10Gbps/5Gbps) technologies. A radiation-hardened 65nm (20Gbps/10Gbps) flavour is in active...
A set of highly integrated read out ASICs with a common digitising and data aquisition back end but different front ends is currently under development at the GSI electronics department. The concept consists in using an analogue transient recorder stage for an efficient application of the area and power consuming analogue to digital converter. A focus of these ASICs is the read out of...
Front-End-Electronics are utilized by ATLAS muon chamber (MDT) to detect charge and give information regarding charge arrival time and amount of charge being detected. Read-Out-Electronics along with being robust, should operate faster, be area and power efficient. This paper presents improved version of AFE, ASD designed in 130nm technology, that is actually used for MDT chambers of ATLAS...
This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 MHz to 50 MHz and generates an output signal ranging from 400 MHz to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28nm CMOS technology of TSMC. The...
We present the test results of the ETROC PLL prototype chip. This chip is based on the latest version of ljCDR from the lpGBT project and is designed to test ljCDR in its PLL mode as the clock generator for the CMS Endcap Timing Layer readout chip (ETROC). An automatic frequency calibration (AFC) block with the data protector is implemented for LC-VCO calibration. Triple Modular Redundancy...
The front-end electronics of the ATLAS muon drift-tube chambers will be upgraded in the experiment's phase-II upgrade to comply with the new trigger and read-out scheme at the HL-LHC. A new amplifier shaper discriminator chip was developed in 130 nm Global Foundries technology for this upgrade. A preproduction of 7500 chips was launched in 2019 and tested in 2020. The functionality of the...
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. A first prototype, CIC1, was tested successfully in early 2019 and was...
Abstract: GBS20 is a transmitter ASIC for particle physics experiments. Two serializers each at 5.12 or 10.24 Gbps share a 5.12 GHz PLL clock. The serializers’ output is combined to a PAM4 signal that drives a VCSEL. The input data channels, each at 1.28 Gbps, is scrambled by a PRBS7 that is also the internal test pattern generator. Preliminary tests indicate that the prototype works at 10.24...
This paper describes the design and testing results of an 8 channels preamplifier-discriminator circuit based on a resistive feedback Transimpedance Amplifier architecture and a Leading-Edge Discriminator stage for fast high-accuracy time measurement systems. The circuit has been designed in a 130 nm CMOS technology. It is intended to be used as a Front-End-Electronics for measuring the Time...
A new data driven readout architecture for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz’ arbiters thanks to which there is no imposed prioritization and protection against glitches during readout is provided. The system allows not only reading the pixel activity, but also retrieving additional data, both analog and...
The CERN-RD50 collaboration aims to develop and study High Voltage-CMOS (HV-CMOS) sensors for use in very high luminosity colliders. Measurements will be presented for the RD50-MPW2 chip, a prototype HV-CMOS pixel detector with an active matrix of 8 x 8 pixels. The active matrix is tested with injection pulses, a radioactive source and a proton beam. This talk will cover the FPGA based DAQ...
This work presents the 8-channel FastIC ASIC developed in CMOS 65nm technology suitable for the readout of positive and negative polarity sensors in High Energy Physics experiments, Cherenkov detectors and Time-of-Flight systems. The front-end can be configured to perform analog summation of up to 4 single-ended channels before discrimination in view of exploiting area segmentation. The...
The ASIC design group at GSI developed an Amplifier With Adaptive Gain Setting (AWAGS) chip. The input stage based on a folded cascode architecture followed by a single-ended to differential conversion and output buffers. In difference to usual designs the capacitive feedback is divided in five capacitances with different values. Starting with the smallest one the capacitances were adaptively...
A monolithic pixel sensor named HVMAPS25 has been implemented in a 180nm HVCMOS technology. The pixel size is 25µm x 35µm. The pixel electronics contains a fast and low power charge sensitive amplifier, comparator, threshold tune DAC and a digital circuit that measure the arrival time of the hit with 10 bit resolution, <10ns bin width, and the amplitude (ToT) with 6 bit resolution.
The sensor...
We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 4fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to...
The Quad Transimpedance and limiting Amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode to look for the optimal coupling. A charge pump...
The ITkPixV1 chip is the pre-production pixel readout chip for the Phase-2 Upgrade of the ATLAS experiment at the HL-LHC. The harsh environment of HL-LHC, including a peak luminosity of 5x10^34cm-2s-1 and an estimated total ionising dose (TID) of more than 500 Mrad throughout its lifetime is placing strong requirements on the radiation tolerance of the chip. This contribution outlines...
A front end and trigger circuit was developed at GSI which is foreseen to be used in a transient recording read out ASIC. It consists of an input buffer with configurable low pass characteristics and a trigger which could be operated as leading edge discriminator as well as switched capacitor trigger which is sensitive to the first derivative of the input signal. The front end was produced on...
Chip design, is a lengthy process, which comes with high development efforts and costs and is a crucial milestone for the overall success of the project. Readout electronics for particle detectors resemble each other to a high degree, thus developing a software-adaptable receiver chain covering a large range of application scenarios is an attractive concept. With a generic approach, designed...
The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification...
