Development of high-time-resolution ASICs in CMOS 28-nm technology dedicated to precision 4D-tracking

5 Dec 2023, 15:30
20m
Conference room (Wosk Centre)

Conference room

Wosk Centre

Oral ASICs Day 2 - Session 3

Speaker

Adriano Lai (Universita e INFN, Cagliari (IT))

Description

Following up and finalizing the developments of former RnD projects and studies (INFN-funded TimeSPOT, Falaphel, Scaltech28 projects), The IGNITE project plans to implement an integrated system module, comprising sensor, electronics, and fast readout, specifically aimed at 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In this paper we present recent advancements on the development of a prototype ASIC, designed in CMOS 28-nm technology, which explores several circuital solutions on the front-end side. The Ignite_0 development is preparatory to the design of the first IGNITE full-ASIC, featuring a 64x64 pixel matrix, being completed in the future months.
The Ignite_0 has been submitted as a mini-ASIC containing new versions of a former 4D pixel design (the Timespot1 ASIC), consisting of an Analog Front End (AFE) and a high-resolution Time-to-Digital-Converter.
The TimeSPOT-type AFE is a Charge Sensitive Amplifier with Krummenacher feedback and discrete-time Offset Compensation. Some imperfections, present in the TimeSPOT 32x32 matrix version, are here corrected. New ideas on the AFE input stage and feedback circuit, aimed at obtaining a faster response and optimizing system performance in terms of time resolution and power, are here explored as well.
The TimeSPOT TDC, based on a Vernier-type architecture, has several improvements in terms of operational and SEU robustness. Furthermore, the front-end pixel size has been changed to make it compatible with the read-out of pixels from 55 µm (TimeSPOT) to 45 µm, by modifying only a redistribution layer (upper metal) according to the specific pitch adopeted.
The Ignite_0 ASIC integrates additional important service circuits, and in particular DACs and PLLS, to test them on silicon before their integration on the 64x64 pixel matrix, which is presently ongoing.
The explored solutions will be critically illustrated during the talk, highlighting their pro and cons.

Submission declaration Original and unplublished

Primary authors

Adriano Lai (Universita e INFN, Cagliari (IT)) Alberto Stabile (Università degli studi di Milano) Gian Matteo Cossu (INFN, Cagliari (IT)) Lorenzo Piccolo Luca Frontini (INFN and Università degli Studi di Milano) Sandro Cadeddu (Universita e INFN, Cagliari (IT)) Valentino Liberali (Università degli Studi di Milano)

Presentation materials