Speaker
Description
The ALICE experiment at the CERN LHC will replace the three innermost layers of the Inner Tracker System (ITS) with an innovative vertexing detector. A single-die stitched monolithic pixel detector of 1.8 cm x 26 cm designed in 65 nm CMOS imaging technology will be used to build these layers. The data communication is done via the 1.8 cm edge of the detector. This contribution will focus on the architecture, challenges and techniques used to aggregate and send off chip up to 46 Gb/s of data flux.
Summary (500 words)
The prototype single-die stitched monolithic pixel detector of 1.8 cm x 26 cm designed in 65 nm CMOS imaging technology is the second iteration of the stitched sensor for ALICE Inner Tracker System and will be submitted in 2024. The chip has two endcaps and a repeating frame which is replicated 12 times to fill the 26 cm length. Each repeating frame is subdivided into six independent sensor units. Each sensor unit can be considered as a self-contained pixel detector, with its own power domain, pixel matrix, biasing, slow control and readout unit. This segmentation granularity allows to switch off each sensor unit independently in case of manufacturing defects.
The data communication is done only through the left endcap (Fig. 1), which can be considered as a self-contained architecture within the stitched sensor design. The endcap receives data from all sensor units and sends it off-chip. Every sensor unit is connected to it with an independent on-chip data line. There are 144 data lines toggling at maximum 320 Mbit/s per line. The 144 on-chip data transmitters are distributed along the detector and generate a total data flux of 46.08 Gb/s. This data flux is aggregated and encoded in the endcap and sent off-chip via six 10.24 Gb/s high-speed serializers. The lpGBT-link protocol is used as a transport layer. The protocol itself increases the demand for the off-chip communication bandwidth. The requirement comes from the lpGBT encoding logic that contains cyclic redundancy check (CRC) and forward error correction (FEC). The use of high-speed serializers is necessary to meet the bandwidth requirements and to cope with a limited number of pads allocated to off-chip data transmission on the 1.8 cm edge of the detector.
The distance between each sensor unit and the endcap varies along the 26 cm sensor length. To maintain the logic levels of transmitted data, rebuffering has to be implemented at least twice per each repeated frame. The buffers are adding jitter to the signal which makes up to 3.6 ns for the longest data line leaving only 40% of the eye opening. The different line lengths make the phase of the data vary from around 1 ns to several dozen nanosecond. This variation depends on the data line length, number of rebuffering stages, voltage and temperature. The adopted solution to account for the jitter and phase delay is to implement a phase aligner per data line, that tracks the correct phase and samples the data in the middle of the eye opening.
This contribution discusses the techniques and solutions, including simulation and implementation details, adopted during the development of the left endcap architecture to address the challenges of aggregating a total of 46.08 Gb/s of data on 144 on-chip data lines with varying phase and jitter of each line. It also presents how the data is encoded and sent off-chip via six 10.24 Gb/s serializers to meet the data bandwidth requirements.
