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1–6 Oct 2023
Geremeas, Sardinia, Italy
Europe/Zurich timezone

Novel developments on the OpenIPMC project

5 Oct 2023, 17:40
1h 20m
Poster Programmable Logic, Design and Verification Tools and Methods Thursday posters session

Speaker

Luigi Calligaris (UNESP - Universidade Estadual Paulista (BR))

Description

In this contribution, we present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics experiments at CERN. We show the addition of new functions and support for new protocols in the controller mezzanine firmware. Finally, the latest changes and improvements to the board design are presented.

Summary (500 words)

Over the last three years, the OpenIPMC project has focused on the development of an IPMC for ATCA electronic boards, with the aim of becoming a free, open-source, and highly customizable solution that permits the ATCA board developer to fully customize the device to fit his board’s needs and allows independent maintenance and evolution of the firmware over the long-term. The OpenIPMC-HW hardware presents itself as an 8-layer PCB in the JEDEC MO-244 form factor designed around an STM32H7 microcontroller, with the card edge connector matching a commonly agreed-upon pin assignment across CERN experiments and providing a large number of general-purpose signals for board-specific use.

Recent developments on the mezzanine firmware include the addition of support for remote firmware upgrades following the PICMG HPM.1 standard, the YAFFS file system, the Trivial File Transfer Protocol, the Xilinx Virtual Cable service, the Remote Management Control Protocol, the RFC5424/3164 Syslog protocol, the IPMI System Event Log and a number of reliability improvements in the core hardware drivers. Other possible features currently being evaluated for introduction are discussed, such as firmware support for Advanced Mezzanine Cards and ATCA E-Keying. Furthermore, a number of improvements in the hardware design of the mezzanine are discussed, such as the addition of a debug header and changes to the method used to drive certain ATCA standard signals, to make the update and reboot processes of the IPMC not interfere with the running payload.

Primary authors

Alp Akpinar (Boston University (US)) Andre Muller Cascadan (UNESP - Universidade Estadual Paulista (BR)) Andrew Peck (Boston University (US)) Mr André Muller Cascadan (UNESP) Antonio Vitor Grossi Bassi (UNESP - Universidade Estadual Paulista (BR)) Carlos Ruben Dell'Aquila (UNESP - Universidade Estadual Paulista (BR)) Dan Gastler (Boston University (US)) Daniel Edward Gastler (Boston University (US)) Giacomo Fedi (Imperial College (GB)) Luigi Calligaris (UNESP - Universidade Estadual Paulista (BR)) Dr Luis Ardila (KIT-IPE)

Presentation materials