As part of the CMS phase-2 upgrade, the Serenity collaboration is developing Serenity-S1, a versatile FPGA-based processing card using the ATCA form factor. Widely adopted by various subdetector systems for the back-end data processing, a total of 777 boards are planned for production. This contribution presents the Factory Acceptance Test (FAT) designed for automated and efficient board...
The High Granularity Timing Detector (HGTD) for the ATLAS experiment, within the HL-LHC upgrade, uses Low Gain Avalanche Diode (LGAD) sensors for high-precision timing measurements.
AltirocA is the pre-production 225-channel readout ASIC, providing both luminosity and time-of-arrival measurements. The full system targets a resolution of 30 ps per hit initially and 70 ps after full...
The Low-power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. In 2023, almost 200,000 lpGBTs V1 were tested with a production test system that exercises the entire ASIC functionality to ensure its correct operation. Furthermore, qualification tests (Total Ionizing Dose, Single-Event...
The LiTE-DTU is an ASIC designed to digitize and transmit scintillation signals from the CMS Electromagnetic Calorimeter (ECAL) at HL-LHC. The chip was produced in TSMC 65 nm technology. The development process of the chip was not without hurdles, going through three prototype cycles and two engineering runs. Functionality and performance has been assessed in four test-beam campaigns. 96k...
The CMS High Granularity Calorimeter (HGCAL), developed for the HL-LHC, uses custom ASICs—HGCROC3 and H2GCROC3—to read out silicon sensors and SiPM-on-tile modules. These chips provide precise charge and timing measurements, digital processing for triggering, and are designed to operate in harsh radiation conditions. Version 3 of the chips implements all final features, with sub-versions A–E...
We present a novel 10 Gbps wafer-level testing system to characterize stitched Monolithic Active Pixel Sensors (MAPS) for ALICE ITS3 and ePIC SVT. Using a custom probe card and a 12-inch wafer-probe station, we demonstrate, for the first time in high-energy physics, 10 Gbps link characterization directly on wafer. Signal integrity was validated via bit error rate testing (BER < 10⁻¹²) and <70...
In order to fulfill the demands of the High-Lumi LHC, the whole ATLAS experiment will undergo a major upgrade.
The current Inner Detector will be replaced by it‘s all-silicon successor - the Inner Tracker (ITk).
The smallest feature complete detector units of the ITk are so-called Loaded Local Supports (LLS).
These LLS have now been tested for the first time, in a complex test-setup, which...
CoRDIA is an X-ray imager being developed, for Photon Science experiments at 4th generation Synchrotron Rings. Its goal is to be capable of continuous operation at 150k frame/s. Its Analog Front-End consists in a battery of adaptive-gain amplifiers and Analog-to-Digital converters, arranged in a pipelined, modular structure compatible with a compact pixel pitch (110um). A test structure has...
ATLAS ITk Pixel detector modules are operated in serial power mode using a Shunt-LDO circuit inside the ITkPix readout chip. Due to cooling requirements, the system must be operated within stringent power constraints, resulting in only 10% of the current being burned in the shunt during nominal physics operation. Since the current consumption scales with hit activity and there are significant...
Abstract
New sensor modules are currently being produced for the Tracker in the CMS Phase-2 Upgrade. These Strip-Strip and Pixel-Strip modules are the two main building blocks of the Outer Tracker. All together 8000 Strip-Strip and 5880 Pixel-Strip modules will be constructed and their construction requires the mass production of 47520 hybrid circuits. Despite careful preparation of the...
The Compact Muon Solenoid (CMS) detector will undergo a major upgrade (Phase-2) to take advantage of the increased luminosity provided by the High-Luminosity LHC (HL-LHC). As part of this upgrade, the Tracker Endcap Pixel detector (TEPX) will be introduced as a subsystem of the Phase-2 Inner Tracker, extending the pseudorapidity coverage up to |η|<4. The TEPX consists of eight double-layer...
The ARCADIA Main Demonstrator 3 (MD3), developed by the ARCADIA INFN collaboration, is a fully Depleted Monolithic Active Pixel Sensor in the LFoundry 110nm CIS technology. It features a custom backside process that allows for the full depletion of the high-resistivity substrate.
The first test beam on the MD3 was performed at the Fermilab Test Beam Facility in July 2024 with a 120 GeV...
The Zero Degree Calorimeters (ZDC) of the ALICE experiment at the LHC were designed to characterize the event and monitor the luminosity in heavy-ion measurement. The ZDC readout system developed for Run 3, based on a commercial 1 GSps 12 bit digitizer assembled on an FPGA Mezzanine Card, is able to operate in self-triggered mode allowing the acquisition of all collisions without dead time....
The Photon Detection Systems of the DUNE Far Detectors (FD-HV and FD-VD) use large SiPM arrays read out by low-noise, discrete-component amplifiers operating in liquid argon. Signals are transmitted to warm electronics either electrically (in FD-HD and in FD-VD membrane modules) or optically (in FD-VD cathode modules). The warm readout board, DAPHNE, interfaces with all these cold electronics...
The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in a high-energy physics detector. The first stitched prototype, the Monolithic Stitched Sensor (MOSS), underwent testing that confirmed yield compliance with ITS3 requirements. Linearity between time-over-threshold and deposited energy was validated from...
The contribution is focused on the new readout electronics for the µ-RWELL-based detectors that should be installed at the LHCb upgrade2 muon system. It is based on the FATIC (FAst Tuning Integrated Circuit) ASIC, providing charge and timing measurements of acquired signals. A first version of the chip, readout and controlled by a custom FPGA board, has been tested both in laboratory and...
The ALICE 3 Time of Flight detector requires a time resolution below 20 ps to allow for electron and charged hadron identification from 15 MeV/$c$ (forward e/$\pi$ separation) to 4 GeV/$c$ (p/K separation).
The expected event rate, of about 280 kHz/cm$^2$, makes monolithic CMOS sensors very attractive.
However, their time resolution is still far from the experiment needs.
A solution is to...
The CMS MIP Timing Detector (MTD) will deliver a timing resolution of ~30 ps at the beginning of High Luminosity LHC. A unified MTD data acquisition (DAQ) system has been developed to provide data readout, as well as comprehensive control and monitoring functionalities. Precision timing distribution is critical for ensuring stable synchronization and robust calibration procedures. The unified...
This paper presents performance of readout electronics for the ATLAS muon-chamber (MDT) to detect and measure the charge resulting from proton-proton collisions. The design emphasizes speed, robustness, and efficiency in area and power. It achieves a peaking time of 15 ns with 60-pF detector capacitance and 4 ns without it. The circuit demonstrates linear sensitivity of 1 mV/fC at the...
This report presents a single-channel readout chip LATRIC0 designed for the CEPC Out Tracker detector. The chip integrates an event-driven ring oscillator time-to-digital converter in a 55 nm process, achieving an average bin-size of 28.9 ps for both time over threshold and time of arrival. The average power consumption for measurement is below 1 mW. To mitigate the inconsistencies between...
In this work we report on the development of a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and can supply up to 1A at a voltage of 1.1 to 1.4V. Simulated PSRR at DC is -56dB. Safety features such as load overcurrent protection and the ability to shunt the current of failed parallel SLDOs...
This paper examines the latest advancements in power supply technologies for the HL-LHC, particularly focusing on the EASY6000 power supply system. Highlighted for its enhanced radiation tolerance, the system supports safe and efficient operations over the HL-LHC's extended lifespan. The study evaluates the system's performance in challenging environments, essential for optimizing power...
This work evaluates how stage count, gate length, and load capacitance tuning affect radiation tolerance in CMOS inverter based ring oscillators using a newly developed Dynamic Voltage-Dependent (DVD) Single-Event Transient (SET) model validated in a 65\,nm CMOS technology. The model captures n- and p-type Single Event Phase Transients (SEPTs). Simulations are performed under worst-case...
The CALOROC1B ASIC has been designed to read out the SiPMs for the ePIC detector at the EIC collider. Each of its 36 channels is composed of a high-gain preamplifier, two low-power preamplifiers, a dynamic gain switching mechanism, a shaper, and two ADCs to read the energy, with a discriminator connected to a TDC for time-of-arrival measurements. This work presents the ASIC architecture and...
The High Luminosity LHC upgrade demands enhanced tracking, prompting a full replacement of ATLAS’s Inner Detector with the all-silicon Inner Tracker (ITk). Spanning 33–291 mm from the beam pipe, ITk will use hybrid pixel detectors with 65 nm CMOS chips. The inner region, facing extreme radiation, will feature 3D pixel sensors, while the outer regions use planar sensors. Testing in 2024–2025...
This work presents the design, implementation, and characterization of a 28 nm CMOS readout channel for pixel sensors in future HEP experiments. The channel adopts the Time-Over-Threshold technique for the digital conversion of the detector signal amplitude and integrates a low-noise, charge-sensitive amplifier based on a composite cascode gain stage. A prototype chip, featuring an 8x32 array...
The bPOL48V is a DC-DC Point-Of-Load (POL) buck converter developed at CERN and characterized at RWTH Aachen University under the DRD7 program. The bPOL48V is designed to address power distribution challenges of next-generation high-energy physics experiments by enabling power delivery at higher voltages and lower currents in supply cables, thereby minimizing power losses. It supports a higher...
Motivated by the Upstream Pixel tracker in the LHCb Upgrade II and future electron-positron collider, COFFEE series chips are developed in a 55nm HVCMOS process. While maintaining a fine spatial resolution and reasonable power consumption, we aim to achieve a few nanosecond timing under hit density up to 100 MHz/cm$^2$. Building on the first validation chip with in-pixel amplification, a new...
High-energy physics experiments require radiation-tolerant optical links for high-speed data communication. Ring modulators offer high bandwidth but are sensitive to temperature and process variations, necessitating thermal control to stabilize their resonant wavelengths. This work presents a radiation-tolerant thermal control unit designed for micro-ring modulators. The system integrates a...
The new version of ToASt as a radiation tolerant readout for silicon microstrips sensors, has been produced and it is now under characterization. It is implemented in a 110 nm commercial CMOS technology, and it is synchronous to a 160 MHz clock. A common time stamp is used to provide both particle time of arrival and energy particle information with ToT technique. Triple logic is applied to...
Abstract (100 words)
The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL. The ETROC2 chips have been extensively tested, and the results have been presented at last TWEPP. We will present here new results including the bump bonding yield improvement study, the time walk correction (WTC) generality study with...
This work presents the Total Ionising Dose (TID) radiation assessment of HV-CMOS pixel sensors fabricated in the LFoundry 150 nm process. Two prototypes, UKRI-MPW1 and RD50-MPW4, were irradiated with X-rays up to 100 Mrad while biased and operated under designed conditions. Post-irradiation measurements on UKRI-MPW1 revealed increased leakage current, reduced breakdown voltage, and parasitic...
This work presents radiation-tolerant implementations for the SALSA front-end readout ASIC through redundancy methods applied to two median-finding algorithms designed for coherent noise suppression. Bit-wise Median Finder (BWMF) and Combinatorial Sum Median Finder (CSMF) were implemented in TSMC 65nm and IHP 130nm technologies and evaluated in terms of area, power, latency, and flip-flop...
We present the initial findings of a silicon photomultiplier powered by a laser and exposed to a light source. The study will explore various parameters of both the laser and the photomultiplier.
This work presents a 12-bit ADC implemented in 65 nm CMOS technology, designed for on-chip conversion in high-energy physics experiments, It is also intended for use as an IP block within the DRD7 collaboration framework. The architecture features a fully differential Capacitive DAC, a double-tail latched comparator and an asynchronous digital controller. Post-layout simulations demonstrate an...
Results are presented for the measurement of Single Event Upset (SEU) rate and recovery demonstration for the Kintex-7 FPGA on Thin Gap Chamber (TGC) readout boards for the ATLAS experiment at HL-LHC. The readout boards were installed on the TGC detectors in the ATLAS detector area. We observed 133 single-bit and 5 multi-bit SEU errors in the configuration memory of the Kintex-7 FPGA during...
MightyPix is a novel high-voltage monolithic active pixel sensor developed for the proposed LHCb Mighty-Tracker. It is designed to handle hit rates up to 40 MHz/cm² with 3 ns timing precision and a high radiation tolerance with NIEL and TID of up to 3×10^14 neq/cm² and 40 MRad. Building on prior prototypes MightyPix1 and LF-MightyPix, MightyPix2 integrates a segmented matrix architecture with...
Data-driven readout architectures produce unsorted streams of data packets with variable latency. Reconstructing an event frame, defined as grouping packets from the same time window, requires a sorting operation. Its complexity increases proportionally to the occupancy and distance between the packets’ source and the sorting step.
This contribution presents an on-chip bucket sorting module...
The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge...
The performance of the new CAEN controller R6060 was measured on a real slice of the ATLAS RPC detector, using 15 Easy3000 modules of various types, and compared with the present controller A1676A. An average improvement of a factor 30 was found for the response time of the single command execution, and of about 5 for the parameter refresh. Considering the test setup, an additional factor of...
The PRISME chip is developed as a new radiation tolerant PLL for clock generation with a jitter lower than ten ps. This block is designed in the TSMC 65 nm technology, to allow its integration in future readout ASICs that are considered for the EIC project. The PLL block is a basis of a low-power standalone clock fan-out ASIC with phase adjustment capabilities. A first prototype was design and...
The High Granularity Timing Detector (HGTD) is a Phase II upgrade project for ATLAS, aimed at providing precise time measurements for tracks to reduce the impact of pile-up effects.
The read-out is performed by ALTIROCA which is a 2x2 cm² CMOS 130nm ASIC with 225 channels.
In order to build the detector, about 27000 ASIC will be produced and tested at the wafer level using a probestation....
The HL-LHC upgrade will lead to increased radiation levels in the LHC tunnel. Consequently, hundreds of vacuum gauge conditioning electronics deployed throughout the LHC must be replaced by new radiation tolerant designs. The development of radiation tolerant electronics followed the CERN radiation hardness assurance protocol. Component and system-level radiation tests have been performed at...
At CERN, for the High-Luminosity upgrade of the Large Hadron Collider (LHC), the cryogenics instrumentation team will produce 2,000 electronic cards to support 1,800 new instrumentation channels. These cards will integrate with the LHC’s existing infrastructure of 10,000 transducer cards and are therefore designed to be radiation tolerant. This paper describes the results of two irradiation...
The INFN IGNITE project plans to implement a large-area ASIC (order 1-2 cm2) aimed at fast 4D-tracking. System pixels are required to have pitch below 50 µm and time resolution better than 30 ps. In the present paper we present measurement results concerning the performance of the two prototype ASICs, the Ignite32 and the Ignite64, designed to readout respectively 32x32 and 64x64 pixel...
The SALSA chip will be a versatile ASIC designed for various MPGD applications, including TPCs, trackers, and photon counting. It will feature 64 channels with tunable front-ends and fast ADCs, and a configurable DSP for data correction and feature extraction. The frontend includes a high open loop gain CSA, a pole-zero cancellation circuit, and a shaper, with four dynamic ranges and eight...
The ALICE ITS3 upgrade at CERN replaces the innermost vertex detector layers with six self-supporting, half-cylinder MAPS sensors.
This concept introduces new electrical and mechanical challenges addressed by a custom flexible printed circuit (FPC). The FPC distributes eight 10.24 Gb/s signals, control lines, and five power supplies for 24 segments, enables a semi-cylindrical transition,...
We studied the Total Ionizing Dose (TID) response of LSF0102 2-channel voltage translators intended for the upgrade of the ATLAS Muon Barrel read-out system for HL-LHC. TID tests were carried out at the CERN CC60 facility using a 60Co gamma source. The devices showed no degradation in key performance metrics, including supply current, eye diagram quality, rise/fall time, jitter, and bit error...
We present the development of an Ultra-Fast Silicon Pixel Detector (UFSPD) for Phase II of the Mu3e experiment, which aims to detect the rare decay of a muon into three electrons. To achieve the required sensitivity of $10^{−16}$, enhanced time and vertex resolution are essential. The UFSPD should replace the Phase I SciFi detector and targets a time resolution of ~100 ps. The first test...
Open-source design tools can play a very important role in the High-Energy Physics community. These tools offer a cost-effective alternative to proprietary EDA software, promoting reproducibility, collaboration, and long-term accessibility. This work presents a mixed comparison of three blocks — a Common-Mode Noise Filter (CMNN), Finite State Machine (FSM), and a VCO — designed using an...
The ALICE ITS3 project develops a wafer-scale monolithic stitched pixel detector chip of 27~cm lengths. One of the main challenges in such a design is to transmit data from the 144 pixel matrices (or tiles) to the Left End-Cap (LEC) region where the readout processor is located, without compromising power consumption, noise coupled into front-ends, and the active pixel area. This contribution...
Dephy is a research and development project supported by the IN2P3 institute, aiming to investigate the technologies required for the development of small-pixel detectors for trackers in future particle accelerators. Among its objectives, the project focuses on designing pixel readout circuits with high timing resolution, capable of operating in extreme radiation environments. For...
The MIP Timing Detector (MTD) is a key component of the CMS Phase-II upgrade for the High-Luminosity LHC. It includes a barrel (BTL) and endcap (ETL) timing layer. The BTL uses LYSO:Ce scintillating crystals coupled to SiPMs, read out by TOFHIR2 ASICs. The system targets a time resolution of 30 ps at the start of HL-LHC operation, degrading to 60 ps by the end due to radiation damage. We...
There are no existing SPICE models that account the effects of radiation doses exceeding 1 GRad in global transistor-level simulations for analog design in 28 nm CMOS technology within Electronic Design Automation environments. We present RAD-BSIM, the first SPICE model based on Berkeley Short-channel IGFET Model (BSIM) leveraging gate-oxide capacitance variations to enable robust circuit...
The BULLKID-DM experiment targets the detection of sub-GeV WIMP-like dark matter candidates using microwave kinetic inductance detectors (MKIDs). The experiment foresees the use of over 2000 individually instrumented silicon dice distributed across 15 wafers. We present the architecture of the room-temperature DAQ system based on the ZCU216 RFSoC board, including the design of a custom analog...
A full readout chain based on TIGER, a triggerless ASIC, and on GEMROCs, ARRIA-V FPGA-based readout modules, has been deployed for the BESIII CGEM-IT detector, along with ancillary modules to connect with the pre-existing DAQ.
The full system was installed in the experimental hall at the end of 2024 and it is now being commissioned with the detector with cosmics and beam collision. A...
This work presents the results of proof-of-concept ASIC implementing a novel TDC based on Time-to-Amplitude Converter (TAC) architecture demonstrating a best-case precision of 0.83 ps in a compact area (~0.021 mm²) and with low power (~2.6 mW per channel) making it suitable for high-density integration, typical of HEP applications.
It performs a time interval measurement between events by...
During LHC Long Shutdown 3, ALICE will replace its innermost three tracking layers with wafer scale stitched Monolithic Active Pixel Sensors(MAPS) bent around the beam pipe. Each 27 cm-long sensor is connected via wire bonds to a custom three-layer Flexible Printed Circuit(FPC). These FPCs deliver power, transmit up to 40 high-speed(10 Gb/s) data and control signals. Designed for a...
We present the design and first test results for SPIDER_v0, the first ASIC prototype in CMOS TSMC 65nm designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements are a time resolution of 15ps, and an occupancy up to 30% (12 Mevent/s).
SPIDER_v0 is a 2-channel waveform digitizer allowing time reconstruction by digital algorithms. The...
We present a Skipper-in-CMOS image sensor integrating Skipper-CCD non-destructive readout with CMOS pinned photodiode gain and in-pixel processing. Fabricated in a 180 nm process, a 200×200 array with 15×15 μm² pixels achieves 0.075e⁻ noise via multisampling. The SPROCKET2 ROIC, in 65 nm CMOS, supports 66.7 ksps high-speed readout with low DNL/INL and 10 μV resolution. A 20,000-pixel SPROCKET2...
We report on the performance studies of the SHiP Timing Detector using the FASTIC+ front-end ASIC developed at CERN. The system is designed to achieve sub-100 ps time resolution to suppress combinatorial background in the SHiP experiment. Ongoing work includes comparative tests between FASTIC+ and a discrete electronics board, as well as studies with two scintillator types, EJ-204 and EJ-232....
The High Granularity Timing Detector (HGTD) is a timing detector designed to mitigate pile-up effects in object reconstruction, arising from increased luminosity in the ATLAS Phase-II upgrade. The demonstrator system is a prototype system incorporating all key components of the HGTD project, developed to validate critical aspects of system integration. Installation and commissioning of this...
Wafer-scale monolithic active pixel sensors (MAPS) for particle detectors face significant
challenges in on-chip data transmission due to high resistance and capacitance in CMOS
interconnects, leading to signal distortion, attenuation, dispersion, and inter-symbol
interference (ISI). This contribution outlines these issues in the ALICE ITS3 MOSAIX chip and
presents current solutions by...
This contribution presents a co-simulation methodology that unifies sensor and front-end circuit modelling for pixel detectors. Traditional simplified signal models often fail to represent realistic particle-induced transients, leading to discrepancies between design-time assumptions and actual performance. The simulation chain enables simulation of a large number of realistic events,...
The DoWnstream Tracker (DWT) is a system of interconnected FPGAs reconstructing, in the upcoming LHC Run 4, stubs of tracks from the LHCb tracking subdetector located downstream to the magnet (SciFi).
Based on the high parellisable architecture “Artificial Retina”, the DWT aims at accelerating the LHCb reconstruction in the High Level Trigger 1, implemented on GPUs, by injecting track...
A short introduction of the "MedAustron Cancer Treatment and Research Center" and the medical application of ion beams in radio therapy including a description of the MedAustron accelerator and instrumentation setup, based on the CERN PIMMS study, and its operation mode.
The talk will be concluded with an overview of research activities and technical developments to improve treatment...
Next‑generation pixel‑based read‑out ASICs for high‑energy physics experiments
face demanding performance and integration requirements. A flexible, pixel‑level
simulation framework is essential to design, validate, and optimize the read‑out
architecture and its building blocks. We present a SystemVerilog/UVM
verification environment developed for the IGNITE project, a 28 nm CMOS...
The Tile Calorimeter of the ATLAS experiment is being upgraded for the
high luminosity LHC. The powering scheme of the calorimeter modules has been updated to provide higher efficiency and redundancy. Switching power supplies used in each module are responsible for providing power to the front-end electronics. The original power supplies, which are currently being used in the detector, lack...
The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in high-energy physics. MOSAIX, a fully functional prototype and the final development step before production, measures 266 mm by 19 mm. The chip integrates 144 independently powered pixel matrices, eight 10 Gbps transmitters, and on-chip power and data...
The consolidation of the Large Hadron Collider (LHC) Beam Position Monitor (BPM) requires digitising analogue signals from more than 1000 dual-plane BPMs using radiation-tolerant analogue-to-digital converters (ADCs). To this end, two commercial off-the-shelf (COTS) quad-channel, 12-bit ADCs operating at up to 1.6 Gsps were tested. Both ADCs were evaluated for cumulative radiation effects and...
Recent advancements in Artificial Intelligence (AI) and AI hardware accelerators have paved the way for on-edge AI processing with many benefits such as reduced data bandwidth and increased power efficiency. Applications in harsh radiation environments could also benefit from these improvements. However, due to the complex nature of both accelerators and the AI models running on them, the...
The dual-radiator RICH detector of the ePIC experiment at the future Electron-Ion Collider will use more than 300 thousand SiPM pixels as photosensors, organized in more than 1000 Photodetector Units (PDU). Each PDU is a $\sim$5x5x12 cm$^3$ module that includes 4 custom ASICs, connected to 256 SiPMs, and a FPGA-based card (RDO) controlling the readout. Considering dRICH moderately hostile...
Large aperture, high resolution, single photon imaging detectors are in high demand for future space explorations by missions
such as HABEX or LUVOIR. Yet making a TRL 10 operational detector prooved to be a very challenging endavour that takes more than
a decade. This talk will review the state of the art technology, and present more in depth an ASIC designed to cope
with the requierd...
ITk hybrid pixel detector consists of about 10,000 planar “quad” modules formed from 4 ASICs, (developed within the RD53 collaboration) bump bonded to a single sensor.
The flexible PCB attached to the sensor connects the ASICs to the system and provides the module's electrical environment.
To guarantee long-term reliability in the harsh HL-LHC environment, a tight quality control is...
We present the development of a 30 cm long Time-of-Flight (ToF) system targeting 30 ps timing resolution for charged particle detection. The system as part of a miniaturized charged particle spectrometer enables the extension of energy measurement to 2 GeV/n without using a magnet. Each of the two ToF channels integrate a plastic scintillator coupled to a silicon photomultiplier (SiPM),...
The growing capacity of high-end FPGAs enables more powerful algorithms in high-energy physics but introduces new challenges for firmware developers. The largest AMD devices, composed of multiple silicon dies (SLRs), face data transfer timing challenges due to Vivado’s placer limitations in large designs. In particular, pipelined buses crossing SLRs often experience poor flip-flop placement,...
One of the main challenges of picosecond TDC for 4D pixel detectors at future hadron colliders is the limitations of power consumption (down to $\mu$W/channel). To significantly reduce the power consumption and maintain other key specifications such as trigger rate and time resolution, a two-stage time-stretching TDC is proposed. This talk will present the proof-of-concept prototype design...
In its phase-2 upgrades, all of the CMS experiment's backend electronics systems are being replaced by ATCA boards featuring AMD Xilinx UltraScale+ FPGAs and high-speed optical modules. The EMP (Extensible Modular data Processor) framework provides common infrastructural firmware components, top-level designs and associated software for multiple CMS phase-2 backend boards and systems. It...
The data acquisition system of LHCb Upgrade I is a single stage readout followed by event building, real time reconstruction and selection. A generic readout board, called PCIe400, embedding Altera’s flagship Agilex 7 M-series FPGA with a 4x112 Gbit/s serial interface and a PCIe Gen 5 interface constitutes a baseline for LHCb future upgrades. It also targets clock distribution with phase...
In the new era of HL-LHC experiments, fast-timing detectors are emerging as a critical priority. Typical requirements include a temporal hit resolution of ~50 ps, spatial resolution of ~12 $\mu$m, and radiation hardness up to 10$^{16}$ neq/cm$^2$. To address these challenges, the development of non-standard sensor designs and advanced fast-readout electronics is required. The OPTIMA...
The Low Voltage Power Supply is a modular power converter stepping down 380VDC to 12VDC to power the widely used bPOL12V point-of-load converters. It is designed to operate in the radiation and magnetic-field environment of the CMS towers of experimental cavern. Three prototype iterations underwent radiation and magnetic-field testing, followed by progressive technical qualification. We...
The low-voltage supply chain for the High Granularity Calorimeter (HGCAL) Phase-2 upgrade of CMS powers the front-end electronics of 620m2 of silicon sensors and 370m2 of SiPM-on-Scintillating tiles. This chain consists of Low-Voltage Power Supplies custom-developed by CMS to operate in the experimental cavern, that power bPOL12V-based DCDC converters located inside the experiment, and custom...
The ATLAS Inner Tracker (ITk) will begin operation at the HL-LHC following LS3 for Run 4. Humidity inside the detector will be monitored using radiation-hard Fiber Optic Sensors based on Long Period Grating (LPG) and Fiber Bragg Grating (FBG), designed to operate below -20 °C and <10% humidity. Measuring relative humidity requires a complex method involving independent temperature and...
We present an implementation of the digital dual mixer time difference (DDMTD) circuit in an ASIC using current mode logic (CML) and discuss how it can be used to stabilize on-detector systems to a level of less than 1 picosecond. This circuit is used extensively in high energy physics applications and other clock distribution systems to monitor clock stability using FPGAs. By using CML logic...
The Barrel Calorimeter Processor (BCP), based on ATCA blade architecture, has been developed for the readout of the electromagnetic calorimeter (ECAL) and hadron calorimeter (HCAL) subdetectors. The BCP supports 120 optical receive channels of up to 25 Gbps, 72 optical transmit channels of up to 25 Gbps, an AMD XCVU13P UltraScale+ FPGA, and an embedded AMD Zynq UltraScale+ SoC. The production...
ALCYONE, an EU-funded project under the Horizon Europe program, addresses the impact of prolonged space exposure on biological systems, which is a critical challenge for future long-duration space missions. The project focuses on the development of a miniaturized on-chip micro-incubator to monitor and control environmental conditions for four types of cell cultures. To ensure precise radiation...
Precision timing is critical for the LHCb ECAL Upgrade II to operate effectively in the high pile-up conditions of the HL-LHC. Fast waveform sampling ASICs have been identified as suitable readout electronics for achieving the few tens of picoseconds resolution required to reconstruct electromagnetic showers. To extract precise timestamps in the presence of pile-up induced background, machine...
The SHiP SBT self-triggered readout will process SiPM sum signals sampled at 800 MSPS and 12 bit resolution to extract calorimetric particle hit information.
A waveform classification is being deployed on the readout FPGA to reduce the volume of transmitted data. The classification divides events into expected signal, expected noise or containing unexpected features applying different...
A 512-channel beam monitor was developed to measure beam parameters at particle rates from single particles up to clinical rates (several GHz). The system is designed for silicon carbide (SiC) strip sensors for increased radiation tolerance. The sensor readout uses four 128-channel analog charge-integrators with on-chip multiplexers, complemented by ADCs and a SoC module (FPGA + CPUs). Gigabit...
LANRS (Exploration of Lattice Dynamics of Nanostructures and Active Site Structures in Iron Proteins and Batteries with Nuclear Resonance) is a ministry-funded project aimed at enabling next-generation Nuclear Resonance Scattering (NRS) experiments. These require a large detection area, ultra-high temporal resolution of a few nanoseconds, and the ability to handle high event rates immediately...
Over the past year, significant progress has been made in the development of a dedicated test stand designed to evaluate the signal transmission integrity of approximately ~9k electrical links used in the Inner System (IS) of the ATLAS Inner Tracker Pixel upgrade. The Quality Control (QC) method of choice is a pre-existing multi-channel FPGA data acquisition architecture that has the...
We present a flexible detector readout prototyping module based on the AMD RFSoC platform, integrating fast ADCs, DACs, programmable logic, multicore CPU and several 28 Gbps-class transceivers. Sampling at GHz rates enables full digital signal processing, simplifying analog front-ends and improving timing and compactness. Two use cases are demonstrated: a digital emulation for the NA62 Liquid...
Modern System-on-Chip (SoC) devices are widely applicable; several boards in the LHC Phase-2 upgrade use them. However, their growing complexity, along with the increasingly intricate firmware and software development tools, makes it difficult for developers to keep up. To address this, we propose SoCks, a modular and scalable build framework for SoC devices that introduces a new layer of...
The Circular Electron Positron Collider (CEPC) has been proposed to operate as a Higgs factory producing electron-positron collisions with a center-of-mass energy of 240 GeV. The muon detector of CEPC plan to use the plastic scintillators with silicon photomultiplier (SiPM) to collect the scintillation light. In this work, we report the design of a readout system based on the ASIC readout...
ITk hybrid pixel detector consists of about 10,000 planar “quad” modules formed from 4 ASICs, (developed within the RD53 collaboration) bump bonded to a single sensor operated in serial power chains.
The flex attached to the sensor connects the ASICs to the system and provides module electrical environment while fulling the mechanical specifications.
The flex must provide a signal...
In preparation for operations at the HL-LHC, the CMS Collaboration is upgrading its endcap calorimeters with a high granularity calorimeter (HGCAL). The HGCAL back-end electronics includes two Non-Zero Suppression (NZS) boards, which dynamically disable zero-suppression in designated regions of interest. This paper presents a detailed discussion of the NZS algorithm’s principal components, and...
We present ongoing work on a Central Trigger Processor (CTP) board for the future Advanced SiPM-based LST camera of CTAO (Cherenkov Telescope Array Observatory). The system aims to implement a fully digital trigger on FPGAs, leveraging increased camera resolution to better discriminate low-energy gamma-ray events from noise. This approach seeks to enhance sensitivity while meeting CTAO-LST’s...
Hybrid pixel X-ray detectors operating in single-photon counting mode provide high spatial resolution, enhanced spectral imaging, and immunity to electronic noise. A common trend is to minimize pixel size, however, it often comes at the expense of spectral fidelity and position resolution due to charge sharing between channels. The spatial resolution can be further improved, though, by...
The Embedded Monitoring Processor (EMP) is a state-of-the-art platform based on a multi-processing System-on-Chip, developed for the upgrade of the ATLAS experiment’s Detector Control System. The EMP interfaces via high-speed optical transceivers with monitoring and control functionalities of radiation-tolerant Front-Ends. Preliminary analysis revealed limitations in throughput and CPU...
The forward Feature EXtractor (fFEX), a new ATLAS calorimeter
first-level trigger subsystem, will extend ATLAS' trigger
performance for jets and electromagnetic signatures in the
Forward Calorimeter (FCal). Utilising the full calorimeter
granularity, each processor processes ~2.3 Tbps of real-time
data. It is part of the trigger upgrade for the challenging
conditions in the High...
Abstract
Performance and stability of the CMS ECAL HL-LHC readout system depends on the good functionality of the Fron-End card (FE) – an interface between on-detector and off-detector section of the readout electronics.
Series of the design-specific integration tests were performed, including dependence of the readout chain functionality on the system clock quality, recovery from the...
In the context of the HL-LHC upgrades, xTCA (Advanced/Micro Telecom Computing Architecture) is a common standard in high energy physics. To keep it is a serious candidate for future readout systems and save the previous development investments in the post-telecom era, when classical telecom vendors migrating to cloud-based solution, the new coordination with manufactures is required. PICMG...
This study addresses X-ray beam stabilization challenges in fourth-generation synchrotron radiation systems by developing an active feedback control system. Replacing passive vibration isolation, the solution integrates high-sensitivity current detection (pA-nA range) for beam positioning with piezoelectric actuators achieving nanometer-scale adjustments. The driver operates at hundreds of mA...
The new CMS trigger system for the High-Luminosity LHC upgrade will exploit detailed information from the sub- detectors at the bunch crossing rate, allowing the Global Trigger (GT) FPGA firmware to use high-precision trigger objects. The GT will contain novel algorithms based on machine learning techniques such as Deep Neural Networks and Boosted Decision Trees to reach higher selection...
For the High-Luminosity Upgrade of the Large Hadron Collider, the ATLAS detector will receive a new silicon strip tracker. The module design utilizes readout hybrid flexes and powerboard flexes glued onto the sensor surface. In total, approximately 13,000 end-cap hybrid readout flexes and 6,000 end-cap powerboards are needed to build both end-caps of the strip detector. This contribution...
The ALICE ITS3 project will upgrade the inner silicon tracker layers with wafer-scale (27cm long) MAPS bent around the beampipe. The MAPS transfers its pixel data via 10.24-Gbps differential links driving a 30cm long FPC-cable.
The NKF7 proto-chip serialises a 16-bit static input to 10.24-Gbps output with a measured Bit Error Rate (BER)<10^-15. Irradiation with 32-MeV protons gives...
AC-LGAD detectors, recognized as promising candidates for 4D tracking systems, have achieved ~40 ps timing and ~10 µm spatial resolution in IHEP's 50-µm-thick strip sensors. However, centimeter-scale devices face challenges including charge sharing, capacitance, and power consumption. This study presents structural and process optimizations—such as n+ sheet resistance tuning, metal-pitch size,...
During the High Luminosity LHC, the instantaneous luminosity is expected to reach a peak of $7.5 x 10^{34} cm^{-2}/s$. The current CMS Inner Tracker will have to be entirely replaced to withstand a significantly higher data rate while operating in an harsher radiation environment.
The demanding requirements for the upgrade are met through the use of 65 nm CMOS technology readout chip and a...
During the next LHC shutdown the LHCb-RICH subdetectors will undergo a major upgrade and their electronics chain will be redesigned. The new on-detector electronics architecture will employ bPOL12V power modules. This work presents the validation strategy and the test system, which was designed to assess the performance of such modules in various LHCb-RICH configurations. We performed...
We report on results of irradiation experiments with ring modulators and Mach-Zehnder modulators of our current silicon photonic transmitter chip COTTONTAIL. Ex-situ experiments on ring modulators show a significant degradation from a total ionizing dose of more than 3 MGy and a difference in low and high frequency behavior. Forward bias annealing can mostly restore the pre-irradiation...
For a proposed upgrade of the Belle II experiment an R&D program has been established to develop a new vertex detector (VTX) made from a single type of depleted active monolithic pixel detector named OBELIX. The chip will provide two LVDS data links with a transmission speed of about 339 MHz. To read out the OBLEIX data it is foreseen to utilize optical links based on the lpGBT chip and the...
This poster presents an advanced real-time Wiener deconvolution algorithm designed to take advantage of the FPGAs integrated into the JUNO experiment readout boards. Exploiting online reconstruction of the signal generated by PMTs, we expect to enable the detection of low energy depositions, like those generated by transient astrophysical phenomena.
The features of the algorithm are...
The first processing stage of the HGCAL Backend trigger primitive generator system for the Phase-2 upgrade of the CMS detector will be implemented using the Serenity ATCA platform. This processing stage is responsible for receiving and pre-processing the trigger data coming from the HGCAL front-end and is composed of several firmware blocks. This contribution will present an overview of the...
The ATLAS Strip Tracker for the HL-LHC uses the End-of-Substructure (EoS) card to connect up to 28 data lines from the silicon sensor modules to the lpGBTs and VL+ ASICs. The EoS provides a 10 Gbit/s optical link to the off-detector systems. We report on the production experience with detailed QC statistics, the issues that were identified with the LpGBTv1 and required a complete reproduction....
This study presents optimizations to the Massive Temperature Readout System (MTRS), a low-cost alternative to traditional PLC-based systems for large-scale temperature monitoring. Our improved MTRS design streamlines hardware by eliminating intermediate microcontrollers and communication modules, reducing complexity and potential failure points. A unified multi-threaded C++ application...
The data acquisition electronics for the new HL-LHC Beam Position Monitor system will be based on a RFSoC, a System-on-Chip with integrated high-speed Analog-to-Digital Converters and Digital-to-Analog Converters.
While modular systems based on industrial computers and FPGA modules are well known and supported across CERN’s accelerators, SoC based systems are still novel, bringing new...
The iFTDC is a low cost, simple and flexible front-end card designed to measure signal timing for different types of detectors with a precision of 150 ps. It's based on ARTIX-7 FPGA, has 64 LVDS inputs and few user IO pins for configuration of attached ASICs. The FPGA's built-in high-speed serial link connects the board to the DAQ using the Unified Communication Framework protocol. The iFTDC...
For the Phase-2 Upgrade of the CMS Level-1 Trigger, a dedicated ATCA Rear Transition Module for the Serenity ATCA blade has been designed. It is intended to be used by the Phase-2 Global Trigger as well as the Beam Radiation Instrumentation and Luminousity group during operations of the CMS detector. It acts as a generic port expander for the Serenity card and is responsible for signal...
We introduce the FLASH experiment and present its electronic read-out system, currently under development. FLASH uses a resonant-cavity in a magnetic field to search for Dark Matter (DM) particles and High-Frequency Gravitational Waves (HFGWs). The cavity is operated at cryogenic temperatures to improve its performance, uses Superconducting Quantum Interference Devices (SQUIDs) as first-stage...
The Back-End Card (BEC) is a crucial component in the trigger readout chain of the JUNO experiment, serving as the interface between approximately 7,000 Global Control Units (GCUs) and the central trigger system. A total of 163 BECs were installed for deployment in the experiment's underground environment. To support the system's expected long-term operation, we perform a reliability...
To sustain the unprecedented radiation and rates of HL-LHC, the readout and trigger electronics for the Drift Tubes (DT) in CMS have been upgraded. The time digitization is implemented on the new OBDT board, and the data are streamed to the new back-end electronics where event building and trigger primitive generation are performed. The development of a new hardware, called MONitor for SAfety...
The ICARUS Liquid Argon (LAr) Time Projection Chamber (TPC) detector is taking data on the Booster (BNB) and Main Injector (NuMI) neutrino beam lines at Fermilab with a trigger system based on the scintillation light (detected by PhotoMultiplier Tubes PMT) produced by charged particles on the time of proton beam extraction from the accelerators. The layout consists of National Instruments...
We present the design, implementation, and characterization of an 8$\times$8 SiPM (AFBR-S4N66P024M) array adapted to the readout electronics of the CBM Ring Imaging Cherenkov detector. The front-end of the array consists of a preamplification stage with low power consumption (12\,mW/channel), high linearity, and low cost. In addition, we evaluated the performance of the SiPMs after neutron...
For the upcoming high-luminosity LHC, the endcap calorimeters of the CMS experiment will be replaced by the high-granularity calorimeter (HGCAL), a sampling calorimeter using silicon sensors in the front and plastic scintillators read out by SiPMs in the back. After successfully integrating the SiPM-on-Tile sensors with the Serenity back-end hardware, we have conducted detailed system tests to...
This paper presents a versatile readout system for particle detector front-end ASICs based on the AMD Zynq Ultrascale+ System-on-Chips. The system is suitable for both extensive laboratory characterization and for data acquisition at testbeam facilities. Its software-level scripting of the test procedure reduces the firmware development effort, maximizing the system reusability among different...
This work explores the use of the AMD Xilinx Versal Adaptable Intelligent Engine (AIE) to accelerate Gated Recurrent Unit (GRU) inference for latency-Constrained applications. We present a custom workload distribution framework across the AIE's vector processors and propose a hybrid AIE–Programmable Logic (PL) design to optimize computational efficiency. Benchmarking against existing FPGA GRU...
The TDAQ of the ATLAS experiment will be upgraded in alignment with the High-Luminosity LHC project so that the trigger rate increases from 100 kHz to 1 MHz. As the hardware muon trigger of TGC (RPC) for the endcap (barrel), we developed a Sector Logic ATCA blade consisting of a large-scale FPGA, AMD Virtex UltraScale+, and 10 Gbps optical transceivers. In two prototyping phases, we evaluated...
The LHCb-UpgradeI experiment has adopted a heterogeneous computing-based trigger system that relies on the reconstruction of all collision events, occurring at 30MHz. In this context, a two-dimensional FPGA-based cluster-finding architecture has been developed to reconstruct in real time hit positions in the vertex pixel detector, capable of processing $\sim10^{11}$ hits/second, and freeing...
Timing and control firmware was developed to operate a vertical slice of the CMS high-granularity calorimeter front-end and back-end systems at beam tests, in the absence of a full-fledged system. It provides various trigger sources (software, regular, random, external), throttling mechanisms and a programmable sequencer of fast commands. A data capture block for local readout of the outgoing...
Future High Luminosity LHC runs introduce more simultaneous proton-proton collisions for the LHC experiments. The ATLAS Tile Calorimeter (TileCal) plans a replacement of the on- and off-detector electronics to meet the requirements for faster data processing. New off-detector electronics provide high-bandwidth data to the upgraded Trigger and Data Acquisition (TDAQ) system. The Tile...
Description
We present the design and first test results for SPIDER_v0, the first ASIC prototype in CMOS TSMC 65nm designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements are a time resolution of 15ps, and an occupancy up to 30% (12 Mevent/s).
SPIDER_v0 is a 2-channel waveform digitizer allowing time reconstruction by digital...
