19–21 Nov 2014
CERN
Europe/Zurich timezone

New Technological Capabilities at CNM

19 Nov 2014, 16:05
20m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

503-1-001 (Council Chamber) on 19th Nov ; 500-1-001(Main auditorium) on 20th in the morning and 4-3-006 (TH auditorium) in the afternoon; 500-1-001(Main auditorium) on 21st Nov.
400
Show room on map

Speaker

Dr David Flores (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC))

Description

In this talk, we will present some technological capabilities that could be of interest for the RD50 community. In this sense, the first results from new PiN diodes integrated on 6-inch N-silicon wafers will be shown. To perform this 6-inch technological process we have upgraded the standard CNM 4-inch process to the new wafer size. Additionally, we will describe the works performed to increase the layout edition capabilities to achieve a full-sensor automatic layout generation using Python. Finally, we will present a description of the technological and electrical characterization resources for silicon detectors at our labs, in particular we will explain our Reverse Engineering procedures that allow a deeper insight on the physical and geometrical properties of the fabricated devices.

Author

Dr David Flores (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC))

Co-authors

Dr David Quirion (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC)) Dr Giulio Pellegrini (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC)) Dr Miguel Ullan Comes (Instituto de Fisica Corpuscular (ES)) Dr Pablo Fernandez-Martinez (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC)) Dr Salvador Hidalgo (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC)) Dr Virginia Greco (Instituto de Microelectronica de Barcelona (IMB-CNM-CSIC))

Presentation materials