TWEPP 2015 - Topical Workshop on Electronics for Particle Physics

Session

ASICs

1

29 Sept 2015, 14:50

Lisbon

Conveners

ASICs

• Christophe De La Taille (OMEGA (FR))

ASICs

• Christophe De La Taille (OMEGA (FR))

ASICs

• Christophe De La Taille (OMEGA (FR))

ASICs

• Alessandro Marchioro (CERN)

ASICs

• Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

ASICs

• Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

ASICs

• Mitchell Franck Newcomer (University of Pennsylvania (US))

27. A High Frame Rate Pixel Chip Design for Synchrotron Radiation Applications

Wei Wei (IHEP, CAS, China)

29/09/2015, 14:50

ASICs

Oral

A hybrid pixel detector working in the single photon counting mode was designed for the High Energy Photon Source (HEPS) in China. The pixel readout chip contains an array of 104 × 72 pixels with a pixel size of 150µm×150µm, each with a counting depth of 20bit. The measurement showed 118e- equivalent noise after bump bonding and non-uniformity less than 55e- after threshold equalization. All...

91. 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

Luigi Gaioni (University of Bergamo)

29/09/2015, 15:15

ASICs

Oral

This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the...

94. Front End ASIC for AGIPD, a high dynamic range fast detector for the European XFEL

Dr Alexander Klyuev (Deutsches Elektronen-Synchrotron)

29/09/2015, 15:40

ASICs

Oral

Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector for the European-XFEL. The detector's important part is the radiation tolerant front end ASIC fulfilling the European-XFEL requirements: High dynamic range - from sensitivity to single 12.5keV-photons up to 10⁴ photons. It is implemented using the dynamic gain switching technique with three possible...

215. Front end Optimization for the Monolithic Active Pixel Sensor of the ALICE Inner Tracking System Upgrade

Daehyeok Kim (Yonsei University (KR))

30/09/2015, 09:50

ASICs

Oral

ALICE plans to replace its Inner Tracking System in 2018 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested....

3. Charge Collection Properties of a Depleted Monolithic Active Pixel Sensor using a HV-SOI process

Sonia Fernandez Perez (CERN)

30/09/2015, 10:15

ASICs

Oral

We have fabricated and tested a new 0.18 um SOI CMOS monolithic pixel sensor using the XFAB process. In contrast to most SOI technologies, this one provides a double well structure, which shields the thin gate oxide transistors from the Buried Oxide. This in addition with the particular geometry between transistors and BOX makes the technology promising. The process allows the use of high...

12. Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

Eva Vilella (University of Liverpool)

30/09/2015, 11:10

ASICs

Oral

HV-CMOS sensors can offer important advantages for large area tracking systems in high energy physics experiments. Their use in future collider experiments (HL-LHC) will depend on the capacity to sustain the anticipated radiation levels. This contribution presents the design and preliminary measurements of an HV-CMOS pixel demonstrator in the ams 0.35 µm HV-CMOS technology for the ATLAS...

145. Development on CMOS MAPS devices for the ATLAS Phase-II Strip Tracker Upgrade

Todd Brian Huffman (University of Oxford (GB))

30/09/2015, 11:35

ASICs

Oral

ATLAS is currently studying the use of CMOS MAPS devices as a replacement for the baseline silicon strip sensors for the Phase-II Strip Tracker Upgrade. One of the key aspects is to establish whether the radiation hardness is suitable for the HL-LHC environment. Two different technologies are being studied: High-Voltage CMOS and High-Resistivity CMOS. Several test chips have already been...

200. Prototype active silicon sensor in LFoundry 150nm HV/HR-CMOS technology for ATLAS Inner Detector Upgrade

Piotr Rymaszewski (Universitaet Bonn (DE))

30/09/2015, 12:00

ASICs

Oral

The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of the inner tracking detectors. A possible solution is to use active silicon sensors taking advantage of commercial HV/HR-CMOS technologies. Current ATLAS R&D programme is qualifying a few commercial technologies it terms of suitability for this task. During...

57. Design and results of a 65 nm digital readout Macro Pixel ASIC (MPA) prototype with on-chip particle recognition for the Phase II CMS Outer Tracker upgrade

Davide Ceresa (CERN)

30/09/2015, 14:50

ASICs

Oral

The High Luminosity LHC (HL-LHC) requires major upgrade to the CMS experiment. In particular, the Phase II CMS Tracker upgrade needs a completely new readout ASIC called Macro Pixel ASIC (MPA) for its Pixel-Strip modules. It will extract and digitise analogue signals from pixelated sensor and perform digital processing at 40 MHz frequency. The digital processing includes particle recognition...

171. A 128-channel event driven readout ASIC for the R3B Tracker

Mr Lawrence Jones (STFC Rutherford Appleton Laboratory)

30/09/2015, 15:15

ASICs

Oral

R3B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams onto and out from a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in...

83. PACIFIC: The readout ASIC for the SciFi Tracker planned for the upgrade of the LHCb detector

Jose Mazorra De Cos (Instituto de Fisica Corpuscular (ES))

30/09/2015, 15:40

ASICs

Oral

PACIFIC is a 64 channel mixed-signal ASIC designed for the scintillating fiber (SciFi) tracker developed for the LHCb upgrade in 2018/19. It connects without interface to the 128 channel double dye SiPM arrays sensing the fibers. The analog processing begins with a current conveyor followed by a tunable fast shaper and a gated integrator. The signal is digitized with a 2bit nonlinear flash ADC...

139. SAMPA Chip: a New ASIC for the ALICE TPC and MCH Upgrades

Marco Bregant (Universidade de Sao Paulo (BR))

01/10/2015, 09:50

ASICs

Oral

This paper presents the SAMPA ASIC that will be used in the ALICE upgrade for time projection chamber (TPC) and muon chamber (MCH) read-out frontend electronics. The SAMPA ASIC is being designed in 130nm CMOS technology with 1.2V nominal voltage supply. The SAMPA ASIC includes 32 channels, with selectable input polarity, and five possible combinations of shaping time and sensitivity. Each...

32. FATALIC: A dedicated Front-End ASIC for the Atlas TileCal Upgrade

Laurent Royer (Univ. Blaise Pascal Clermont-Fe. II (FR))

01/10/2015, 10:15

ASICs

Oral

A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline...

223. KLauS: A low power Silicon Photomultiplier Charge Readout ASIC in .18 UMC CMOS

Konrad BRIGGL (Heidelberg University)

01/10/2015, 11:10

ASICs

Oral

We present the development of a low power Silicon Photomultiplier readout ASIC for imaging calorimetry detectors at future linear colliders. The analog front-end is designed to achieve sufficient SNR for single pixel signals using low gain SiPMs, while allowing charge measurements over the full sensor dynamic range. It consists of an input stage, two charge measurement branches and a fast...

67. A low jitter PLL frequency synthesizer for high resolution TDCs in 65nm CMOS technology

Jeffrey Prinzie (KU Leuven (BE))

01/10/2015, 11:35

ASICs

Oral

A PLL has been designed for high frequency clock generation with only 280 fs RMS jitter. The integer N PLL multiplies a 40 MHz reference clock to 2.56 GHz. The PLL uses a low phase noise LC tank oscillator that has a tuning range from 2.4 GHz to 3.7 GHz with a phase noise of only 125 dBc/Hz @ 1 MHz and a power consumption of 5.7 mW. An all-digital automatic frequency calibration circuit is...

208. A fast multichannel, ultra-low power 10-bit ADC for readout of future particle physics detectors

Marek Idzik (AGH University of Science and Technology (PL))

01/10/2015, 12:00

ASICs

Oral

The architecture, design, and preliminary measurements of multichannel 10-bit SAR ADC developed in CMOS 130~nm technology for readout systems of particle physics experiments, are presented. Other design issues like data serialization and high speed transmission are also discussed. The results of static and dynamic measurements, power consumption, crosstalk, etc., performed in multichannel...

68. Redundant SAR ADC architecture and circuit techniques for ATLAS LAr Phase-II upgrade

Yun Chiu (UT Dallas)

01/10/2015, 14:50

ASICs

Oral

We present the architecture and circuit techniques of a 14-bit 80-MS/s split-SAR ADC in 65-nm CMOS with preliminary simulation results. By exploiting redundancy, SEE-related conversion errors can be efficiently detected and corrected at the architectural level by the added SEE-detection circuitry. The digital calibration also makes the overall ADC performance insensitive to transistor...

175. Development of a low power Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) in 130nm CMOS technology

Miroslaw Firlej (AGH University of Science and Technology (PL))

01/10/2015, 15:15

ASICs

Oral

The design and measurement results of a low power PLL and DLL prototypes for applications in particle physics readout systems are presented. The PLL was designed for frequency range 30MHz - 450MHz and 16 clock phases. Preliminary measurements show, that is functional and has period jitter ~6.7ps (RMS) at 160MHz. The DLL operates for input clock range 18MHz - 62MHz and generates 64 uniform...

232. GBLD10+: A Compact Low-power 10 Gb/s VCSEL Driver IC

Tao Zhang (SMU)

01/10/2015, 15:40

ASICs

Oral

We report the design and implementation of a low-power and radiation-tolerant 10 Gb/s VCSEL Driver (GBLD10+) for High Energy Physics (HEP) applications. With new circuit techniques, the single-channel driver consumes 40 mW and occupies a compact size of 380 µm × 1730 µm including the PADs. These features allow multiple of driver ICs to be assembled side by side in a compact package, with each...