Conveners
POSTER Session: 1 - Other
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 1 - Power, Grounding and Shielding
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 1 - Production, Testing and Reliability
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 1 - ASIC
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 2 - Programmable Logic, Design Tools and Methods
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 2 - Trigger
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 2 - Radiation Tolerant Components and Systems
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 2 - Systems, Planning, Installation, Commissioning and Running Experience
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 1 - Optoelectronics and Links
- Mitchell Franck Newcomer (University of Pennsylvania (US))
POSTER Session: 1 - Packaging and Interconnects
- Mitchell Franck Newcomer (University of Pennsylvania (US))
We present a serial link transmitter designed for CMOS pixel sensors in a 0.18 µm CMOS Technology. The transmitter includes a digital interface block with Reed-Solomon encoder, a Phase-Locked Loop (PLL), a serializer and a Current Mode Logic (CML) driver with pre-emphasis. Functionalities of the transmitter is verified by simulation, consuming 174 mW from a 1.8 V power supply. The transmitter...
A 4-channel parallel 56 Gb/s optical receiver for VCSEL-based optical links is presented. The receiver has been manufactured in a standard 65nm-CMOS process. Simulation results with layout parasites and a model of a wire-bonded photo diode demonstrate that the single channel works at bit rate of 14 Gb/s and has an input sensitivity of better than 20 uApp, an input-referred noise of 2.3 uArms...
The MPA is the pixel readout ASIC for the hybrid Pixel-Strip module of the Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It employs a novel technique for identifying high transverse momentum particles and provides this information at a 40$\,$MHz rate to the L1-trigger system. The chip also comprises a binary pipeline buffer for the L1-trigger latency, and a data path...
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground experiment based on a 20,000 ton liquid scintillator with the one main objective to determine the neutrino mass hierarchy. The signal detection is performed by photomultipliers with directly attached readout electronics. The central component for the digitization process is a receiver chip with a low power...
Large area silicon trackers with excellent time and position resolution are now considered in the upgrade programs of the ATLAS and CMS detectors.
In this contribution we present the development of a custom ASIC chip meant to be bump-bonded to segmented Ultra-Fast Silicon Detector, aiming to achieve a combined time resolution of $\sigma \sim$ 30 ps.
The ASIC is implemented in standard...
We present the design and characterization of a CMOS pixel direct charge sensor, Topmetal-IIa, fabricated in a standard 0.35$\mu$m CMOS process. The sensor features a $45\times216$ pixel array with a 40$\mu$m pixel pitch which collects and measures external charge directly through exposed metal electrodes in the topmost metal layer. Each pixel contains a low-noise charge-sensitive...
The Liquid Argon Pixel (LArPix) prototype ASIC implements 32 channels of analog front end circuitry and backend digitizers at a power consumption of less than 50 uW/channel. LArPix is envisioned as a component of a potential DUNE near detector TPC module. Demanding noise, power, and dynamic range requirements are imposed by myriad particle interaction scenarios. Widely varying track...
This paper presents a HV/HR-MAPS detector designed in the framework of the HVCMOS collaboration for the ATLAS Inner Tracker update in the HL-LHC era. It was fabricated with a 150 nm HVCMOS process which includes a layer to isolate the bulk of PMOS transistors from the collecting node of the sensor. All front-end electronics are integrated inside the pixel, which is of only 50 µm x 50 µm, and...
After having commissioned the readout electronics currently implemented in the Insertable B-Layer, Layer 1 and Layer 2 of the ATLAS Pixel Detector (B-Layer and Disk readout electronics in under commissioning), we have designed and fabricated a new readout electronic board looking at the upgrade of the LHC pixel detectors. A couple of PCI_express-based prototype boards, namely PCI-ROD featuring...
The ALICE experiment at the LHC plans an upgrade of its TPC, due to the expected high Pb-Pb collision-rate after the shutdown of LHC in 2018. In the upgraded TPC, Gas Electron Multiplier (GEM) chambers and continuous readout system will replace MWPC chambers and conventional triggered readout, respectively. In the continuous readout, GEM signals will be processed using 32 channels of SAMPA...
The digitization stage of the main electromagnetic calorimeter of the CBELSA/TAPS experiment in Bonn (Germany) is being equipped with custom 80 MSPS, 14 bit Sampling-ADCs. Onboard data processing with FPGAs allows determination of the signal characteristics, reducing the data substantially. The readout of the unprocessed sampling data allows offline analysis and refinement of the...
Large aperture MCP based UV single photon imaging detectors are commonly used in space applications. NASA granted,the development of new detector with a geometrical acceptance up to a 100x100 mm, as well as ASICs for the construction its readout system. We developed the detector and ASIC chips which enabled the construction of it's readout system. The system is composed of fast, low noise and...
The prototype Barrel module design, for the Phase II upgrade of the of the new Inner Tracker (ITk) detector at the LHC, has adopted an integrated low mass assembly featuring single-sided flexible circuits, with readout ASICs, glued to the silicon strip sensor. Further integration has been achieved by the attachment of module DCDC powering, HV sensor biasing switch and autonomous monitoring and...
The increase of luminosity foreseen for the Phase-II HL-LHC upgrades calls for new solutions to fight against the expected pile-up effects. One approach is to measure very accurately the time of arrival of the particles with a resolution of few tens of picoseconds. In addition, a spatial granularity better than a few millimeter will be needed to obtain a fake jet rejection rate acceptable for...
The silicon-strip system in the ATLAS ITk detector has individual sensor modules mounted on staves to provide integrated solution for mechanical support, power, cooling, and data transmission. The data and power are transmitted to individual modules on polyimide tapes placed on thermo-mechanical stave cores. The 1.4 m long tapes transmit module data at rates up to 640 Mbps, several multi-drop...
This work presents the design and characterization of a SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications. The prototype chip was designed and fabricated in the framework of the CHIPIX65 project and was completely characterized. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal...
This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive...
We present designs and test results of two radiation-tolerant VCSEL array driver ASICs fabricated in 65 nm CMOS technology, VLAD28 and VLAD14. VLAD28 is a 4 × 28-Gbps driver, delivering 2 mA bias and 5 mA modulation currents with a power consumption of 90 mW/ch. VLAD14 is a low-power 4 × 14-Gbps driver, delivering 2 mA and 6 mA modulation with a power consumption of 44 mW/ch. The two drivers...
We present a front-end readout ASIC developed for a new family of ultra-fast 1D detectors. The ASIC is designed in 110 nm CMOS technology and is compatible with different semiconductor sensors (Si or InGaAs) and geometries. The chip contains up to 128 channels, each consisting of a Charge-sensitive Amplifier, a fully-differential shaping stage and an high-speed output buffer. A frame-rate of...
One of the crucial parts of the proposed low occupancy Timing Vertex Detector (TVD) is a waveform sampling ASIC denoted the RFpix. It is being developed to sample and digitize voltage pulses and enable measurements of their arrival times with a timing resolution of 100fs or less. To achieve this, the RFpix needs to have an analog bandwidth of 3GHz and a sampling speed of 20GS/s. In this paper,...
Currently there is a lot of activity in R&D for future colliders. Multiple detector prototypes are being tested, each with different requirements for data acquisition and monitoring, which has generated different ad-hoc software solutions. We present [DQM4HEP][1], a generic C++11 framework for online monitoring for particle physics experiments, and results obtained at several testbeams with...
The upgrade of the ALICE Inner Tracking System uses a newly developed Monolithic Active Pixel Sensor (ALPIDE) which will populate 7 tracking layers surrounding the interaction point. Chips communicate with the readout electronics using a 1.2 Gb/s data link and a 40 Mb/s control link. Event data are transmitted to the readout electronics over microstrips on a Flexible Printed Circuit and a 5m...
In the Large Hadron Collider (LHC), the cryogenics instrumentation infrastructure uses fuse-protected high-voltage isolated temperature transducer cards. Spurious faults were observed at their miniature silver fuses during the periods 2008-2010 and 2014-2016 and a study was launched to understand the underlying failure mechanism.
The study uses data from Scanning Electron Microscopy (SEM),...
High efficiency, radiation hard, hybrid GaN and CMOS integrated module DC-to-DC converter has been designed. The integrated, compact, low-mass, single-module DC-DC converter solution has an input voltage of 18V regulated down to an output voltage of 1.4V, with 5A maximum load current. It exhibits >80% efficiency. Discrete GaN transistors are used for the power stage, and the controller...
A pseudo-LVDS driver has been designed in a 180 nm technology for operation up to 5 Gb/s.
It contains parallel main driver units based on an H-bridge circuit steering a current on an external load. The number of active units is selectable,
to reduce switching capacitance and static current, and hence power consumption, if a smaller current swing can be tolerated.
Pre-emphasis is applied with...
This paper proposes a novel 2.56 Gbps radiation hardened by design LVDS/SLVS like receiver for use in transmission systems requiring timing accuracy. The circuit, designed in a commercial 65 nm CMOS technology, uses a replica receiver with charge pump feedback. This feedback loop equalizes the propagation delay of the outputs rising and falling edge, independent of total ionizing dose (TID)...
All LHC experiments will be upgraded during the next LHC long shutdowns (LS2 and LS3). The use of more advanced CMOS technology nodes typically implies higher current consumption of the on-detector electronics. In this context, and in view of limiting the cable voltage drop, point-of-load DC-DC converters will be used on detector. This will have a direct impact on the existing powering scheme,...
Monolithic Active Pixel Sensors are becoming increasingly attractive for the next generation High Energy Physics experiments. For this reason several R&D are ongoing in different laboratories to improve the performance of conventional MAPS.
In this context we present a flexible readout electronics specifically developed for the detailed characterization of MAPS. The prototype ASIC has been...
The future of connectivity is wireless, and the HEP community is not an exception. The demand for high capacity data transfer continues to increase every year at a significant rate. For example the tracking detectors require readout systems with several thousand links that has to handle a data transfer of multiple-gigabit/s each. We propose to use the millimeter-wave band between (57-66 GHz)....
The CMS ECAL barrel electronics will be upgraded for the HL-LHC to meet the latency and bandwidth requirements of the Phase-II Level-1 trigger system. The front-end electronics will mitigate the increasing noise from the avalanche photodiodes (APDs), discriminate against anomalous APD signals and provide improved timing information. The foreseen solution is to replace the current...
A new inner tracking detector (ITk) for the Phase-II upgrade of the ATLAS experiment is in development. A serial power scheme is foreseen for the pixel detector. This requires a new detector control system (DCS) to monitor and control the pixel modules in the serial power chain.
The Pixel Serial Power Protection (PSPP) chip is an ASIC for this purpose. It operates parallel to the modules and...
A quad chip module hybrid—assembled with FE-I4 chips—has been fabricated to test performance in a serially powered module chain as would be used in the upgraded ATLAS pixel layer at the High Luminosity LHC. This poster present results of the development of a flex circuit board interface for the quad chip modules and system integration tests of modules installed on an I-beam. Experience from...
Radiation tolerant serial links for high-speed data transmission in High Energy Physics experiments have been developed at INFN-Pisa and UCSB in a commercial 65nm CMOS technology: 2Gbps Standard-Cell based Serializer and Deserializer and custom 3GHz SLVS Driver and Receiver. Results of test and characterization of the last version of the circuit prototypes produced in the second half of 2016...
The SSA is a silicon-strip readout ASIC for the hybrid Pixel-Strip detector of the CMS Outer Tracker High Luminosity LHC (HL-LHC) Phase II upgrade. It is a 120-channel ASIC with double-threshold binary readout architecture, utilizing a quick hit cluster finding logic to provide encoded hit information for particle momentum discrimination to the Macro Pixel ASIC (MPA) at the bunch crossing rate...
The project of the LHCb upgrade foresees a replacement of the whole acquisition system of the detector to allow a full readout at 40 MHz. The development of a new control board, called the 3CU for the electromagnetic and hadronic calorimeters was proposed. This board receives commands from the main LHCb control system and sends them through the backplane to the front-end boards. Each...
We present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel serializer ASIC for detector front-end readout. LOCx2-130 consists of two serializer channels with custom encoders and each channel operates at 4.8 Gbps. The ASIC is fabricated with a commercial 130-nm CMOS process and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a bit...
Two optical link data transmission ASICs have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I upgrade. The latency of each ASIC and its corresponding receiver implemented in the back-end FPGA, are critically specified to be less than 150 ns. We present the latency measurements of two ASICs. The optical link latency measurement results indicate that both ASICs achieve their...
We present the quality assurance (QA) test of LOCx2, a low-latency, low-overhead transmitter ASIC for the ATLAS Liquid Argon Calorimeter Phase-I upgrade. In the QA test we will screen about 7000 LOCx2 chips to ensure their basic functionality. The QA test system, including two printed circuit boards, firmware, software, are under development. All tests are automatically conducted and...
A VCSEL driver ASIC, LOCld, has been designed for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade. In total about 7000 chips have been produced and are in packaging process. We present the quality assurance test aiming at screening all functional chips before they are assembled into optical transmitter modules. A detailed test procedure is proposed. A dedicated test board has been designed...
This paper reports the development of a high resolution, low power, and adjustable in frequency Time-to-Digital Converter (TDC), based on two vernier Ring Oscillators (RO) made of standard XOR cells. The TDC is aimed at exploiting the excellent timing performance of the multigap Resistive Plate Chambers (RPC). The frequency of each RO is adjustable thanks to a 9-bit register from 340MHz to...
We present two designs of a dual-channel VCSEL driver ASIC, named LOCld130 and LOCld65, aiming for the upgrade of ATLAS Liquid Argon Calorimeter. Each channel of the driver operates at 5 Gbps or 10 Gbps respectively. They are implemented in commercial 130 nm and 65 nm CMOS technologies. In typical case the 5 Gbps driver dissipates 56 mW/channel (VCSEL included) and the 10 Gbps 58 mW/channel....
Recent advances in light detectors has led to the introduction of a number of highly pixelated but compact photomultiplier tubes. These PMTs require compact readout electronics that directly couple to the PMTs, are high performance and can provide timing resolution on par with the PMT. In this paper we propose a compact readout device for the Hamamatsu H13700 PMT with 256 pixels. The design is...
Mini-EUSO is a telescope and detector designed by the JEM-EUSO Collaboration to observe the UV emission of the Earth from the vantage point of the International Space Station (ISS) in an Earth orbit of around 400 Km. The main goal of the mission is to map the Earth in the UV, thus increasing the technological readiness level of future EUSO experiments and to lay the basis for the detection of...
Readout chips of hybrid Pixel detectors use low power amplifier and threshold discrimination to sense and digitise charge deposited in semiconductor sensor. Due to variability in CMOS transistors each pixel circuit needs to be calibrated individually to achieve response uniformity. Traditionally this is addressed by programmable threshold trimming in each pixel. In this presentation a...
The ALICE Central Trigger Processor (CTP) is going to be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing Control (TTC) system based on a Passive Optical Network (PON) system. The new trigger system has been designed as dead time free and able to transmit trigger data at 9.6 Gbps. A new universal trigger board has been designed, where by changing the FMC card,...
The AdvancedTCA (ATCA) telecom industry standard has been selected as the hardware platform for the “Phase-II Upgrade” of ATLAS at the Large Hadron Collider (LHC) at CERN.
In November 2014 a project dedicated to the study of the impact of the ATCA integration in the actual counting rooms was launched analyzing the impact on the cooling infrastructures. A spare rack equipped with two ATCA...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per...
The first implementation of Machine Learning inside a Level 1 trigger system at the LHC is presented. The Endcap Muon Track Finder at CMS uses Boosted Decision Trees to infer the momentum of muons based on 25 variables. All combinations of variables represented by 2^30 distinct patterns are evaluated using regression BDTs, whose output is stored in 2 GB look-up tables. These BDTs take...
The Pixel Luminosity Telescope (PLT) is a dedicated system for luminosity measurement at the CMS experiment using silicon pixel sensors. It was installed during LS1 and has been providing luminosity measurements throughout Run 2. The online bunch-by-bunch luminosity measurement employs the "fast-or" capability of the pixel readout chip (PSI46) to quickly identify likely tracks at the full...
ATLAS Experiment has reworked and upgraded some systems during the 2014-2016 LHC shut down and the Pixel Detector has inserted an additional layer: the Insertable B-Layer. The layers 1 and 2 have been also upgraded, using the same BOC and ROD cards designed for IBL, while maintaining the detector unchanged. Now the efforts focus on the upgrade of the B-Layer and the Disks, again leaving the...
In the framework of the ALICE experiment upgrade at HL-LHC, the whole electronics of the existing Muon Tracking Chambers (MCH) will be refactored with a new frontend chip and the associated readout electronics. This paper presents the design of the dedicated concentration cards ‘SOLAR’ to ensure the readout of 30,000 frontend chips. Based on the CERN GBTx and FEAST DCDC chips, allowing to work...
This paper presents a data acquisition board associated with a beam-tagging hodoscope to be used in hadrontherapy for ion-range monitoring. The board was designed to couple to a 64-channel multi-anode photomultiplier, and to meet the hodosope’s requirements: 1-mm spatial resolution and 1-ns temporal tagging resolution, with 100-MHz counting rate capability. It mainly consists of two 32-channel...
With ever-increasing luminosity at the LHC, optimum online data selection is getting more and more important. While in the case of some experiments (LHCb/ALICE) this task is being completely transferred to computer farms, the others - ATLAS/CMS - will not be able to do this in the medium-term future for technological, detector-related reasons. Therefore, these experiments pursue the...
The CRU (Common Readout Unit) is the new readout card that will be used in ALICE during Run 3.The card will receive detector data and it will store the information in the memory of the PC through DMA. To handle the high data throughput an Altera Arria 10 FPGA has been installed on the CRU.A custom DMA controller has been developed to optimize the DMA data transfer reducing the CPU utilization....
A LED (Light Emitting Diode) based directional lighting has been designed to indicate the best evacuation direction for applications like the LHC tunnel. The design includes constraints for redundancy required by safety systems and for components selection by radiation effects. Prototype lighting units were irradiated in CERN’s CHARM facility and were operational up to a Total Integrated Dose...
At the high-luminosity upgrade of the LHC (HL-LHC), the electromagnetic calorimeter of CMS (ECAL) will have to cope with a challenging increase in the number of interactions per bunch crossing and radiation levels. The ECAL front-end readout electronics was completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a...
At the high-luminosity upgrade of the LHC (HL-LHC), the electromagnetic calorimeter of CMS (ECAL) will have to cope with an increase in the number of interactions per bunch crossing and radiation levels. CMS implements a sophisticated two-level triggering system composed of the Level-1, instrumented by custom-designed hardware boards, and a software High-Level-Trigger. The off-detector...
We have developed a 2nd generation high resistivity CMOS process, suited for integration of complimentary pixel circuitry. High charge collection efficiency can be maintained after neutron irradiation up to 1016 neq/cm2 when applying a depletion voltage to the backside of the 50 µm thick devices. Results measured with a 15 µm MAPS detector, fabricated in this technology, will be...
The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40-80 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS...
A testbeam telescope, based on the ATLAS IBL silicon pixel modules, has been built to investigate the possibility of using the CMOS technology in the HL-LHC upgrade of ITk. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between different front-ends and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed...
The ATLAS first-level Endcap Muon trigger in LHC Run-3 will
identify muons by combining data from the Thin-Gap chamber detector (TGC) and a new detector, called the New-Small-Wheel (NSW). In order to handle data from both TGC and NSW, new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger...
The Silicon Vertex Detector of the Belle II Experiment at the KEK in Tsukuba, Japan, consists of 172 double-sided strip sensors. They are read out by 1748 APV25 chips, and the analogue data are sent out of the radiation zone to 48 modules which convert them to digital. FPGAs then compensate line signal distortions using digital finite impulse response filters and detect data frames from the...
A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics was developed to test and validate the architecture of front-end driver (FED) firmware. The emulation, implemented on the CERN GLIB uTCA platform, drives optical transmitters to the back-end electronics. The firmware emulates the complex functions of the readout chips and Token Bit Managers and allows for...
During first long stoppage (LS1) of the LHC, the Central Trigger Processor (CTP) of the ATLAS experiment has been upgraded. In addition to enriched functionality, it resulted in increasing the CTP input-output latency by 75 ns (3 cycles@40 MHz). The ALFA triggers were no longer early enough to contribute to the global ATLAS triggering. A dedicated input board, speeding up the ALFA signal...
The contribution shows possibilities of the readout for Timepix3 (Ethernet Embedded Readout Interface for Timepix3 – called Katherine) for a wide range of applications. The architecture and features of the system are described in detail. The stress is laid on the usage of more readouts in a telescope configuration, where more Timepix3 sensors are operated and their time-dependent functions are...
We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS muon spectrometer. The processor will fit candidate muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an...
This paper will present the irradiation test results performed on the first two prototypes (MPW1 and V2) for the new readout ASIC (SAMPA). The SAMPA chip is aimed to be used in the ALICE Time Projection Chamber detector (TPC) and ALICE Muon Chamber (MCH) detector during RUN3 starting in 2021. The irradiation tests have been performed using proton beams of 180 MeV.
KALYPSO is a 1D imaging detector with 10 MHz frame-rate developed for high repetition-rate experiments, such as electro-optical beam profile measurements with sub-ps resolution at ANKA and Eu-XFEL. KALYPSO consists of a Si or InGaAs microstrip sensor coupled to a front-end readout, integrated with an FPGA readout card. A Low Gain Avalanche Diode (LGAD) sensor is being developed to improve the...
A next generation control infrastructure to be used in Advanced TCA (ATCA) blades at CMS experiment is being designed and tested. Several ATCA systems are being prepared for the High-Luminosity LHC (HL-LHC) and will be installed at CMS during technical stops. The next generation control infrastructure will provide all the necessary hardware, firmware and software required in these systems,...
Upgrades over the next decades will enable LHC to operate at a higher luminosity (HL-LHC). Accordingly, the optical links designed to transmit collision data should be hardened against increased radiation levels, allowing for a reliable communication. This paper studies fibre cabling design of a generic link between the in-detector optical front-end and the counting room. The proposed solution...
Readout Electronics for the First Large HV-MAPS Chip for Mu3e
Mu3e is an upcoming experiment searching for charged lepton flavor violation in the rare decay mu->eee. A silicon pixel tracker based on 50 um thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1T magnetic field will deliver precise vertex and momentum information. The MuPix HV-MAPS chip combines pixel sensor cells...
The CASCA is a 32-channal readout ASIC designed for the TPC based X-ray Polarimeter (XTP). We propose a prototype Readout system of the CASCA chip for the XTP. The system mainly consists of three kinds of modules. The ASIC cards, mounted with CASCA chip, are designed for sampling XTP signals. The Adapter card, edged-mounted with the ASIC card, is in charge of digitizing the output from ASIC...
The instantaneous luminosity of the LHC at CERN will be increased up to a factor of seven with respect to the original design value to explore higher energy scale. The first station of the ATLAS muon end-cap Small Wheel system need to replaced by a New Small Wheel (NSW) detector. The NSW provide precise track segment information to the muon Level-1 trigger to reduce fake triggers. This...
For the LS2 upgrade of the ITS detector in the ALICE experiment at the LHC,
a novel pixel detector chip, the ALPIDE chip, has been developed. In the event
of busy ALPIDE chips in the ITS detector, the readout electronics may need
to take appropriate action to minimize loss of data. A lightweight, statistical
simulation model for the ALPIDE/ITS has been designed using the...
In the context of the ATLAS Phase-II upgrade, new front-end electronics is developed, which reads out the detector at higher bandwidth due to finer granularity and higher occupancy.
Because of the high bandwidth requirements, new concepts are needed for the ATLAS ITk readout system. A new scalable approach based on many rather simple nodes is proposed to support lab setups, testing sites as...
During the ATLAS Phase-I upgrade, the global feature extractor (gFEX) will be designed to maintain the trigger acceptance against the increasing luminosity for the ATLAS Level-1 calorimeter trigger system. The prototypes v1 and v2 have been designed and tested in 2015 and 2016 respectively. With the lessons learned, a pre-production board with three UltraScale+ FPGAs and one ZYNQ UltraScale+,...
The End-Of-Substructure Card (EoS) is the interface between the building block of the ITk Strip Tracker and the outside world. All the control and command signals, the data and the power will be passing through it. The card concept is built around using the lpGBT chip set and the VTRx optical link. The EoS will handle up to 28 640 MBit data links and 10 GBit Downlinks and Uplinks. It will be...
In order to accommodate new back-end electronics of upgraded CMS sub-detectors, a new FEROL40 card in the microTCA standard has been developed. The main function of the FEROL40 is to acquire event data over multiple point-to-point serial optical links, provide buffering, perform protocol conversion, and transmit multiple TCP/IP streams (4x 10Gbps) to the Ethernet network of the aggregation...
Our work aims at improving the performances of the NA62 low-level trigger implementing a real-time stream processing architecture based on an orchestrated combination of heterogeneous computing devices (CPUs, FPGAs and GPUs).
To enable it we devised NaNet, a FPGA-based PCI-Express Network Interface Card with processing and GPUDirect capabilities, which supports multiple link technologies...
The LHCb experiment is currently engaged in an upgrade effort that will implement a trigger-less 40 MHz readout system. The upgraded Front-End Electronics profits from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new and final version of the firmware core that transmits slow control information from the...
The TrainBuilder is an ATCA based data acquisition system developed at the STFC Rutherford Appleton Laboratory to provide readout for each of three Mega-pixel detectors at the European-XFEL Hamburg. Each Train Builder system constructs over 5,000 detector images per second using FPGAs with DDR2 data buffering and an analogue crosspoint switch architecture; thereby processing 10 GBytes/sec of...
To cope with large amount of data and high event rate expected from the planned High-Luminosity LHC (HL-LHC) upgrade, the ATLAS monitored drift tube (MDT) readout electronics will be replaced. In addition, the MDT detector will be used at the first-level trigger to improve the muon transverse momentum resolution and reduce the trigger rate. A new trigger and readout system has been proposed....
Yet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb/s bandwidth of the next generation readout chip in development by the RD53 collaboration for...
