Conveners
Readout: Front-end electronics: Tuesday Early
- Frederic Nolet (Université de Sherbrooke)
- Christophe De La Taille (OMEGA (FR))
Readout: Front-end electronics: Tuesday Late
- Jean-Francois Pratte (Université de Sherbrooke)
- Paul Leroux (KU Leuven (BE))
Readout: Front-end electronics: Thursday Middle
- Leonid Kurchaninov (TRIUMF (CA))
- Jean-Francois Pratte (Université de Sherbrooke)
Description
Zoom Room: TIPP2021 Parallel Room 1
(see e-mail sent to registered participants for connection details)
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Hongtao Yang (Lawrence Berkeley National Lab. (US))25/05/2021, 05:30Readout: Front-end electronicsParallel session talk
The ITkPix-V1 readout front-end (FE) chip, based on 65 nm CMOS technology, is designed by the RD53 collaboration as the pre-production chip for the upgraded ATLAS Inner Tracker Pixel detector operating with extreme rates and radiation at the High-Luminosity LHC. The ITkPix-V1 chip uses a novel differential analog FE design featuring low noise and small time-walk. ITkPix-V1 was submitted in...
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Mr Takuto Kosaka (Iwate University)25/05/2021, 05:48Readout: Front-end electronicsParallel session talk
We currently developed a new front-end electronics for a liquid argon time projection chamber (LAr-TPC) detector, which has been developed for neutrino oscillation and nuclear decay search experiments.
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We developed the electronics (LTARS 2018) to have a wide dynamic range for input charge up to 1600 fC and a function to output a signal with an appropriate time constant for signals having... -
Shanshan Gao (Brookhaven National Laboratory (US))25/05/2021, 06:06Readout: Front-end electronicsParallel session talk
As the leading-edge international experiment for neutrino science and proton decay studies, Deep Underground Neutrino Experiment (DUNE) is based on the LArTPC technology. The first 10-kton DUNE far detector module will employ wired-based anode planes with cold readout electronics (CE) installed inside the cryostat. The CE developed for cryogenic temperatures (77K-89K) operation is an optimal...
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Flavio Loddo (Universita e INFN, Bari (IT))25/05/2021, 06:24Readout: Front-end electronicsParallel session talk
The Phase-2 upgrades of ATLAS and CMS will require a new tracker with readout electronics operating in extremely harsh radiation environment and high data rate readout.
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The RD53 collaboration, a joint effort between the ATLAS and CMS experiments, developed in 2017 a large size demonstrator, called RD53A, to qualify the chosen 65nm CMOS technology and compare different analog front-ends and... -
Devanshu Kiran Panchal (University of Texas at Austin (US))25/05/2021, 06:42Readout: Front-end electronicsParallel session talk
To meet new TDAQ buffering requirements and withstand the high expected radiation doses at the high-luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. Developments of low-power preamplifiers and shapers to meet low noise and excellent linearity requirements are ongoing in 130nm CMOS technology. In order to digitize the analogue signals on two gains after...
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Mateus Vicente Barreto Pinto (CERN)25/05/2021, 09:30Readout: Front-end electronicsParallel session talk
An alternative pixel-detector hybridization technology based on Anisotropic Conductive Films (ACF) is under development to replace the conventional fine-pitch flip-chip bump bonding. The new process takes advantage of the recent progress in industrial applications of ACF and is suitable for time- and cost-effective in-house processing of single devices. This new bonding technique developed can...
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281. Performance of the "IRSX" multi-GSa/s, Switched Capacitor Array Waveform Sampling Frontend ASICOskar Hartbrich (University of Hawaii at Manoa)25/05/2021, 09:48Readout: Front-end electronicsParallel session talk
The "Ice Ray Sampler X" (IRSX) is a low-power 8-channel waveform sampling frontend ASIC designed for HEP applications, fabricated by TSMC in a 250nm CMOS process. Each input channel samples into a switched capacitor array (SCA) of 32,768 samples depth at an adjustable rate of 2-4GSa/s, for an effective sample buffer depth of 8-16μs. Stored samples can be digitised with 12bit resolution using...
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Andrea Fabbri (INFN - National Institute for Nuclear Physics)25/05/2021, 10:06Readout: Front-end electronicsParallel session talk
In this work we present a low noise high speed readout electronics for large area Silicon Photomultipiers (SiPMs) to be used in a cryogenic environment. The board is able to manage the signals coming from a ~ 25 cm$^2$ SiPM tile, showing <10% SPE resolution and wide dynamic. The sub-nanosecond timing properties make them suitable to work with the typical mixtures of Liquid Scintillators...
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Mr Matias Senger (Universitaet Zuerich (CH))25/05/2021, 10:24Readout: Front-end electronicsParallel session talk
We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of 100x100 µm², where the sensors are LGADs. The long term focus is towards a possible replacement of disks in the extended forward pixel system (TEPX) of the CMS experiment during the HL-LHC. The requirements for this ASIC are...
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Sergio Rescia25/05/2021, 10:42Readout: Front-end electronicsParallel session talk
Silicon Photomultipliers (SiPMs), used for light detection in Noble Liquid Time Projection Chambers (TPCs), can be ganged as good spatial resolution is not needed in the light detection. Thus, the detector capacitance seen at the input of the SiPM readout electronics is larger than any previous detector arrangement: from 5 to 12.5 nF. We propose an integrated readout system suitable for...
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Mohsine Menouni (Centre National de la Recherche Scientifique (FR))27/05/2021, 07:30Readout: Front-end electronicsParallel session talk
The RD53 collaboration has been working since 2014 on the development of pixel chips for CMS and ATLAS phase 2 upgrades. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50×50 μm2.
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The RD53B chip is designed to be robust against the Single Event Upset (SEU), allowing such a complex chip to... -
Mr Keven Deslandes (Université de Sherbrooke)27/05/2021, 07:48Readout: Front-end electronicsParallel session talk
The nEXO experiment requires a low-radioactivity and cryogenically compliant interconnect medium for its photodetection tile modules. The pursued tile size is 100 cm$^2$ which is larger than what is available with commercial interposers. We made a partnership with the IZM Fraunhofer institute to develop a custom technology. In Fall 2019, an 8" full scale wafer has been designed at Sherbrooke....
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Massimo Manghisoni (Universita and INFN (IT))27/05/2021, 08:06Readout: Front-end electronicsParallel session talk
This work describes the first experimental results from the characterization of a 32 channels mixed-signal processor developed for the readout of lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment to search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon...
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Yuxiang Guo (University of Michigan), Yuxiang Guo (University of Michigan (US))27/05/2021, 08:24Readout: Front-end electronicsParallel session talk
The monitored drift tube (MDT) chambers are the main component of the precision tracking system in the ATLAS muon spectrometer, capable of measuring the sagitta of muon tracks to an accuracy of 60 μm, which corresponds to a momentum accuracy of about 10% at pT=1 TeV. To cope with large amount of data and high event rate at HL-LHC, the present MDT readout electronics will be replaced and the...
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Matthew Noy (CERN)27/05/2021, 08:42Readout: Front-end electronicsParallel session talk
The High Granularity Calorimeter (HGCAL) will replace the CMS endcap calorimeters for the High Luminosity phase of LHC and will feature 6 million channels. The requirements of the front-end electronics are extremely challenging: high dynamic range (0-10 pC), low noise (~2000e- to allow MIP calibration through to end-of-life), pileup mitigation through 25 ps binning timestamping within a power...
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