Front End Electronics (FEE 2014)

19 May 2014, 18:00 → 23 May 2014, 18:00 US/Central

Energy Sciences Building (Argonne National Laboratory)

grzegorz deptuch (fnal)

FEE2014 meeting will provide an opportunity to discuss the front-end electronics for future HEP experiments as well as for upgrades to existing ones, for astrophysics, medical instrumentation, photon science and in the field of CMOS Monolithic Active Pixel Sensors. The FEE2014 meeting will be an excellent opportunity to discuss these developments and exchange new ideas. Meeting themes will include: - Front-end circuits and signal processing for particle physics, photon science, nuclear, medical and space applications; - Monolithic Active Pixel Sensors (MAPS); - Vertical integration processes and fine-pitch interconnection techniques; - Homogeneous and heterogeneous 3D integrated circuits; - SOI detectors; - Deep submicron technologies and radiation tolerance.

Argonne Site Map Site_Map.pdf

Fermilab Site Map Fermilab_Site_Map.pdf

Monday 19 May

18:00 → 21:00 Welcome Reception

Tuesday 20 May

08:00 → 08:20 Registration

08:20 → 08:40 Introduction

Speaker: Marcel Demarteau (Fermi National Accelerator Lab. (US))

08:40 → 09:40 X-Ray Detectors: Status and Future Needs

Speaker: Mark Rivers (The University of Chicago CARS)

Slides

• gt_6_apr07_a_00L_b.mpg
• PA9_furnace_on.mpeg
• pa9_tomo.mpg
• Rivers_talk.pptx

09:40 → 10:55 Photon Science Session I

Convener: Valerio Re (Universita e INFN (IT))

09:40 XFEL Chip Development

Speaker: Mr Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

Slides MJFrench_v1.1_FEE2014_LPD_Chip_Development.pdf MJFrench_v1.1_FEE2014_LPD_Chip_Development.pptx

10:05 ePix Family Readout Chips

Speaker: Angelo Dragone (SLAC)

Slides DragoneFEE05-20-2014.pptx

10:30 AGIPD-System

Speaker: Ulrich Trunk (DESY)

Slides AGIPD-System.pdf AGIPD-System.pptx

10:55 → 11:25 Break & Poster Session

10:55 CMOS ASICs for MicroBooNE and LBNE

Speaker: Hucheng Chen (Unknown)

10:55 Development of MAPS Based Telescope for Neutron Spectroscopy

Speaker: Maciej Kachel (IPHC Strasbourg)

10:55 DSSC-System

Speaker: Matteo Porro (Max Planck Institut fuer Extraterrestrische Physik)

10:55 Jungfrau and Gotthard: charge integrating detectors with automatic gain switching for SwissFEL

Speaker: aldo mozzanica (PSI)

10:55 Self-Triggered Front-End ASIC for ATLAS Muon Upgrade

Speaker: Gianluigi De Geronimo (Brookhaven National Laboratory (US))

10:55 Serial Powering for Silicon Strip Detectors

Speaker: Mitchell Franck Newcomer (University of Pennsylvania (US))

FEE2014SerialPowerPoster2.pdf

10:55 Time-Based Silicon Strip Readout ASIC for the PANDA Detector at FAIR

Speaker: A Goerres (FZ Juelich-Germany)

10:55 VIPRAM

Speaker: Siddhartha Joshi (FNAL)

11:25 → 13:05 Photon Science Session II

Convener: Valerio Re (Universita e INFN (IT))

11:25 2nd Generation Cameras for LCLS and the New Challenges of High Repetition Rates at LCLS-II

Speaker: Sven Herrmann (SLAC)

Slides 2nd_Gen_cameras_for_LCLS.pdf

11:50 MÖNCH, a small pitch, integrating hybrid pixel detector for X-ray applications

Speaker: Dr Roberto Dinapoli (Paul Scherrer Institut)

Slides Dinapoli_FEE14.ppt

12:15 SOPHIAS for the X-ray Free-Electron Laser Experiments: Lessons and Outlook of SOI Pixel Process

Speaker: Takaki Hatsui (RIKEN)

12:40 Development of ToT-based Front-end Circuits for X-ray/gamma-ray Imaging Applications

Speaker: Kenji Shimazoe (The University of Tokyo)

Slides FEE2014.pdf FEE2014.pptx

13:05 → 14:10 LUNCH

14:10 → 15:25 LHC Session I

Convener: Mr Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

14:10 The RD53 Project: Pixel Readout Chips for Extreme Rate and Radiation

Speaker: Valerio Re (U.Bergamo)

Slides Re_RD53_FEE14.pdf Re_RD53_FEE14.pptx

14:35 CMS Pixel ROC Development

Speaker: Frank Meier Aeschbacher (University of Nebraska, Lincoln)

Slides praesFEE2014meier.pdf

15:00 Pixels for HL Upgrade of CMS

Speaker: Farah Fahim (Fermilab)

Slides CMS%20PIXEL%20Test%20Chip%20FCP130.pptx

15:25 → 15:55 Break / Poster Session

The posters that were included in the 10:45 session will continue to be displayed.

15:55 → 17:35 LHC Session II

Convener: Mr Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

15:55 QIE 10 and 11 Readouts

Speaker: Tom Zimmerman (Fermilab)

Slides QIE_FEE_talk.pdf QIE_FEE_talk.pptx

16:20 CMS Binary Chip Development for Outer Tracker

Speaker: Mark Prydderch (STFC Rutherford Appleton Lab)

Slides CMS_Binary_Chip_Development_FEE2014.pptx

16:45 ABC130 - Silicon Strip Readout Chip for ATLAS Inner Tracker Upgrade

Speaker: Krzysztof Piotr Swientek (Fac. of Phys. & Applied Comp. Sci.-AGH Univ. of Science & Techn)

Slides ABC130_Swientek_AGH.pdf

17:10 The Timepix3 readout chip for hybrid pixel detectors

Speaker: Massimiliano De Gaspari (CERN)

Slides MDeGaspari_FEE2014.pdf

18:30 → 21:00 Dinner

Wednesday 21 May

08:30 → 09:30 Quanta Image Sensor (QIS) - an oversampled visible light sensor

Analytical and experimental results with the Digital Integration Sensor (DIS) and with the Quanta Image Sensor imaging concepts, including dynamic range extension and realization, are reported. The “quantized” DIS (qDIS) concept is also proposed. The continuum between the conventional CMOS APS, the DIS, the qDIS and the QIS is discussed as a sort of roadmap, along with trades in power and performance enhancement. Imaging performance metrics of single-bit and multi-bit photo-electron-counting Quanta Image Sensors (QIS) are analyzed using Poisson arrival statistics. Signal and noise as a function of exposure are determined. Simulation of binary data acquisition and image formation was performed. Initial analysis and simulation of a readout signal chain has been performed and bounds on power dissipation established. Photodetector device concepts have been explored using TCAD. The D-log H characteristic of single-bit sensors including overexposure latitude is quantified. Linearity and dynamic range are also investigated. Read-noise-induced bit-error rate is analyzed and a read-noise target of less than 0.15 e- rms is suggested.

Speaker: Eric Fossum

Slides 2014_Argonne_Nat_Lab_May_QIS.pdf

09:30 → 10:45 MAPS Session I

Convener: Gianluigi De Geronimo (Brookhaven National Laboratory (US))

09:30 3D MAPS

Speaker: Lodovico Ratti (University of Pavia)

Slides ratti_FEE14.pdf ratti_FEE14.pptx

09:55 Ultra Low-Power, CSA Based MAPS for ALICE Upgrade

Speaker: Magnus Mager (CERN)

Slides mmager.pdf

10:20 Experience from Construction and Operation of the First Vertex Detector Based on MAPS

Speaker: Leo Greiner (Lawrence Berkeley National Laboratory)

Slides 2014_05_FEE_2014_PXL_MAPS_detector_LG.ppt

10:45 → 11:15 Break / Poster Session

The posters that were included in Tuesday's 10:45 session will continue to be displayed.

11:15 → 12:55 MAPS Session II

Convener: Gianluigi De Geronimo (Brookhaven National Laboratory (US))

11:15 Fully Depleted MAPS in Standard CMOS

Speaker: Tomasz Hemperek (Universitaet Bonn (DE))

Slides DMAPS_-_FEE_2014_-_21.05.2014.pdf

11:40 Progress in High Voltage MAPS

Speaker: Ivan Peric (Ruprecht-Karls-Universitaet Heidelberg (DE))

Slides FEE_2014.pptx

12:05 PERCIVAL CMOS Imager

Speaker: Iain Sedgwick (RAL/STFC)

Slides FEE_2014_Sedgwick_v0_5.pptx

12:30 MAPS for ALICE Upgrade and Beyond

Speaker: Frederic Morel (IPHC/CNRS/IN2P3)

Slides FEE_2014_MOREL.pdf FEE_2014_MOREL.pptx

12:55 → 13:15 Group Photo

13:15 → 14:00 LUNCH

14:00 → 15:00 Low Power Robust Design of FinFET-based Circuits using a Technology-Circuit Co-optimization Approach

Transistor scaling has been the main driving force for the success of the semiconductor industry for the past several decades. However, sustaining the benefits of scaling with conventional bulk MOSFETs has proved to be extremely challenging due to prohibitively large increase in short channel effects and sensitivity to process variations. As a result, alternative technologies with higher scalability are being explored, amongst which FinFETs have emerged as the most promising substitute for the standard transistors. However, FinFETs have their own limitations and design issues like width quantization and higher front end capacitance due to their non-planar structure. Hence, using FinFETs as a drop-in replacement for the bulk MOSFETs is expected to yield sub-optimal designs. In order to harness the full potential of FinFETs, there is a need to explore technology-aware circuit design techniques, which utilize the unique features of FinFETs to achieve superior design solutions. In this talk, I will present several such techniques with a focus on low power robust design of memories and digital logic. I will start my talk by introducing the device structure and characteristics of FinFETs and the circuit implications of making a transition from bulk MOSFETs to FinFETs. I will, then, present technology-circuit co-design techniques based on symmetric and asymmetric spacer optimization, asymmetric source/drain doping, fin orientation and independent gate control of FinFETs. I will highlight the importance of considering device-circuit interactions to achieve higher energy efficiency and stability of FinFET-based memories and logic. I will also briefly discuss the implications of some of the techniques on analog circuit design. Finally, I will present the simulation framework that we have developed for FinFET-based circuits in sub-10nm technologies and discuss its key features.

Speaker: Prof. Sumeet Gupta (Penn State)

Slides FinFET_Circuits_Talk_Gupta_FEE2014.ppsx

15:00 → 15:25 3D Integration Session I

Convener: Takaki Hatsui (RIKEN)

15:00 3D Integrated Circuits at Fermilab

Speaker: Dr Grzegorz Deptuch (Fermi National Accelerator Lab. (US))

Slides EE2014_deptuch_white_slides_hr.pdf

15:25 → 15:45 Break / Poster Session

The posters that were included in Tuesday's 10:45 session will continue to be displayed.

15:45 → 16:35 3D Integration Session II

Convener: Takaki Hatsui (RIKEN)

15:45 Towards a 3D AGIPD

Speaker: Alessandro Marras (Deutsches Elektronen-Synchrotron)

Slides Marras_FEE14.vlr_v0.6.pdf

16:10 3D CMOS Sensors with Two Layers in the 180nm Tower/Jazz Process

Speaker: Wojciech Dulinski (Institut Pluridisciplinaire Hubert Curien (FR))

Slides dulinski_FEE-2014.pdf dulinski_FEE-2014.ppt

16:35 → 17:35 SiPM Session I

Convener: Takaki Hatsui (RIKEN)

16:45 SiPM ROC Chips for Fast Timing Applications

Speaker: Nathalie Seguin-Moreau (OMEGA/CNRS/IN2P3)

Slides SiPM_ROC_FEE14.pdf

17:10 Large Scale CMOS Single-Photon Detector Arrays for PET Applications

Speaker: Mr Augusto Carimatto (TU-DELFT)

Slides FEE2014_v4_released.pptx

17:35 → 21:00 Dinner

Dinner will take place at Chuck's BBQ

Thursday 22 May

08:30 → 09:45 Timing Session

Convener: Pawel Grybos (AGH University of Science and Technology)

08:30 Deep‐Sampling CMOS Digitizers

Speaker: Gary Varner (University of Hawaii)

Slides Varner_FEE_DepthSCA_May2014.pdf

08:55 Development of FE ASICS for Tof-pet with SiPM

Speaker: Peter Fischer (Heidelberg University)

Slides Talk_FEE_PETTiming.pptx

09:20 Proton Tomography Using Silicon Strip Detectors Including the Custom ASIC Design for this Applicaiton

Speaker: Robert Johnson (University of California at Santa Cruz)

Slides FEEpCT.pptx

09:45 → 10:15 Break / Poster Session

The posters that were included in Tuesday's 10:45 session will continue to be displayed.

10:15 → 11:55 Medical, Space, and Other Topics Session

Convener: Pawel Grybos (AGH University of Science and Technology)

10:15 8-bit 5-MS/s per-pixel ADC for the DSSC ASIC

Speaker: Christian Reckleben (DESY)

Slides 8bit_ADC_Thurs_1015_FFE2014.pptx

10:40 Latest Analog Memoy Developments at IRFU

Speaker: Olivier Gevin (CEA)

Slides ED_SAMPIC_av2014_last.pdf ED_SAMPIC_av2014_last.pptx

11:05 NA62 Readout Chip (TDCpix)

Speaker: Dr Gianluca Aglieri Rinella (CERN)

Slides AglieriRinella-CERN-NA62-TDCpix-OSX.pdf AglieriRinella-CERN-NA62-TDCpix-OSX.pptx

11:30 Development and Performance of Kyoto's X-Ray Astronomical SOI Pixel Sensor

Speaker: Takeshi Tsuru (Kyoto University)

Slides 20140522_FEE2014_XRPIX_v11_open.pdf

11:55 → 12:35 LUNCH

12:45 → 13:45 APS Tour

13:45 → 14:45 ANL Tour

14:45 → 15:30 Travel to Fermi

The bus will depart at approximately 2:45PM

15:30 → 18:00 Fermilab Tours

Group A:
3:35-4:35 MINOS/NOvA
4:45-5:55 SRF/Test Beam

Group B:
3:40-4:35 D0/Tevatron
4:45-5:55 WH/Linac

18:30 → 21:30 Dinner

Dinner will take place at Meson Sabika.
Transportation will be provided

Friday 23 May

08:30 → 09:20 SiPM Session II

Convener: Gary Varner (University of Hawaii)

08:30 An ASIC for TOF and DOI Measurement with SiPM Matrices

Speaker: Cristoforo Marzocca (Universita e INFN (IT))

Slides FEE14_v3.pptx

08:55 PMm² : Smart Chips for Large Area Distributed Photomultipliers

Speaker: Gisele Martin-Chassard (Omega IN2P3)

Slides GMC_FEE14.pdf

09:20 → 09:45 Advanced CMOS and Extreme Environments Session I

Convener: Gary Varner (University of Hawaii)

09:20 Pixel Readout Circuit in 40 nm CMOS

Speaker: Pawel Grybos (AGH University of Science and Technology)

Slides Grybos_Krakow_40nm_FEE2014.pdf

09:45 → 10:15 Break / Poster Session

The posters that were included in Tuesday's 10:45 session will continue to be displayed.

10:15 → 11:30 Advanced CMOS and Extreme Environments Session II

Convener: Gary Varner (University of Hawaii)

10:15 Radiation Damage Tests at 1 Grad Dose on 65 nm CMOS Transistors

Speaker: Marlon Benoit Barbero (CPPM France)

Slides Rad_damage_65nm.ppt

10:40 LArASIC4 Noise Results in Liquid Argon Long Drift Tests

Speaker: Dr Igor Kreslo (Universitaet Bern (CH))

Slides LARSIC4-1_BERN.pdf

11:05 CMOS Lifetime at 300K and at 77K

Speaker: Shaorui Li (BNL)

Slides Lifetime_FEE2014.pdf Lifetime_FEE2014.pptx

11:30 → 12:10 Summary

Speaker: Jim Hoff (Fermilab)

Slides FEE2014_Summary.V2.pptx