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Francois Vasey (CERN)21/09/2009, 14:15
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Dr Christophe de La Taille (IN2P3/LAL Orsay)21/09/2009, 14:30Oral
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Paul INDELICATO (UPMC)21/09/2009, 14:50Oral
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Etienne AUGE (IN2P3)21/09/2009, 15:10
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Dr Christophe de La Taille (IN2P3/LAL Orsay)21/09/2009, 15:30Oral
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Sergio Bertolucci (CERN)21/09/2009, 16:15
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Dr Ryosuke Itoh (KEK)21/09/2009, 17:00The HEP experiment in Japan is now stepping into the next phase. The J-PARC, which is a newly-built high intensity proton synchrotron facility, started the operation recently. A new long-baseline neutrino experiment T2K is now at the commisioning stage utilizing the beam. In parallel, the upgrade of the KEKB/Belle, the new-stage B-factory experiment at KEK, is about to start. The accelerator...Go to contribution page
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Alex Kluge (CERN)21/09/2009, 17:45The planned linear colliders - international linear collider (ILC) and compact linear collider (CLIC)- will provide electron-positron collisions in the TeV range. Due to the high energy of the passing electrons and positrons at the interaction point a large number of background particles not related to the collision are produced. Thus the detectors must identify and reject these background...Go to contribution page
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21/09/2009, 20:00
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Massimiliano Ferro-Luzzi (CERN)22/09/2009, 09:00Systems, installation and commissioningOralA review is given of possible beam failure modes at the LHC and of the strategy adopted in the LHC experiments to protect the detectors against such events. Damage limits for the detectors are discussed and, in particular, some recent experimental tests concerning the LHCb silicon microstrip vertex detector are presented.Go to contribution page
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Dr Christine HU-GUO (DRS-IPHC Strasbourg (IReS))22/09/2009, 09:45Designed and manufactured in a commercial CMOS 0.35 μm Opto process for equipping the EUDET beam telescope, MIMOSA-26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels of 576 rows and 1152 columns covering an active area of ~224 mm2. A single point resolution, better than 4 μm, is expected with a pixel pitch of 18.4 μm....Go to contribution page
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Dr Sergei Lusin (Fermilab)22/09/2009, 09:45Systems, installation and commissioningOralThe design of the CMS power distribution system plays a major role in the ultimate noise performance of detector, both from the perspective of internally generated noise and of noise coupling between subdetectors. Noise considerations in a detector power system depend strongly on the mechanical configuration of the detector and the cabling and grounding conventions used. This talk will...Go to contribution page
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Mrs Cristina Fernandez Bedoya (Cent.de Investigac.Energeticas Medioambientales y Tecnol. (CIEMAT))22/09/2009, 10:10Systems, installation and commissioningOralAfter several months of completing the installation and commissioning of the CMS (Compact Muon Solenoid) DT (Drift Tube) electronics, the system has finally been operated under magnetic field during the so-called CRAFT (Cosmic Run at Four Tesla) exercise. Over 4 weeks, the full detector has been running continuosly under magnetic field and achieved to acquire up to 300 million cosmic muons....Go to contribution page
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Thanushan Kugathasan (INFN – Sezione di Torino, Università di Torino)22/09/2009, 10:10ToPix 2.0 is a prototype in a CMOS 0.13 μm technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 μW/cell). In an area of by 100 μm×100 μm each cell incorporates the...Go to contribution page
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Ms Rebecca Coath (STFC - Rutherford Appleton Laboratory)22/09/2009, 11:00We will present recent developments from two projects targeting advanced pixel architectures for scientific applications. Results will be reported from test structures demonstrating variants on a 4T pixel architecture. The variants include differences in pixel and diode size, the in-pixel source follower transistor size and the capacitance of the readout node to optimise for low noise and...Go to contribution page
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Dr Valeria Sipala (Dipartimento di Fisica - Università degli Studi di Catania & INFN sez Catania)22/09/2009, 11:00Systems, installation and commissioningOralNew developments in the proton-therapy field for cancer treatments, leaded Italian physics researchers to realize a proton imaging apparatus consisting of a silicon microstrip tracker, to reconstruct the proton trajectories, and a calorimeter, to measure their residual energy. For clinical requirements, the detectors used and the data acquisition system should be able to sustain 1 MHz proton...Go to contribution page
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Mr Daniel Charlet (Laboratoire de l''Accelerateur Lineaire (LAL) (IN2P3) (LAL))22/09/2009, 11:25Systems, installation and commissioningOralThe description of the electronic chain for the BArionicOscillation project The BAO Radio project aims at mapping the H gas distribution in the universe using the 21 cm (1420 MHz) hyperfine transition of atomic hydrogen, up to red-shifts z ~ 1.5-2. The main goal of the project is to constrain the Dark Energy properties using the BAO (Baryon Acoustic Oscillation) cosmological probe, which can...Go to contribution page
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Mr Francis Anghinolfi (CERN)22/09/2009, 11:25We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25um technology and optimized for the short, 2.5cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We obtain the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in...Go to contribution page
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Dr Gregory Hallewell (Centre de Physique des Particules de Marseille)22/09/2009, 11:50Systems, installation and commissioningOralKM3NeT is a future cubic kilometre-scale neutrino telescope for the deep Mediterranean. Several hundred vertical detection lines, each containing up to 100 optical modules with photomultipliers will be anchored to a sea floor power and data transport network. Data acquisition will minimize offshore electronics, reducing difficult and expensive maintenance operations. No off-shore triggering or...Go to contribution page
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Dr Ryo Ichimiya (KEK)22/09/2009, 11:50A pixel sensor in 0.2um Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide in a monolithic chip, has many advantages. However, it has been found that applied electric field in the sensor layer also affects transistors in the adjacent circuit layer. Thus, full depletion voltage cannot be applied. To overcome...Go to contribution page
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Dr Paschalis Vichoudis (CERN)22/09/2009, 12:15Systems, installation and commissioningOralThe CMS Preshower is a fine grain detector that comprises 4288 silicon sensors, each containing 32 strips. The raw data are transferred from the detector to the counting room via 1208 optical fibres producing a total data flow of ~72GB/s. For their readout, 40 multi-FPGA 9U VME readout boards are used. This article is focused on the commissioning of the VME readout system using two tools: a...Go to contribution page
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Prof. Wladyslaw Dabrowski (Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, Al. Mickiewicza 30, 30-059 Cracow, Poland)22/09/2009, 12:15In this paper we present the preliminary experimental results obtained with 10 µm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/µm for a minimum ionizing particle, therefore a low noise, high gain and...Go to contribution page
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Dr Wojciech Bialas (CERN)22/09/2009, 12:40Systems, installation and commissioningOralThe CMS Preshower detector, based on silicon strip sensors, was installed on the two endcaps of CMS in March/April 2009. First commissioning showed that of the 137000 electronics channels virtually all were fully operational. This report summarizes the electronics integration (on-detector) and in-situ performance in terms of noise (including common-mode pickup), channel-to-channel variations,...Go to contribution page
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Andrea Baschirotto (University of Milan-Bicocca)22/09/2009, 14:15The running CMOS technology scaling has a big impact in the design of analog circuits. Since scaled technologies offer big advantages to digital parts (reduce space, lower power consumption, etc...), complex mixed-signal systems are typically developed in the smallest minimum-gate-length technology. However these advantages for the digital part in a scaled technology correspond to a big...Go to contribution page
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Mr Vladimir Gromov (NIKHEF)22/09/2009, 15:00In a joint effort of Nikhef (Amsterdam) and University of Bonn, the Gossipo-3 IC is being developed. This circuit is a prototype of a full-reticle chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors. The chip is defined as a high granulated (55um) array in which every readout pixel is equipped with a high resolution TDC (1.6ns) covering dynamic...Go to contribution page
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Mr Michal Dwuznik (Faculty of Physics and Applied Computer Science AGH Univeristy of Science and Technology)22/09/2009, 15:00A test system developed for ABCN-25 for ATLAS Inner Detector Upgrade is presented. The system presented is based on commercial off the shelf DAQ components by NI and foreseen to aid in chip characterization and module/hybrid development complementing full custom VME based setups. The key differences from the point of software development are presented, together with guidelines for developing...Go to contribution page
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Dr Renaud Gaglione (LAPP, Université de Savoie, CNRS/IN2P3)22/09/2009, 15:25This mixed-signal circuit is a 64 channels readout R&D ASIC for Micro-Pattern Gaseous Detectors (Micromegas, Gas Electron Multiplier) or Resistive Plate Chambers. These detectors are foreseen as the active part of a digital hadronic calorimeter for a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up...Go to contribution page
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Mr Carlos Abellan Beteta (Universidad de Barcelona-Unknown-Unknown)22/09/2009, 15:25An integrated test environment for the data acquisition electronics of the Scintillator Pad Detector (SPD) from the calorimeter of the LHCb experiment is presented. It allows to test separately every single board or to perform global system tests, while being able to emulate every part of the system and debug it. This environment is foreseen to test the production of spare electronics boards...Go to contribution page
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Mrs Nathalie Seguin-Moreau (OMEGA/LAL ORSAY/IN2P3)22/09/2009, 15:50HARDROC (HAdronic Rpc Detector ReadOut Chip) is the very front end chip designed for the readout of the RPC or Micromegas foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the ILC hadronic calorimeters (1cm2 pads) implies a huge number of electronics channels (400 000 /m3) which is a new feature of “imaging”...Go to contribution page
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Mr Dominique Breton (Laboratoire de l'Accelerateur Lineaire (LAL/IN2P3/CNRS))22/09/2009, 15:50The currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The time resolution measured on the most advanced ASICs based on CFDs is of the order of 30 ps rms. TDC architectures are usually based either on a voltage ramp started or stopped by the digital pulse,...Go to contribution page
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Mr Laurent Gallin-Martel (LPSC/IN2P3 Grenoble)22/09/2009, 16:40The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35µm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the...Go to contribution page
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Dr Richard Plackett (CERN)22/09/2009, 16:40Radiation tolerant components and systemsOralWe present the first measurements of the performance of the Medipix3 hybrid pixel readout chip after exposure to significant x-ray flux. Specifically the changes in performance of the mixed mode pixel architecture, the digital periphery, digital to analogue converters and the e-fuse technology were characterised. A high intensity, calibrated x-ray source was used to incrementally irradiate...Go to contribution page
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Mitchell Franck Newcomer (Departm.of Physics & Astronomy)22/09/2009, 17:05We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at Large Hadron Collider upgrade (SLHC). IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance, low noise bipolar NPN devices, wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is...Go to contribution page
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Ms Evangelina GOUSIOU (CERN)22/09/2009, 17:05Radiation tolerant components and systemsOralThere are more than 6000 electronic cards for the instrumentation of the LHC cryogenics, housed in crates and distributed around the 27km tunnel. Cards and crates will be exposed to a complex radiation field during the 10y of LHC operation. COTS and rad-tol ASIC have been selected and individually qualified during the design phase of the cards. The test setup and the acquired data presented in...Go to contribution page
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Kostas Kloukinas (CERN)22/09/2009, 17:30Oral
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Arno Straessner (IKTP, TU Dresden)22/09/2009, 17:30Radiation tolerant components and systemsOralThe ATLAS Liquid Argon (LAr) calorimeter consists of 182,486 detector cells whose signals need to be read out, digitized and processed, in order to provide signal timing and the energy deposited in each detector element. The current readout electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years ≥2017, and will be replaced by new electronics...Go to contribution page
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Bruno Dutrey (Cadence Design Systems)22/09/2009, 17:45
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Sandro Bonacini (CERN)22/09/2009, 18:15
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Kostas Kloukinas (CERN)22/09/2009, 18:45
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Jerry Gipper (Embedify LLC)23/09/2009, 09:00From motherboard to backplane to blade based computer systems, the choices are numerous. This session will cover the markets and trends within those markets that are impacting decisions made by board suppliers. Discussion will focus on the various form factors, the development and evolution of industry standards, and the consortia that support and develop these standards, including VITA,...Go to contribution page
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40. Construction and Performance of a Double-Sided Silicon Detector Module using the Origami ConceptMr Christian Irmler (HEPHY Vienna)23/09/2009, 09:45The APV25 front-end chip with short shaping time will be used in the Super-Belle Silicon Vertex Detector (SVD) in order to achive low occupancy. Since fast amplifiers are more susceptible to noise caused by their capacitive input load, they have to be placed as close to the sensor as possible. On the other hand, material budget inside the active volume has to be kept low in order to reduce...Go to contribution page
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Gianmaria Collazuol (INFN Sezione di Pisa (INFN))23/09/2009, 09:45The TDC based integrated trigger and data acquisition system of the NA62 experiment at CERN will be presented. The system architecture, the trigger algorithm and its implementation in commercial high performance FPGAs will be described. The results of test and characterization of the custom components as well as those of extensive field tests performed on a system prototype handling up to 512...Go to contribution page
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Mr Markus Krämer (Technische Universität München)23/09/2009, 10:10In order to provide a trigger for the Primakoff reaction, in 2009, the trigger system of the COMPASS experiment at CERN will be extend by an electromagnetic calorimeter trigger. Since it was decided to gain from various benefits of digital data processing, a FPGA based implementation of the trigger, running on the front-end electronics, which are used for data acquisition at the same time, is...Go to contribution page
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Dr Anna Macchiolo (Max-Planck-Institut fuer Physik)23/09/2009, 10:10We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting vertical integration technologies developed at the Fraunhofer Institute IZM-Munich. A new Solid-Liquid-InterDiffusion technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the...Go to contribution page
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Dr Hervé Chanal (LPC Clermont-Ferrand)23/09/2009, 11:00The Level 0 Decision Unit (L0DU) is one of the main components of the first trigger level of the LHCb experiment. This 16 layers custom board receives data from the calorimeter, muon and pile-up sub-triggers and computes the level 0 decision, reducing the rate from 40MHz to 1MHz. The processing is implemented in FPGA using a 40MHz synchronous pipelined architecture. The L0DU algorithm is fully...Go to contribution page
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Mr Ashley Greenall (Department of Physics)23/09/2009, 11:00We will present the development of prototype flex hybrids and modules for the short strip layers of the ATLAS inner detector upgrade. The hybrid utilises the ABCN-25 front end readout chip, which has been optimised for the short 2.5cm strip sensor topology. The design and production choices for a high yield, low cost reliable device will be discussed. Preliminary results from the first...Go to contribution page
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Mrs Pamela Renee Klabbers (University of Wisconsin-Madison)23/09/2009, 11:25The CMS Regional Calorimeter Trigger (RCT) receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the Global Calorimeter Trigger (GCT) after processing. The RCT hardware consists of 1 clock distribution crate and 18 double-sided crates containing custom boards, ASICs, and backplanes. The electronics for the RCT have been fully...Go to contribution page
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Mr Ray Yarema (FNAL)23/09/2009, 11:25In 2008 a consortium of 15 international institutions was formed to pursue the development of 3D integrated circuits at a commercial foundry. The first MPW run from the consortium was submitted to Tezzaron. Wafers were fabricated at Chartered Semiconductor in the 130 nm process. These wafers were then assembled by Tezzaron into vertically integrated circuits. More than fifteen designs were...Go to contribution page
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Mrs Stéphanie Godiot (CPPM)23/09/2009, 11:50Facing the future challenges of hybrid pixel vertex detectors is foreseen to be done by microelectronic technology shrinking. However, this straightforward approach has some disadvantages in term of performances and cost. Based on a previous prototype of the future ATLAS pixel read-out chip FE-I4, this paper presents design and test of a hybrid pixel read-out chip using 3 dimensional...Go to contribution page
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John Morris (Queen Mary University of London)23/09/2009, 11:50The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system using custom electronics which identifies, within a fixed latency of 2.5 us, highly energetic objects resulting from LHC collisions. It is composed of three main sub-systems. The PreProcessor system first conditions and digitises approximately 7200 pre-summed analogue calorimeter signals at the bunch-crossing rate of 40...Go to contribution page
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Mr Yu Suzuki (KEK)23/09/2009, 12:15The ATLAS level1 endcap muon trigger system consists of about 4000 Thin Gap Chambers (TGC) with 320,000 input electronics channels in order to find level1 trigger candidates for muons in both endcap regions. We had already adjusted channel-to-channel timing difference in overall TGC system with 1.2ns level, and found its consistency with the observation of beam halo events in the first proton...Go to contribution page
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Mr Wojciech Dulinski (IPHC, Strasbourg)23/09/2009, 12:15On the way towards fast, radiation tolerant and ultra thin CMOS sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). The proposed prototype device is a 245x245 pixel array with a pitch of 20 µm, In the first silicon layer charge sensing diode and the input buffer amplifiers are integrated, using 0.6 µm...Go to contribution page
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Mr Ralf Spiwoks (CERN)23/09/2009, 12:40The ATLAS Level-1 Muon to Central Trigger Processor Interface (MUCTPI) receives information on muon candidates from the muon trigger sectors and sends multiplicity values to the Central Trigger Processor (CTP). The CTP receives the multiplicity values from the MUCTPI and combines them with information from the calorimeter trigger and other triggers of the experiment and makes the...Go to contribution page
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Marvin Johnson (Fermi National Accelerator Laboratory (FNAL))23/09/2009, 14:15Low common mode noise design methods for small instruments such as oscilloscopes are well known. Extending these ideas to very large systems such as detectors at the Large Hadron Collider is often not very obvious. This talk will describes methods for developing large detector designs and provide some examples of successful designs using these ideas. It will also describe some common design...Go to contribution page
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Matt Warren (UCL)23/09/2009, 15:00The existing ATLAS Level-1 trigger system is seriously challenged at the SLHC's higher luminosity. A hardware tracking trigger might be needed, but requires a detailed understanding of the detector. Simulation of high pile-up events, with various data-reduction techniques applied, will be described. Two scenarios are envisaged: (a) regional readout - calorimeter and muon triggers are used to...Go to contribution page
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Dr Satish Dhawan (Yale University)23/09/2009, 15:00Previous tests have shown that Enpirion EN5360, a 6 amp device is capable of taking sLHC radiation dosage but the input voltage is limited to a maximum of 5.5V. But from a systems point of view it is essential to have a factor of 10 in input/out voltage ratio in single stage i.e. maximum input voltage be >12 Volts. The silicon foundry that made this device can now make 12 V FETS on the same...Go to contribution page
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Mr Stefano Michelis (CERN)23/09/2009, 15:25In the context of a new power distribution scheme for SHLC tracker based on switching DC/DC converter, we are developing a custom converter able to work in the high radiation and high magnetic field environment of the experiments. Two new ASIC prototypes, in two different technologies, have been designed and manufactured. Design techniques, functional and radiation tests of the prototypes will...Go to contribution page
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Prof. Geoff Hall (Imperial College London)23/09/2009, 15:25The CMS experiment is planning a major upgrade of its tracking system to adapt to an expected increase in luminosity of the LHC accelerator to 1035 cm-2.s-1. The CMS Tracker will then have to cope with several hundred interactions per bunch crossing and fluxes of thousands of charged particles emerging from collisions. CMS requires tracker data to contribute to the first level trigger, which...Go to contribution page
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Dr Katja Klein (I. Physikalisches Institut (B))23/09/2009, 16:15The distribution of power to the CMS tracker upgrade at SLHC is challenging, as the power consumption is expected to be similar as or higher than today, while the operating voltage will decrease and the cables must remain the same. The CMS tracker has adopted parallel powering with DC-DC conversion as baseline solution to the powering problem. The current status of the implementation of...Go to contribution page
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Dr Gregory Michiel Iles (Imperial College)23/09/2009, 16:15CERN has made public a comprehensive plan for upgrading the LHC accelerator to provide increased luminosity commonly referred to as SuperLHC (SLHC). The plan envisages two phases of upgrades during which the LHC luminosity increases gradually to reach 6-7×1034 cm-2sec-1. Over the past year CMS has responded with a series of workshops and studies which have defined the roadmap for upgrading the...Go to contribution page
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Alexander Madorsky (University of Florida)23/09/2009, 16:40D. Acosta, M. Fisher, I. Furic, J. Gartner, G.P. Di Giovanni, K. Kotov, A. Madorsky, D. Wang University of Florida/Physics, POB 118440, Gainesville, FL, USA, 32611 B. P. Padley, M. Matveev Rice University, Houston, Texas The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and...Go to contribution page
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Mr Georges Blanchot (CERN)23/09/2009, 16:40The upgrade of the trackers at the sLHC experiments requires implementing new powering schemes that will provide an increased power density with reduced losses and material budget. A scheme based on buck and switched capacitors DC to DC converters has been proposed as an optimal solution. The buck converter is based on a power ASIC, connected to a custom made air core inductor. The arrangement...Go to contribution page
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Tomas Tic (RAL/ASCR)23/09/2009, 17:05Serial powering is an elegant solution to power the SLHC inner trackers with a minimum volume of cables. So far R&D on serial powering for silicon strip modules was based on discrete commercial electronics. With the delivery of the first iteration of the ABCN-25 readout chip and the SPi serial powering interface chip, custom elements of shunt regulators and transistors became available. The...Go to contribution page
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Dr John Jones (Princeton University)23/09/2009, 17:05The Matrix card is the first in what is expected to be a series of xTCA cards produced for a variety of projects at CERN, Trieste and LANL. Developed as a joint collaboration between colleagues at Princeton, Imperial College, LANL and CERN, the device comprises the latest generation of readily-available Xilinx FPGAs, crosspoint-switch technology and optical links in a 3U form factor. In this...Go to contribution page
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Mr Mario Sedita (INFN-LNS)23/09/2009, 17:30The KM3NeT EU-funded consortium, pursuing a cubic kilometre scale neutrino telescope in the Mediterranean sea, is developing technical solutions for the construction of this challenging project, to be realized several kilometres below the sea level. In this framework a proposed DC/DC power system has been designed, maximizing reliability and minimizing difficulties and expensive underwater...Go to contribution page
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Richard Philip Holt (Rutherford Appleton Laboratory)23/09/2009, 18:00
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Federico Faccio (CERN)23/09/2009, 18:15
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Fernando Arteche (Instituto Tecnológico de Aragón)23/09/2009, 18:30
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Marc Weber (Rutherford Appleton Laboratory)23/09/2009, 18:45
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Federico Faccio (CERN)23/09/2009, 19:00
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23/09/2009, 19:15
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Dr Jean-Christophe Antona (Alcatel-Lucent)24/09/2009, 09:00Optoelectronics and LinksOralIn less than forty years, optical fiber has become omnipresent to convey high volumes of information over long distances for any segment of transport network. Short reach access networks are now boosted by the advent of 10Gigabit Ethernet standards, Fiber-To-The-Home and Passive Optical Networks technologies. Longer reach (from a few hundreds up to a few thousands of kilometers),...Go to contribution page
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Dr B. Todd Huffman (Oxford University)24/09/2009, 09:45Optical fibres experience significant differences in Radiation induced absorption (RIA) depending upon the temperature environment. At the LHC upgrade there are plans in some cases to mount optical fibres on or near to cold surfaces at sub-zero temperatures. Consequently a programme of characterization of optical fibre's RIA in cold environments is essential for identification of acceptable...Go to contribution page
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Luigi Caponetto (INFN/CNRS)24/09/2009, 09:45A transient waveform sampler/recorder IC has been developed and realized in AMS C35 technology to be used in the front-end of a neutrino detector. It is based around a switched capacitors array unit sampling its voltage inputs at 200MHz external clock rate and transferring them at its outputs at 1/10th of the sampling rate. This unit is replicated inside the ASIC providing 4 independent...Go to contribution page
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Ms Selma Conforti Di Lorenzo (OMEGA/LAL/IN2P3/CNRS)24/09/2009, 10:10PARISROC is a complete read out chip, in AMS SiGe 0.35μm technology [1],for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by French national agency for research (ANR) and called PMm2:“Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles” [2]...Go to contribution page
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Prof. K.K. Gan (The Ohio State University)24/09/2009, 10:10We study the radiation hardness of 850 nm PIN/VCSEL arrays for possible deployment in the detector optical readouts for the LHC luminosity upgrades. In 2008, we irradiated two devices from several vendors to the radiation doses expected for the ATLAS silicon trackers. This leads to the identification of the best arrays from two vendors for possible deployment in a new ATLAS pixel-detector for...Go to contribution page
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Mr Sebastien Crampon (LPC Clermont Ferrand)24/09/2009, 11:00This paper describes the Analog to Digital Converter developed for the front end electronic of the IN2P3 INNOTEP project by the “pole microelectronique Rhone-Auvergne”. (Collaboration LPC Clermont-Ferrand and IPNL Lyon). This ADC is a 4 stages, 2.5 bits per stage pipe line, with open loops track and holds and amplifiers. It runs at 100MSamples/s and has 8 bits of resolution. The stages...Go to contribution page
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Mr Paulo Moreira (CERN)24/09/2009, 11:00The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planed for the SLHC the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs addresses this...Go to contribution page
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Mrs Vanessa Tocut (CNRS/IN2P3/LAL-ORSAY)24/09/2009, 11:25The SNATS chip is designed to provide both a high resolution of 70ps RMS and a large dynamic range of 53 bits. The architecture is based on the association of 32 cell delay locked loops and of a 48-bit digital counter which are synchronized to a 160 MHz external clock. A 16 channel prototype has been designed in AMS 0.35 µm CMOS technology and its main performances are a Differential...Go to contribution page
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Dr Jan Troska (CERN)24/09/2009, 11:25SLHC experiment upgrades will make substantial use of optical readout to enable high-speed data readout and control. The Versatile Link project will develop and assess optical link architectures and components suitable for deployment at SLHC. The on-detector element will be bidirectional opto-electronic module: the Versatile Transceiver that will be based on a commercially available module...Go to contribution page
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Mr Alessandro Gabrielli (CERN EP-MIC - Physics Department & INFN Bologna)24/09/2009, 11:50Here is described a novel approach to detect particles by means of a solid-state device susceptible to latchup-like effects. The stimulated ignition of latchup effects caused by external radiation has so far proven to be a hidden hazard. Here this is proposed as a powerful means of achieving the precise detection and positioning of a broad range of ionising particles. The cell can be...Go to contribution page
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Dr Ioannis Papakonstantinou (CERN)24/09/2009, 11:50In this paper we propose a generic Passive Optical Network (PON) platform for the distribution of synchronous, fast rate signals within particle physics experiments. Our aim is to demonstrate a versatile network architecture that will be able to serve one or more applications in future high energy physics (HEP) experiments. In order for the current PON systems to be adapted to future HEP...Go to contribution page
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Giovanni Mazza (INFN sezione di Torino, Italy)24/09/2009, 12:15A laser driver for data transmission at 5 Gb/s has been developed as a part of the GigaBit Transceiver (GBT) project. The GigaBit Laser Driver (GBLD) targets High Energy Physics (HEP) applications for which radiation tolerance is mandatory. The GBLD ASIC can drive both VCSELs and some types of edge emitting lasers. It is essentially composed of two drivers capable of sinking up to 12 mA each...Go to contribution page
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Francois Vasey (CERN)24/09/2009, 12:15Oral
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24/09/2009, 12:35Oral
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Mr Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)24/09/2009, 12:40This paper presents a 4.8 Gbit/s optical receiver designed in a 0.13 µm CMOS process as part of the GBT project. The receiver consists of a transimpedance amplifier (TIA) and a limiting amplifier. A differential cascode structure with inductive peaking is adopted for the TIA to achieve high gain, high bandwidth and low input referred noise. Experimental results at room temperature show an open...Go to contribution page
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Christian Piguet (Centre suisse d'Electronique et de Microtechnique SA)24/09/2009, 14:15The design of Systems-on-Chip (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description to low level consideration due to technology defaults and variations. This talk will describe some of these low level main issues, such as dynamic and static power consumption, temperature, technology variations, interconnect, DFM,...Go to contribution page
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Prof. John Richard Thome (Laboratory of Heat and Mass Transfer)24/09/2009, 15:00An overview of the author’s decade of experience with two-phase cooling research for computer chips and power electronics will be described with its possible beneficial application to high energy physics experiments. Flow boiling in multi-microchannel cooling elements in silicon (or aluminium) have the potential to provide high cooling rates (up to as high as 350 W/cm2), stable and uniform...Go to contribution page
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Mr Hugo Franca Santos (CERN)24/09/2009, 16:15This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage....Go to contribution page
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Mr Yunan FU (DRS-IPHC, University of Strasbourg, CRNS-IN2P3)24/09/2009, 16:15CMOS Monolithic Active Pixel Sensors (MAPS) combined with 3D Integrated Technologies (3DIT) offer new opportunities to meet the challenging requirements of the next generation pixel technologies. This paper presents a 3D CMOS pixel sensor design adapted to the innermost layer of the ILC vertex detector. It contains a matrix of 96x256 pixels; each integrating, in a 12µm pitch, a sensing...Go to contribution page
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Federico Alessio (CERN)24/09/2009, 16:15LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on...Go to contribution page
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Mr Fatah Rarbi (IN2P3 / LPSC Grenoble)24/09/2009, 16:15The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 32 analog channels through one analog to digital converter. A...Go to contribution page
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Mr Piotr Jurga (CERN)24/09/2009, 16:15The Timing Trigger and Control (TTC) system distributes timing signals from the LHC Radio Frequency (RF) source to the four experiments. A copy of these signals is also transmitted to a monitoring system, installed in the Control Center in Prevessin, which provides continuous measurement of parameters such as Bunch Clock jitter and frequency, Orbit period in BC counts, transmission delay over...Go to contribution page
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Mr Felix Müller (Kirchhoff Institute for Physics, University of Heidelberg)24/09/2009, 16:15A scalable multi-channel analogue signal generator is presented. It uses a commercial low-cost graphics card with multiple outputs in a standard PC as signal source. Each color signal serves as independent channel to generate an analogue signal. A custom-built external PCB was developed to adjust the graphics card output voltage levels for a specific task, which needed differential signals....Go to contribution page
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Gianmaria Collazuol (INFN Sezione di Pisa (INFN))24/09/2009, 16:15We describe a pilot project for the use of GPUs in an online triggering application at the CERN NA62 experiment, and the results of the first field tests together with a prototype data acquisition system.Go to contribution page
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Mr Vincent Pierre Delord (ISIMA-Clermont Ferrand)24/09/2009, 16:15The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid. The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. ...Go to contribution page
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Dr Alexander A. Grillo (Santa Cruz Institute for Particle Physics, University of California, Santa Cruz)24/09/2009, 16:15The upgrade of the ATLAS detector for the high luminosity upgrade of the LHC will require a rebuild of the Inner Detector as well as replacement of the readout electronics of the Liquid Argon Calorimeter and other detector components. We proposed some time ago to study silicon germanium (SiGe) BiCMOS technologies as a possible choice for the required silicon microstrip and calorimeter...Go to contribution page
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Mr Tim Armbruster (Heidelberg University)24/09/2009, 16:15The development of front-end electronics for the planned CBM experiment at FAIR/GSI is in full progress. For the charge readout of the various subdetectors a new self triggered amplification and digitalization chip is being designed and tested. The chip will have 32-64 channels each containing a low power/low noise preamplifier/shaper front-end, an 8-9 Bit ADC and a digital post-processing...Go to contribution page
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Mr Abdelkader HIMMI (DRS-IPHC, University of Strasbourg, CNRS-IN2P3)24/09/2009, 16:15The EUDET-JRA1 beam telescope and the STAR vertex detector upgrade will be equipped with CMOS pixel sensors allowing to provide high density tracking adapted to intense particle beams. The EUDET sensor Mimosa26, is designed and fabricated in a CMOS-0.35µm Opto process. Its architecture is based on a matrix of 1152x576 pixels, 1152 column-level analogue-to-digital conversion by discriminators...Go to contribution page
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Mr Eric Delagnes (CEA/Irfu)24/09/2009, 16:15The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan, for which a near detector complex (ND280), used to characterize the beam, will be built 280m from the target in the off-axis direction of the neutrino beam produced using the 50 GeV proton synchrotron of J-PARC (Japan Proton Accelerator Research Complex). The central part of the ND280 is a...Go to contribution page
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Dag Toppe Larsen (University of Bergen)24/09/2009, 16:15ALICE is a dedicated heavy-ion experiment at CERN LHC. It aims to reproduce the state of matter shortly after the Big Bang, i.e. the quark-gluon plasma. Each lead-lead collision will produce the order of ten thousand new particles. Detailed study of the event requires precise measurements of the particle tracks. An 95m3 Time Projection Chamber (TPC) with more than 500 000 read-out pads...Go to contribution page
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Dr Raffaele Giordano (Universita' di Napoli Federico II and INFN, Napoli)24/09/2009, 16:15The ATLAS Level-1 barrel muon trigger is built as a synchronous pipeline and includes some high-speed serial links in order to transfer data from the detector to the counting room. The links are based on the GLink chip-set, which transfers data with a fixed and deterministic latency. Despite its unique timing features, the production discontinued and no compatible off-the-shelf chip-sets are...Go to contribution page
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Mr Michal Bochenek (CERN)24/09/2009, 16:15After the LHC luminosity upgrade the number of readout channels in the ATLAS Semiconductor Tracker will be increased. Therefore a new solution for powering the readout electronics has to be found. The two main approaches for power distribution are under development, the serial powering of a chain of modules and the parallel powering with DC-DC conversion. In both cases...Go to contribution page
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Mr François WICEK (LAL IN2P3 CNRS)24/09/2009, 16:15The ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%. The architecture is based on a double correlated sampling. 2 methods have been investigated: differential output Dual Slope Integrator which has been chosen to be the LSST baseline and...Go to contribution page
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Dr Peter Vankov (University of Liverpool)24/09/2009, 16:15The ATLAS experiment at the CERN Large Hadron Collider (LHC) has started taking data last autumn with the inauguration of the LHC. The SemiConductor Tracker (SCT) is the key precision tracking device in ATLAS, made up from silicon micro-strip detectors. The completed SCT has been installed inside ATLAS. Since then the detector was operated for many months under realistic conditions....Go to contribution page
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Mr Matt Warren (UCL)24/09/2009, 16:15The ATLAS Tracker Upgrade project is developing large modules of up to two hybrids each. Each hybrid comprises two columns of ABCN-25 readout ASICs, each with a data rate twice the bunch-clock. A hybrid readout link thus handles two streams at quadruple the bunch-clock rate. To allow hybrids to operate at different potentials (as required by serial-powering), control signals make use of a...Go to contribution page
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Mr Sergio Silva (CERN)24/09/2009, 16:15In the context of the versatile link project, a set of semiconductor lasers were studied and modeled aiming at the optimization of the laser driver circuit. High frequency measurements of the laser diode devices in terms of reflected and transmission characteristics were made and used to support the development of a model that can be applied to study their input impedance characteristics and...Go to contribution page
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Andre Konrad Kruth (Physikalisches Institut der Universität Bonn, Nussallee 12, D - 53115 Bonn, Germany)24/09/2009, 16:15FE‐I4 is the 130nm ATLAS pixel IC currently under development for upgraded LHC luminosities. FE‐I4 is based on a low‐power analog pixel array and digital architecture concepts tuned for higher hit rates. An integrated PLL has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40MHz bunch crossing reference. This block is designed for low‐power,...Go to contribution page
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Mr Alexey Kozyrev (BINP)24/09/2009, 16:15The cryogenic magnetic detector CMD-3 developed for experiments on elektron-pozitronnom collider VEPP-2000 is under construction at Budker Institute of Nuclear Physics now. This paper describes the modules which are forming an infrastructure and datapath of the First Level Trigger (FLT) of CMD-3. There are few types of modules specially developed for detector subsystems. These modules are...Go to contribution page
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Mikhail Matveev (Rice University)24/09/2009, 16:15The Endcap Muon (EMU) Cathode Strip Chamber (CSC) sub-detector at the CMS experiment at CERN has been fully installed and operational since summer of 2008. The system of 180 optical links connects the middle and upper levels of the CSC Level 1 Trigger chain. Design and commissioning of all optical links presents several challenges, including reliable clock distribution, link...Go to contribution page
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Dr Fernando Arteche (Instituto Tecnológico de Aragón)24/09/2009, 16:15This paper presents a detailed and comparative analysis from the electromagnetic compatibility point of view of the proposed power distributions for the SLHC tracker up-grade. The main idea is to identify and quantify the noise sources, noise distribution at the system level and the sensitive areas in the front-end electronics corresponding to both proposed topologies: The DC-DC converter...Go to contribution page
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Mr Jan Scheirich (Charles University in Prague, Faculty of Mathematics and Physics)24/09/2009, 16:15The Mini-matrix readout system is being developing for measuring characteristics of a small (3.5 x 3.5 mm) prototype of a DEPleted Field Effect Transistor (DEPFET) sensor for particle detection. The small sensor will have 8 x 6 active pixels allowing studies of the DEPFET structure behaving and processes during sensor operation. The Mini-matrix readout setup should allow us to make a precision...Go to contribution page
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Mr Szymon Kulis (Fac. of Phys. & Applied Comp. Sci.-AGH Univ. of Science & Techno)24/09/2009, 16:15The design and preliminary measurement results of a prototype 10 bit pipline ADC for the Luminosity Detector (LumiCal) at the International Linear Collider (ILC) are presented. The motivation for the chosen architecture is presented and followed by the description of the core blocks. The prototype was fabricated in 0.35 um CMOS technology. The preliminary measurements of static (INL, DNL) and...Go to contribution page
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Mr Wim Beaumont (Universiteit Antwerpen)24/09/2009, 16:15The CMS CASTOR detector is a small calorimeter located at 14.3 meters from the interaction point behind the HF detector. The CASTOR project was only approved mid of 2007. Cherenkov radiation in a sampling structure is used to measure the energy as the HF does. Logically one would use the same readout hardware as used for HF. But also other architectures were considered. Given the...Go to contribution page
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Georgi Leshev (Labor fur Hochenergiephysik)24/09/2009, 16:15The challenging constraints on the design of the Electromagnetic Calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment, such as rigorous temperature and voltage stability, imposed the development of a complex Detector Control System (DCS). In this paper the final layout and functionality of the CMS ECAL DCS are presented and the operational experience during the detector's...Go to contribution page
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Mr Claudio Bortolin (Universita degli Studi di Udine)24/09/2009, 16:15The Silicon Pixel Detector (SPD) is the section of the ALICE Inner Tracking System closest to the interaction point. In order to operate the detector in a safe way, a control system was developed in the framework of PVSS which allows monitoring a large number of parameters such as temperatures, currents, etc. The control system of the SPD implements interlock features to protect the detector...Go to contribution page
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Mr Datao Gong (Southern Methodist Univeristy)24/09/2009, 16:15Radiation tolerant, high speed and low power serializer ASIC is used for optical digital data links systems in particle physics. Based on a commercial 0.25 μm silicon-on-sapphire CMOS technology, we designed a 16:1 serializer with a 5 Gbps serial data rate. We present the design details and post layout simulation results. This ASIC will be submitted for fabrication in August 2009. A shared PLL...Go to contribution page
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Mr Sebastian Schopferer (University of Freiburg)24/09/2009, 16:15The GANDALF transient recorder with a resolution of 12bit@1Gsps has been developed to sample analog signal pulses with fast rising edges (3ns) and large dynamic ranges at the COMPASS experiment. Signals are digitized and processed by fast algorithms to extract pulse arrival times and amplitudes in real-time and to generate experiment trigger signals. With 8 analog channels, deep memories and...Go to contribution page
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Dr Sandro Bonacini (CERN)24/09/2009, 16:15the e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The e-link is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable Low-Voltage Signaling (SLVS)...Go to contribution page
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Mr Jan Buytaert (CERN)24/09/2009, 16:15The LHCb experiment plans to upgrade the entire detector and increase its running luminosity by a factor 10, by 2015/2016. This will require a full scale replacement of the front end electronics, to enable all detector information to be read out at 40 MHz and combined in the first level trigger executed on a PC-farm. In addition, the parts of the detector which suffer from radiation damage...Go to contribution page
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Prof. Marco Meschini (Istituto Nazionale di Fisica Nucleare, Firenze, Italy)24/09/2009, 16:15We demonstrate the feasibility of 10.7 Gb/s error-free (BER < 1e-12) optical transmission on distances up to 2 km using a recently developed ultra-low-voltage commercial electro-optic modulator (EOM) that is driven by 0.6 Vpp and with an optical input power of 1 mW. Thus, the modulator could be driven directly from the detectors’ board signals without the need of any further amplification...Go to contribution page
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Mr Stefan Haas (CERN)24/09/2009, 16:15The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to...Go to contribution page
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Ms Annie Xiang (Southern Methodist University)24/09/2009, 16:15Serial optical data transmission provides a solution to High Energy Physics experiments' readout systems with high bandwidth, low power, low mass and small footprint. It will commonly be used in detector upgrades for the SLHC. In the meanwhile, commercial FPGAs with embedded multi-gigabit transceivers have become accessible. We develop a test bench with such a device at its core to verify link...Go to contribution page
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Fernando Arteche (Instituto Tecnologico Aragon - Saragoza - Spain)24/09/2009, 16:15The identification of the coupling mechanisms between noise sources and sensitive areas of the front-end electronics (FEE) in the previous CMS tracker sub-system is critical to optimize the design of integrated circuits and hybrids for the proposed SLHC Silicon Strip Tracker systems. This paper presents a validated model of the noise sensitivity of the Silicon Strip Detector-FEE of the CMS...Go to contribution page
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Mohsine Menouni (CPPM, Aix-Marseille Université, CNRS/IN2P3, Marseille, France)24/09/2009, 16:15The design of the front-end (FE) pixel electronics requires high speed, low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the...Go to contribution page
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Dr Valeria Sipala (I.N.F.N. Catania)24/09/2009, 16:15A proposal for a system to capture signals in the Optical Module of an underwater neutrino telescope is described, with focus on power consumption and dynamics considerations. All considerations regarding the signals and their acquisition are made starting from the most general hypothesis possible, so that they will be valid for any underwater Cherenkov neutrino telescope. A front-end board,...Go to contribution page
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Dr Thomas NOULIS (Electronics Lab. , Physics Dept., Aristotle Univ. of Thessaloniki, 54124 Thessaloniki Greece)24/09/2009, 16:15Alternative current mode charge sensitive amplifier (CSA) topology and related methodology for use as pre-amplification block in radiation detection read out front end IC systems is proposed. It is based on the use of a current conveyor architecture providing advantageous noise performance characteristics in comparison to the typically used CSA folded caccode structure. In the proposed...Go to contribution page
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Mr Damien Thienpont (IN2P3/LAL)24/09/2009, 16:15The OMEGAPIX circuit is the first front end prototype ASIC designed at LAL (Orsay) using 3D technology for the ATLAS upgrade SLHC pixel project. This work has been done inside a new international consortium for development of Vertical Integrated Technologies for Electronics and Silicon SEnsors (VITESSE), which has gathered, not only 3 IN2P3 (France) institutes, but also Fermilab (USA) and...Go to contribution page
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Dr Isabelle Valin (DRS-IPHC, University of Strasbourg, CNRS-IN2P3)24/09/2009, 16:15In a detector system, clock distribution to sensors must be controlled at a level allowing proper sensors synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), it has been proposed to distribute a low frequency clock at 10 MHz which will be multiplied in each sensor by a PLL to 160 MHz. A PLL was designed for low...Go to contribution page
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Dr Jean-Francois Genat (University of Chicago)24/09/2009, 16:15Micro-Channel Plates anodes are coupled to fast transmission lines in order to reduce the number of electronics readout channels, and provide two-dimensions position measurements using centroids and two-ends delay timing. Tests using a laser and waveformanalysis have shown that resolutions of a few hundreds of microns along thetransmission line can be reached. This technique is planned to be...Go to contribution page
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Mr Stéphane Callier (Laboratoire de l'Accélérateur Linéaire)24/09/2009, 16:15The OMEGA group at LAL has designed 3 chips for ILC calorimeters: one analog (SPIROC) and one digital (HARDROC) for the hadronic one and also one for the electromagnetic one (SKIROC). The readout and the management of these different chips will be explained. To minimize the lines between the ASICs and the DAQ, the readout is made thanks to 2 lines which are common for all the chips: Data and...Go to contribution page
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Mr Sergio Díez (Instituto de Microelectrónica de Barcelona - Centro Nacional de Microelectronica IMB-CNM (CSIC), Spain)24/09/2009, 16:15We present in this paper radiation hardness studies on devices of the 130 nm 8WL Silicon Germanium (SiGe) BiCMOS technology from IBM. This technology has been proposed as one of the candidates for the Front-End (FE) readout chip of the upgraded Inner Detector (ID) and the Liquid Argon Calorimeter (LAr) of the ATLAS Upgrade experiment. Gamma, neutron and proton radiation experiments have been...Go to contribution page
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Dr Markus Friedl (HEPHY Vienna)24/09/2009, 16:15A prototype readout system has been developed for the future Super- Belle Silicon Vertex Detector at the Super-KEK-B factory in Tsukuba, Japan. It will receive raw data from double-sided sensors with a total of approximately 250,000 strips read out by APV25 chips at a trigger rate of up to 30kHz and perform strip reordering, pedestal subtraction, a two-pass common mode correction and zero...Go to contribution page
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Mr Stépahne Callier (Laboratoire de l'Accélérateur Linéaire)24/09/2009, 16:15The SPIROC chip is a dedicated very front-end electronics for an ILC technical prototype hadronic calorimeter with Silicon Photomultiplier (or MPPC) readout. This ASIC is due to equip a 2,000-channel demonstrator in 2009. The SPIROC chip is the successor of the ILC_SiPM ASIC presently used for the ILC AHCAL physics prototype incorporating additional features like autotriggering, pipelines,...Go to contribution page
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Vasilii Kushpil (Academy of Sciences of the Czech Republic (ASCR))24/09/2009, 16:15This paper describes a new electronics module for converting a parallel data flow to a serial stream in the USB 2.0 High Speed protocol. The system provides a connection between a PC USB port and a parallel interface of the DAQ board, which is used for investigation of performance of Active Pixel Sensors (APS) prototypes. The DAQ readout software supports Win XX OS and Linux OS. GUI examples...Go to contribution page
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Dr Thijs Wijnands (CERN)24/09/2009, 16:15Based on the principle of the RADMON on line radiation monitoring system for the LHC, a new type of low cost, battery powered radiation monitors has been designed that do not need external cabling. In this paper we will outline the hardware design, summarise on the radiation tolerant components and tests and describe the associated usb interace and labview software. First operational data from...Go to contribution page
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Mr Babak Abi (Oklahoma State University)24/09/2009, 16:15We study the radiation hardness of PiN diodes which are part of the optical link. These components were irradiated by 200 MeV protons up to 8.2 x 10exp(15) 1-MeV neq/cm2 ( 84 MRad). The responsivity of PiN diodes are measured as a function of the radiation dose to estimate life time reliability of diodes.Go to contribution page
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Mr Nicolai Schroer (Ruprecht Karls Universitaet Heidelberg)24/09/2009, 16:15About 600 custom-built ReadOut Buffer INput (ROBIN) PCI boards are used in the Data-Collection of the ATLAS experiment at CERN. In the standard setup requests and event data are passed via the PCI interfaces. The performance meets the requirements, but may need to be enhanced for more demanding use cases. Modifications in the software and firmware of the ROBINs have made it possible to...Go to contribution page
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Mrs Jennifer Boek (Bergische Universitaet Wuppertal)24/09/2009, 16:15For the sLHC upgrade a new ATLAS Pixel Detector is planned, which will require a completely new Control System. The requirements, a first concept and a layout will be presented. We will focus on a control chip which necessarily has to be implemented in the new Detector Control System. A setup of discrete components has been built up to investigate and verify the chip's requirements. First...Go to contribution page
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Mr Tiankuan Liu (Southern Methodist University)24/09/2009, 16:15Detector front-end readout upgrades for the ATLAS Liquid Argon Calorimeter call for radiation tolerant, high speed, and low power optical digital data links. In the development for a high speed, low power serializer ASIC, we have designed an LC-based phase locked loop (PLL) using a commercial 0.25-µm Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates that we can...Go to contribution page
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Mr Guido Volpi (INFN, Sezione di Pisa-Unknown-Unknown)24/09/2009, 16:15Hadron collider experiments search for extremely rare processes hidden in much larger background levels. Only a tiny fraction of the produced collisions can be stored on tape and an enormous real-time data reduction is needed. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise...Go to contribution page
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Dr Alessandro Gabrielli (CERN EP-MIC - Physics Department & INFN Bologna)24/09/2009, 16:15This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a...Go to contribution page
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Dr Michele Caselle (CERN - Università Degli Studi di Bari)24/09/2009, 16:15The SPD forms the two innermost layers of the ALICE experiment. It is equipped with a total of 120 modules (half-staves) with a total number of 9.8 x 106 readout channels. Each half-stave is connected via three optical links to the off-detector electronics made of FPGA based VME readout cards (Routers). The Routers and their mezzanine cards provide the zero-suppression, data formatting and...Go to contribution page
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Ms Costanza Cavicchioli (CERN)24/09/2009, 16:15The ALICE Silicon Pixel Detector (SPD) constitutes the two innermost layers of the ALICE experiment. It consists of 1200 pixel chips with a total of ~107 channels with a pixel size of 50x425 μm2. Each pixel chip transmits a Fast-Or signal upon registration of at least one pixel hit. These signals are extracted every 100 ns and processed by the Pixel Trigger (PIT) system. A signal is then...Go to contribution page
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Mrs Serena Mattiazzo (Dipartim. di Fisica Galileo Galilei-Universita degli Studi di Pa)24/09/2009, 16:15A monolithic pixel detector in deep-submicron Silicon On Insulator (SOI) technology has been developed and characterized. This summary presents the first assessments of the effect of ionizing radiation as regards the total dose damage on single transistors in the technology used for the development of the first prototype chip. This work shows the decisive effect of the substrate bias condition...Go to contribution page
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Jens Dopke (University of Wuppertal)24/09/2009, 16:15The first upgrade for the ATLAS pixel detector will be an additional layer, which is called IBL (Insert-able B-Layer). To readout this new layer having new electronics assembled an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth and also compatible with the existing system to be integrated into it. The talk will...Go to contribution page
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Ms Agnes Rudert (Atlas HEC)24/09/2009, 16:15The signal amplification and summation electronics of the ATLAS Hadronic End-cap Calorimeter (HEC) is operated at the circumference of the HEC calorimeters inside the cryostats in liquid argon. The present electronics is designed to operate at irradiation levels expected for the LHC. For operation at the sLHC the irradiation levels are expected to be a factor 10 higher, therefore a new...Go to contribution page
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Mr Peter Phillips (Particle Physics)24/09/2009, 16:15The ABCN-25 chip was fabricated in 2008 in the IBM 0.25 micron CMOS process. One wafer was immediately diced to make chips available for evaluation with test PCBs and hybrids, programmes which are reported separately. Early indications based on the diced wafer suggested a percentage yield in the high nineties, however the community decided to screen the remaining wafers such that faulty die...Go to contribution page
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Dr Ozgur Cobanoglu (CERN, PH-ESE-ME)24/09/2009, 16:15This paper describes the data serializer of the GigaBit Transceiver (GBT) which has been under development for the LHC upgrade (SLHC). The circuit operates at 4.8 Gb/s and is implemented in a commercial 130 nm CMOS technology. The serializer occupies an area of 0.6 mm² and its power consumption is 300 mW. The paper focuses on the techniques used to achieve radiation tolerance and on the...Go to contribution page
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Prof. Michael Schulte (College of Engineering - University of Wisconsin)25/09/2009, 09:00Programmable Logic, design tools and methodsOralEmerging FPGA architectures include large amounts of programmable logic and interconnect, dedicated memory, and digital signal processing slices, along with high-speed serial and parallel I/0, embedded microprocessors, integrated communication blocks, and advanced clocking capabilities. These emerging FPGA architectures and new FPGA development tools, which enable designs to be developed at a...Go to contribution page
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Dr Salvatore Loffredo (INFN)25/09/2009, 09:45Programmable Logic, design tools and methodsOralTime to Digital Converters (TDCs) are often required in many applications in High Energy and Nuclear Physics. Furthermore, they have been widely used in many scientific equipments such as Time-Of-Flight (TOF) spectrometers and distance measurements. Different configurations of tapped delay lines are widely used to measure sub-nanosecond time intervals both in ASIC and FPGA devices. However,...Go to contribution page
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Mr Frederic MARIN (CPPM)25/09/2009, 10:10Programmable Logic, design tools and methodsOralThe GBT chip is a radiation tolerant ASIC that can be used to implement bidirectional multipurpose 4.8 Gb/s optical links for high-energy physics experiments. It will be proposed to the LHC experiments for combined transmission of physics data, trigger, timing, fast and slow control and monitoring. Although radiation hardness is required on detectors, it is not necessary for the electronics...Go to contribution page
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Mr Csaba Soos (European Organization for Nuclear Research (CERN))25/09/2009, 10:35Programmable Logic, design tools and methodsOralReliable optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Ratio (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER...Go to contribution page
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Anthony Gregerson (University of Wisconsin-Madison), Michael Schulte (College of Engineering - University of Wisconsin), Shuvra BHATTACHARYYA (University of Maryland)25/09/2009, 14:15This two-part tutorial will introduce the audience to FPGA tools and techniques that provide the ability to efficiently design, integrate, and test high performance digital systems. The first half of the tutorial will cover hardware design techniques and tools currently available from industry such as Xilinx ISE Foundation, PlanAhead Design Analysis, and ChipScope. The second half of the...Go to contribution page
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