Speaker
Description
This talk introduces and shows the simulated performance of two FPGA-based techniques to improve fast track finding in the ATLAS trigger. A fast hardware based track trigger is being developed in ATLAS for the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), the goal of which is to provide the high-level trigger with full-scan tracking at 100 kHz in the high pile-up conditions of the HL-LHC. Options under development for achieving this include a method based on matching detector hits to pattern banks of simulated tracks stored in a custom made Associative Memory ASIC (“HTT”) and one using the Hough transform (whereby detector hits are mapped onto a 2D parameter space with one parameter related to the transverse momentum and one to the initial track direction) on FPGAs (“Hough”).
Both of these methods can benefit from a pre-filtering step, to reduce the number of hit clusters that need to be considered and hence reduce the overall system size and/or power consumption, by examining pairs of clusters in adjacent strip detector layers (or lack thereof). This stub-filtering was first investigated by CMS but has been unexplored in ATLAS until now, and we will show the reduction in throughput enabled along with the performance impact on both HTT and Hough systems of track finding, as well as estimates of resource usage. [No results on the performance of this technique in ATLAS have been shown in previous conferences, workshops or national meetings, though the idea and some feasibility studies were presented at APS 2020]
One feature of the Hough transform method is that it identifies a large number of track candidates, which must be reduced before a second stage precision fit. A neural network has been developed to identify the most promising track candidates, and its promising performance will also be shown, in combination with and independent of stub filtering, along with the resources required to run it on an FPGA. [No results have been presented on this method by ATLAS
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