Conveners
ASIC
- Christophe De La Taille (OMEGA (FR))
ASIC
- Angelo Rivetti (Universita e INFN Torino (IT))
ASIC
- Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
ASIC
- Ping Gui (Southern Methodist University (US))
ASIC
- Christophe De La Taille (OMEGA (FR))
The CBC3 is the latest version of the CMS Binary Chip for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon micro-strip sensors with aligned micro-strips. On-chip logic...
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL–LHC experiments. The PLL features a novel LC-oscillator...
An ultra-low current sensing digitizer circuit for radiation monitoring for personnel and environmental safety was designed.
The ASIC includes some key functionalities like on-chip active leakage current compensation and multi-range charge balancing. The calibration procedure and the measurements of the Ultralow Picoammeter 2 (Utopia 2) ASIC are presented. This chip can measure input current...
ATLAS Muon-Drift-Tubes spatial resolution-&-efficiency depend on drift-time resolution, noise levels, and accurate threshold setting. A new 130nm read-out device is developed and optimized, for the required time resolution, to guarantee rise-times below 10ns, with acceptable time-slewing effects. Moreover, the large chain-amplification results in increased sensitivity to any disturbance...
The development of a large scale 65nm CMOS pixel demonstrator chip for very high rate (3GHz/cm2) and very high radiation levels (1Grad) for ATLAS and CMS phase 2 pixel upgrades has taken place within the RD53 collaboration. The development and testing of radiation test structures, building blocks and small scale pixel array demonstrators are summarized together with test and radiation...
ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and the readout electronics is 30 ps/MIP. Each analog channel of the ASIC must exhibit an extremely low jitter noise to ensure this challenging time resolution, while keeping a low power...
The design and measurement results of a waveform digitizer based on the Switched Capacitor Array (SCA) architecture, fabricated in CMOS 180 nm technology, are presented. The prototype ASIC containing two channels inside is fully functional at a sampling rate of 2 Gsps with an analogue -3 dB bandwidth of more than 400 MHz. Each channel integrates 128 sampling cells and a ramp-compare ADC. With...
The MuTRiG chip, which is dedicated to the Mu3e experiment, is a 32 channel
mixed-signal Silicon Photomultiplier readout ASIC with high timing precision
and high event rate capability designed and fabricated in UMC 180 nm CMOS
technology. It combines the excellent timing performance of the fully
differential analog front-ends and the 50 ps time binning TDCs with a high
event rate capability...
SALT is a 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It
will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial
output data. SALT is designed in CMOS 130~nm process and uses a novel architecture comprising of analogue
front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit...
For the HGCAL calorimeter upgrade of CMS, two test vehicles were submitted in 2016. They provide the main building blocks of the future ASIC that will read out 50 pF Si-sensors over 10 pC dynamic range. The first test-vehicle features several variants of low-noise, dual-input-polarity current-sensitive preamplifiers. The second test vehicle has eight channels of the full analog-chain :...
CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 $\mu m^2$. It is fully functional, can work at low thresholds down to 250e$^-$ and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex...
We report on the measurements performed on the full custom ASIC TOFFEE designed to read out Ultra Fast Silicon Detectors (UFSD). The ASIC has been tested in laboratory with custom test boards and an infrared laser hitting the sensor and emulating a minimum ionizing particle signal.
Laser measurements showed that a time resolution of less than 50 ps is achievable with a 10 fC signal.
We will...
The H35DEMO chip is a HV/HR-MAPS demonstrator of 18.49 mm x 24.4 mm, fabricated with a 0.35 µm HVCMOS process from AMS in four different substrate resistivities. The chip is divided into four independent matrices with a pixel size of 50 µm x 250 µm. Two of the matrices include all the digital readout electronics at the periphery. This contribution describes the two standalone matrices of the...
Detectors with precise time-of-flight measurement capabilities are a very active area of research in particle physics and imaging, due to their improved accuracy and background rejection. In this contribution we present a monolithic readout ASIC, developed for a novel PET scanner, featuring a 30 ps time resolution for 511 keV photons using a SiGE HBT based front-end, capable of driving large...
TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal...
This work presents a Depleted Monolithic Active Pixel Sensor (DMAPS) prototype manufactured in LFoundry 150 nm CMOS process. The described device, named LF-Monopix01, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of ATLAS Inner Tracker upgrade for High Luminosity LHC. Implementing such device in the detector will result...
We present the latest results of the FE65-P2 pixel readout test chip. This is a 64 by 64 pixel matrix on 50 um by 50 um pitch, produced in 65nm CMOS technology at the end of 2015. FE65-P2 was designed to demonstrate small pixel performance and stable operation down to 500 electron threshold even with the front end pixel amplifiers embedded in a synthesized logic environment. The FE65-P2...
The ATLAS experiment at CERN plans to upgrade its Inner Tracking system for the High-Luminosity LHC in 2026. After the ALPIDE monolithic sensor for the ALICE ITS was successfully implemented a 180nm CMOS Imaging Sensor technology, the process was modified to combine full sensor depletion with a low sensor capacitance (~2.5fF), for increased radiation tolerance and low analog power consumption....
