Speaker
Piotr Kmon
(AGH UST Krakow)
Description
We present a multichannel integrated circuit of pixel architecture designed in CMOS 40nm technology. The chip is composed of 40 × 24 pixels of 75 μm pitch working in the SPC mode, each built of Charge Sensitive Amplifier (CSA), Peak Detector (PDH), 6-bit Analog to Digital Converter (ADC), and memory composed of 64 × 12-bit counters. Thanks to the proposed functionality it is possible to store in each pixel separately information of incoming particles energy spectrum. The chip is dedicated to operate with both electrons and holes of 2.2 ke- – 32 ke- energy. The IC occupies an area of 2 x 4.5 mm2, is back from fabrication, and being prepared for measurements.
