27 June 2021 to 1 July 2021
Europe/Brussels timezone

Timepix4, a large area pixel detector readout chip which can be tiled on 4 sides providing sub-200ps timestamp binning

30 Jun 2021, 15:50
Zoom (Online)



Oral presentation Front end electronics and readout Oral presentations


Xavi Llopart Cudie (CERN)


The Timepix4 chip is designed to read out a large area pixel detector comprised of 448 x 512 pixels of 55 micron square. The chip is the first large area pixel detector which can be tiled on all 4 sides when Through Silicon Vias are used to access the chip IO. There are two operating modes: data driven and photon counting. In data driven mode each pixel which is hit will produce a 64-bit word containing the hit pixel address, the Time over Threshold (with a precision of ~ 120 e- rms) and the arrival time stamped to within a 200ps bin over a total time of up to ~80 days. The maximum flux which can be read out correctly is ~ 7Mhits/mm2/s when all 16 serial links running at 10 Gbps are used. In photon counting mode the chip can operate at up to 44kfps in 16-bit mode and 89 kfps in 8-bit mode. This paper will describe the requirements, the chip architecture and show first measurements

Primary authors

Xavi Llopart Cudie (CERN) Jerome Alexandre Alozy (CERN) Rafael Ballabriga Sune (CERN) Michael Campbell (CERN) Raimon Casanova Mohr (The Barcelona Institute of Science and Technology (BIST) (ES)) Vladimir Gromov (Nikhef National institute for subatomic physics (NL)) Erik Heijne (Czech Technical University in Prague (CZ)) Tuomas Sakari Poikela Edinei Santin Viros Sriskaran (EPFL - Ecole Polytechnique Federale Lausanne (CH)) Lukas Tlustos (Czech Technical University in Prague (CZ)) Arseniy Vitkovskiy (Nikhef National institute for subatomic physics (NL))

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