The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics, atomic physics, interdisciplinary science, and relative applications. There are many different kinds of detectors for radiation imaging in the experiments at HIRFL-CSR. To reduce the development time, production cost, and maintenance difficulties of the readout electronics for the detectors, a Common Data Acquisition Unit (CDAU) has been designed as a common interface between the detector-specific electronics and the common computing system.
The geometry of the CDAU is designed according to the PCIe speciﬁcation, which allows several CDAUs to be installed into adjacent PCIe slots. The central component on the board is Xilinx Kintex Ultrascale FPGA, which has 20 GTH Transceivers. The CDAU exchanges data from the detector front-end electronics with 4 serial full-duplex optical links, which are four SFP modules. The serial links are directly connected to the front-end boards with detectors by fibers, achieving a speed of up to around 16.5 Gbps. The CDAU connects with the online data computer with the PCIe interface, which is realized with the PCIe hard block in the Kintex Ultrascale FPGA for up to eight-lane PCIe Gen3 (8.0 Gbps per lane). The CDAU hosts four DDR4 SRAMs with a total size of 16 GBytes and a maximum data rate of 2400 Mbps. The CDAU also hosts a 300Mhz differential oscillator for the main FPGA. On the other hand, a conﬁgurable reference clock oscillator for the PCIe, GTH, and the DRR4 memories, which allows the interface to run at any speed within the supported range. This paper will discuss the design and performance of the CDAU.