In Germany nearly 30 universities and several research laboratories perform research in particle physics. This includes a strong theory community and the participation in a wide range of experiments, R&D projects, accelerator physics and computing. A strong focus is on the LHC physics programme. The talk will give an overview of the activities as well as the structure and perspective in this...
Detector instrumentation and the development of the underlying technologies in Germany take place in a rather diverse landscape of institutions. This includes university groups, Helmholtz centres, Max Planck institutes, Fraunhofer institutes and others. With the creation of the Helmholtz programme "Matter and Technologies" the field of detector instrumentation in Germany has been strengthened...
Within the last decade, the idea of invisibility cloaking has turned from Science Fiction to scientific reality. Here, we review the underlying principle based on coordinate transformations and demonstrate application in terms of making metallic contacts on solar cells, detectors, and light-emitting diodes invisible.
The FAIR Project at GSI Helmholtzzentrum für Schwerionenforschung in Darmstadt (GSI) will offer unique research capabilities with heavy ion and antiproton beams. The ambitious goals of the scientific communities require to extend the capabilities of the present accelerators at GSI which will be the injectors of the future facility and push the future accelerators to the technical limits. We...
Consumer electronics focus on low cost, small size, low power consumption and overall system performance. This lead to combined multi-axis sensing structures, integrated power management schemes and sensor data fusion. Bosch is actively driving this evolution further with novel multiple sensors on one single chip which will become the key element for new IoT applications.
The ATLAS experiment will use an all-silicon tracker in the Phase II upgrade for the HL-LHC collider at CERN. For the Silicon Strip detector of the ITk, a new readout chip ABCStar is under design to meet the new requirements of higher trigger rates and lower latency. We summarize the status of this work and present the new features of the chip.
Firmware for FPGA trigger applications at the CMS experiment is conventionally written using hardware description languages such as Verilog and VHDL. MaxCompiler is an alternative, Java based, tool for writing FPGA applications and removes some of the need for electronics expertise. This provides potential to lower the barrier for contribution to firmware design. An implementation of the jet...
SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit...
Accelerating trigger applications on FPGAs (using VHDL/Verilog) in CMS experiments at LHC-CERN warrants consistency between each trigger firmware and its corresponding C++ model. This tedious and time consuming process of convergence is exacerbated during each upgrade study. High-level synthesis, with its promise of increased productivity and C++ design entry bridges this gap exceptionally...
PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. It will be composed of four barrels and six disks, instrumented with silicon hybrid pixel detectors and double-sided microstrip detectors.
PASTA (PAnda STrip ASIC) is the readout chip for strip sensors.
An overview of the chip, of its readout system and of...
A Serial Powering Stave Prototype has been developed using FE-I4 Quad Pixel Modules in order to investigate a Serial Powering scheme for ATLAS ITk Phase II Pixel upgrade.
The talk will explain the need for a new powering scheme which is different from the currently used parallel (direct) powering in order to power detector modules for the ATLAS ITk Phase II Pixel upgrade. The Serial...
This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64x64 matrix of 50x50$\mu m^2$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5 % at 3GHz/cm$^2$ pixel rate, 1MHz trigger with 12.5$\mu$sec latency. Two analog front end designs, one synchronous and one asynchronous, are...
A new vertical JFET technology, based on a 3D trenched design, has been developed at the IMB-CNM. Conceptually introduced in TWEPP 2015, these transistors are conceived to work as radhard switches in the HV powering scheme of the ATLAS ITk strip detectors. The first fabricated wafers have been fully characterized and the results are presented here. Device performance is very close to...
This work describes the design, in 65nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC. Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to few hundreds MHz. Two small prototypes have been submitted and tested; a X-ray...
This presentation will provide an overview of key enabling technologies addressing the increasing demands for reduced size, weight, power consumption and enhanced signal processing throughput in next generation radiation tolerant systems, without sacrificing reliability.
RTG4 is Microsemi’s next generation FPGA family for radiation environments using a 65nm low-power
flash process, which is...
ICPIX28 is the first 28nm bulk-CMOS readout frontend for High Energy Physics pixel detectors. It performs the conversion of the input charge into a voltage signal, hence detect the charge arrival time and amount of charge information through Time-over-Threshold signal. The front-end is composed by the cascade of a Charge Sensitive Preamplifier and a low-power switched-capacitor...
Coherent synchrotron radiation requires DAQ systems with picosecond resolution. The Karlsruhe Pulse Taking Ultra-fast Readout Electronics (KAPTURE) is a novel system for a continuous investigation of THz synchrotron radiation. It is capable to sample single THz pulses with sampling times down to 3 ps. To improve performance and flexibility a second version of KAPTURE has been developed. The...
The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16bit dynamic range, and the development of...
HEPS-BPIX is a dedicated hybrid pixel detector for the High Energy Photon Source in China. It works in the single photon counting mode, and each pixel chip contains an array of 10472 pixels with a pixel size of 150um150um. Based on the successful design of the chip, the detector module was assembled by bump bonding with 2*4 pixel chips and a single large sensor. Six detector modules were...
In this presentation the read-out scheme will be introduced. Laboratory measurements have been done to characterize and optimize the analog electronic scheme and the FPGA VHDL code. The adaption process to different detector pulse shapes will be also shown. The results obtained at beam tests at the MAMI accelerator in Mainz and the SPS at CERN will be presented.
We have been developing a monolithic type pixel detector for the ILC vertex detector with 0.2 um fully depleted SOI CMOS process. We are aiming to achieve 3 um of a single point resolution that is required for the ILC with a 20 um x 20 um pixel. Beam test result of the first prototype sensor that an amplifier and an analog memory are implemented in each pixel is presented. Design of second...
ATLAS and CMS are presently collaborating on a design of a pixel readout chip in 65nm CMOS technology to be used for the LHC Phase-II upgrade. This work presents a prototype containing part of the I/O interface of this readout chip. The clock-data recovery circuit recovers clock from 160 Mbps incoming data and produces 1.6 GHz clock to be used by serializer. Double data rate serializer...
The paper describes a SAR ADC, elaborated for digitization the shaper signal of the read-out CBM MUCH ASIC. The MUCH ASIC was designed and prototyped by means of the 0.18 um CMOS process of UMC (Taiwan). Each channel of ASIC consist of a CSA, fast and slow shapers, discriminator, ADC and a digital peak detector. ADC has a power consumption of 1.5 mW at 50 Ms/s and an occupied area of 0.0162...
CMOS pixel sensors with notable depletion have been demonstrated to be feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, replacing the current passive sensors. A further step to exploit the potential of CMOS sensors is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. In this work, a monolithic CMOS pixel...
The ALICE experiment at the LHC plans upgrade of its TPC, due to expected high Pb-Pb collision-rate after the shutdown of LHC in 2018. In the upgraded TPC, Gas Electron Multiplier (GEM) chambers and continuous readout system will replace MWPC chambers and conventional triggered readout. In the continuous readout, GEM signals will be processed using 32 channels of SAMPA ASIC (preamplifier and...
CATIROC is an upgraded version of PARISROC2 designed to read huge photodetection areas for neutrinos experiments. This “System-on-Chip” is a very innovative concept as it sends out only relevant data by network to the central data storage turning the detector into a smart one. The ASIC integrates a self-triggering mode down to 50 fC which provides time measurement better than 1 ns and charge...
This work presents the design and characterization of a SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications.
The prototype chip was designed and fabricated in the framework of the CHIPIX65 project and was completely characterized in the first quarter of 2016. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing...
In particle physics experiments a stable sub-1-V reference voltage is needed in spite of harsh ionizing radiation conditions. After such radiation load the bandgap using standard p-n junction of bipolar transistor does not work properly. This is why several sub-1V voltage references based on DTMOS (dynamic threshold MOS) and ELTMOS (enclosed layout transistor MOS), using CMOS 130nm process...
Low-power and high-data-rate laser array driver is an important on-detector component of the Versatile Link for the high-luminosity LHC experiments. We report the design and implementation of a low-power and radiation-tolerant 4x10 Gb/s VCSEL Driver array IC (LDQ10P). The entire four-channel VCSEL driver consumes 130 mW and occupies a silicon area of 1900 µm × 1700 µm. By integrating four...
The 2018/2019 upgrade of LHCb Muon System foresees a 40 MHz readout scheme and requires the development of a new Off Detector Electronics (nODE) board that will be based on the nSYNC, a radiation tolerant custom ASIC developed in UMC 130 nm technology.
Each nODE board has 192 input channels processed by 4 nSYNCs. The nSYNC is equipped with fully digital TDCs and it implements all the required...
We present work to develop a radiation-hard receiver ASIC in 65nm CMOS with Decision Feedback Equalization (DFE), which is a very efficient technique for compensating the distortions caused by cable losses. Achieving the best possible compensation is particularly important for HL-LHC tracking detectors because the readout cable mass is inversely related to the tolerated amount of distortion....
The Time Over Threshold (TOT) is usually measured by counting the number of clock cycles that the output of the preamp is over the threshold but the time resolution obtained is limited by the clock frequency and power consumption. Future HEP experiments will require a time resolution of few nanoseconds so that new approaches are needed. This paper presents a circuit to measure the TOT with a...
The 32-channel system for processing asynchronous data from the GEM detectors is presented. It has been developed as part of ASIC intended for the muon chamber of the CBM experiment and allows to run up to 10 MHz channel rate.
The system provides the generation of data packages, consisting of the digital codes of signal amplitude, arrival time and channel number. Control and data exchange...
The SPIDR system is a flexible general-purpose readout platform for new and existing R&D ASIC projects, like Medipix3 and Timepix3. The system consists of an FPGA board, which reads out the ASIC and communicates via 1 and 10 Gigabit Ethernet to the back-end DAQ. It can be easily adapted and used as test-bed for other ASICs . The SPIDR system is currently used in various hybrid pixel detector...
We present the ARAGORN front-end, a cost optimized, high-density Time-to-Digital Converter (TDC) platform. Four Xilinx Artix-7 FPGAs implement 384 TDC channels with a time resolution smaller than 200 ps on a single module. A fifth FPGA acts as data concentrator and master of an onboard SFP+ and a multi-channel optical transceiver slot to interconnect with up to seven boards though a star...
The STS/MUCH-XYTER2 is the new front-end ASIC for the STS and MUCH detectors in the CBM experiment. It uses an innovative protocol ensuring reliable synchronization of the communication link between the controller and the ASIC, transmission of time deterministic commands to the ASIC and efficient readout within a GBT-based data acquisition structure. The paper describes the FPGA-based tester...
The replacement of the whole ATLAS inner detector is foreseen for 2023/2024. The requirements of the data transmission rates for the upgraded pixel detector will be particularly difficult to meet as the projected transmission rates per chip are 5 GBit per second for each readout chip at the inner-most radius. Results from a first prototype (intended for the Alpine layout) of a flex based...
A fast non-destructive transverse profile monitor, named PS Beam Gas Ionization monitor (PS- BGI), is under development at CERN for the Proton Synchrotron (PS). This monitor infers the beam profile from the transverse distribution of electrons created by the ionisation of rest gas molecules by the high energy beam particles. The distribution is measured by accelerating the electrons onto a...
The CMS tracker upgrade for the HL-LHC relies on different module types, depending on the position of the respective module. They are built with HDI flexible circuits that are wire bonded to silicon strip sensors. The front-end hybrids will contain several flip-chip bonded readout ASICs that are still under development. Mock-up prototypes are used to qualify the advanced flexible circuit...
Thin polyurethane (PU) coatings for aluminum wedge wire bonds are proposed to protect the ATLAS Inner Tracker upgrade from condensation-induced corrosion and oscillations from periodic Lorentz forces. Coating robustness after exposure to an HL-LHC lifetime dose is being evaluated. Mechanical properties of irradiated samples are tested at room temperature and -20C. Irradiated samples are...
A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (< 1GRad) and Single Event Upset (SEU) on digital logic gates in a 65nm CMOS technology. Nine different versions of standard cell libraries are explored in this chip, basically differing in the device dimensions, Vt flavor and layout of the device.
Each library has eighteen...
The Mu2e experiment at Fermilab searches for the muon conversion to electron in the Coulomb field of a nucleus. The detector is composed of a straw tube tracker and an CsI crystals electromagnetic calorimeter housed in a superconducting solenoid.
The digitizing electronics will be located inside the magnet cryostat and will be operated in vacuum.
The harsh experimental conditions, with the...
The Versatile Link Demonstrator Board (VLDB) is the evaluation kit for the Radiation Hard Optical Link ecosystem, which provides a 4.8 Gbps data transfer link for communication between front-end (FE) and back-end (BE) of the experiments. It gathers the Versatile Link main radiation hard custom ASICs: GBTx, GBT-SCA and VTRx/VTTx plus the FeastMP, a radiation hard in-house designed DCDC.
This...
The MuPix Telescope is a particle tracking telescope, optimized for low momentum particles and high rates. It was build to test and integrate the novel High-Voltage MonolithicActivePixelSensors (“HV-MAPS”), designed for the Mu3e tracking detector. It is also used to test the Mu3e readout concept.
The telescope consists of four layers of the newest prototypes, the MuPix7 sensors, which send the...
The High Luminosity LHC (HL-LHC) aims to reach the unprecedented integrated luminosity of 3 ab-1 with an instantaneous luminosity up to 5x10^34 cm2 s-1. This poses stringent requirements on the radiation resistance of detector components and on the latency of the trigger system. The barrel region of the CMS Electromagnetic Calorimeter will be able to retain the current lead tungstate crystals...
The ALICE Collaboration is preparing an upgrade of the experimental apparatus. A key element of this upgrade is the construction of a new silicon-based (12 Gpixels, 10m2) Inner Tracking System. Its readout system consists of 192 readout units that control the pixel sensors, power modules and deliver the sensor data to the counting room. A prototype readout unit has been designed to test the...
In this talk we present the design, assembly and integration of the service cylinders for the barrel pixel detector. Furthermore, we present results of the testing and calibrations carried out with a set of Phase 1 detector modules.
Various german Helmholtz centers started 2014 to develop a modular data acquisition platform. This platform integrates generic hardware components like the multi-purpose HGF-AMC Hardware or the UFO smart camera framework, adding user value with linux drivers and board support packages. Technically the scope comprises FPGA-modules, frontend-electronics-interfaces, FPGA-microcontrollers plus...
In order to cope with a twofold increase in nominal LHC luminosity, the second level of the readout system of the CMS Drift Tubes (DT) electronics needs to be redesigned to minimize event processing time and remove present bottlenecks. The uROS boards are uTCA modules, which include a Xilinx Virtex-7 FPGA and equip up to 6 12-channel optical receivers of the 240 Mbps input links. Each board...
The luminosity, latency, and trigger rate foreseen at the High Luminosity LHC presents challenges to efficient readout of the Cathode strip chambers (CSCs) of the CMS end cap muon detector. Upgrades to the electronics are targeted for the inner rings of CSCs in each station, which have the highest flux of particles. The upgrades comprise digital cathode front end boards for nearly...
The RICH detectors of the existing HADES spectrometer and the CBM experiment (to be built at FAIR) will use 64 channel Multi-Anode PMTs.
We designed a complete set of digitizing electronics, consisting of analog and digital frontend modules, power supply and data concentrator cards plugged into a backplane carrying 3x2 MAPMTs on the front side, and all readout modules on the backside.
These...
The Barrel part of the CMS Electromagnetic Calorimeter is made of 61200 scintillating lead tungstate (PbWO4) crystals, read out by avalanche photo-diodes. For the high luminosity phase of the LHC, a timing measurement with a precision of approximately 10 ps can be exploited for pileup mitigation and vertex assignment. Test beam results on the timing performance of PbWO4 crystals with various...
The CMS experiment at the Large Hadron Collider at CERN is upgrading the photo-detection and readout system of the forward hadronic calorimeter (HF). The phase-1 upgrade of the CMS forward calorimeter requires the replacement of the current photomultiplier tubes, as well as the installation of a new front-end readout system. The new PMTs contain a thinner window as well as multi-anode...
The ART Data Driver Card (ADDC) will be used in the ATLAS New Small Wheel (NSW) upgrade to process and transmit the Address in Real Time (ART) signals, which indicates the address of the first above-threshold event. A custom ASIC (ART ASIC) will receive the ART signals and do the hit-selection processing.
To evaluate the performance of the ADDC before the ART ASIC is fabricated, an FPGA based...
The NA62 experiment at CERN SPS has began its data-taking. Its main topic is to reduce uncertainties in the branching ratio of the ultra-rare decay $K^{+} \rightarrow \pi^{+}\enspace\nu\enspace\bar{\nu}$. In this context rejecting the background is a crucial topic. The Cal-l0 trigger get energy deposit from the calorimeters to suppress decays with $\pi^{0}$ and muons in the final state. In...
The NA62 experiment aims to measure the branching ratio of the rare kaon decay K+->pi+nu nubar at the CERN SPS. The calorimeter L0 trigger is the part of the TDAQ used to select events with a pi+ in the final state hadronic and to veto one of the most dominate background from events K+ -> pi+pi0. It has been developed and installed (it has taken first physics data in autumn 2014). We present...
NaNet is a framework for the development of FPGA-based PCI Express (PCIe) Network Interface Cards (NICs) with real-time data transport architecture that can be effectively employed in TRIDAQ systems.
Key features of the architecture are the flexibility in the configuration of the number and kind of the I/O channels, the hardware offloading of the network protocols stack, the stream processing...
The COMET detector will include a electromagnetic calorimeter (ECal). The ECal signals will used for energy deposition measurement and for triggering. For triggering, the calorimeters signals will transformed into special short-shaped analog signals. These signals will then digitally processed with special algorithm, which allows one to obtain a set of logic signals necessary for event...
ALICE is the detector at the CERN LHC dedicated to the study of strongly interacting matter. The collaboration plans a major upgrade of the detector in RUN3. The interaction rates will increase to about 50 kHz for Pb-Pb and few hundred kHz for pp. The aim of the ALICE trigger system is to select essentially all of these interactions.The events are read out and the event records are sent to the...
The Phase 2 upgrade of the CMS Drift Tubes detector aims at moving all the readout and trigger electronics from the inner detector to outside the cavern. Trigger algorithms need to be redesigned to handle direct timing information and remove present bottlenecks of resolution and deadtime, approaching to present high level trigger performance. In the present contribution we describe the work...
Real-time track reconstruction at high event rates is a major challenge for future experiments in high energy physics. To perform pattern-recognition and/or track fitting, artificial retina or Hough transformation have been introduced in the field which have to be implemented in the FPGA firmware.
In this contribution, we will report on a possible FPGA hardware implementation of retina...
This report describes the Tile-Muon Trigger within the TileCal upgrade activities, focusing on the new on-detector electronics such as the Tile Muon Digitizer Board (TMDB) providing (receive and digitize) the signal from eight TileCal modules to three Level-1 muon endcap sector logic blocks.
The Overlap Muon Track Finder (OMTF) is the new system developed during the upgrade of the CMS experiment. It uses the novelty approach to find muon candidates basing on data received from three types of detectors: RPC, DT and CSC. The upgrade of the trigger system requires also upgrade of the associated Data Acquisition (DAQ) system, that must transmit the data from the RPC detector, but for...
CMOS Image Sensors (CIS) have become the main solid state image sensor technology for visible imaging applications. Despite the higher radiation hardness of CIS compared to its CCD counterpart, there are still demanding applications where CMOS imager performances can be significantly reduced by high energy particles. This is the case for the most severe radiation environments where imaging...
This paper presents the SAMPA, a new ASIC for the ALICE upgrade for Time Projection chamber (TPC) and Muon chamber (MCH) read-out frontend electronics.
The SAMPA ASIC is designed in 130nm CMOS technology with 1.2V nominal power supply. SAMPA includes 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel comprises a Charge...
The CMS experiment at the LHC will deploy the first large (16k channel)
silicon photomultiplier system in a high radiation environment as the central
feature of its hadron calorimeter upgrade.
The exceptional 35% photon detection efficiency of the SiPMs is critical
for ameliorating the effects of radiation damage of the calorimeter scintillator.
The SiPM signals are digitized by the QIE11...
The data acquisition system (DAQ) for a highly granular analogue hadron calorimeter (AHCAL) for the future International Linear Collider (ILC) will be presented. The developed DAQ chain has several stages of aggregation and scales up to 8 million channels foreseen for the AHCAL detector design. The largest aggregation device, LDA (Link data aggregator), has 96 HDMI connectors, four Kintex7...
SKIROC2_CMS is a chip derived from CALICE SKIROC2, providing 64 channels of low noise readout for 50pF Si-sensors over 10pC dynamic range. The pre-amps are followed by high/low gain 25ns shapers, 16-deep 40 MHz analog memory “waveform sampler” and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA...
HARDROC is the very front end chip designed to readout the Resistive Plate Chambers foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the calorimeter implies thousands of electronics channels per cubic meter which is a new feature of “imaging” calorimetry. Moreover, for compactness, chips must be embedded inside the...
The SoLid collaboration have developed an intelligent read-out system to reduce their 3000 silicon photomultiplier detector's data rate by a factor of 10000 whilst maintaining high efficiency for storing data from antineutrino interactions.
The system employs an FPGA level waveform characterisation to trigger on neutron signals.
Following a trigger, data from a spacetime region of interest...
Petiroc2a is a 32-channel front-end ASIC designed in AMS 0.35µm SiGe technology to read out Silicon Photomultipliers (SiPMs) for applications requiring accurate time resolution and energy measurement over a large dynamic range.
Each channel integrates a 20GHz Gain Bandwidth preamplifier followed by an ultra fast discriminator and a TDC. The first incident photons can be measured with a time...
The on-detector electronics of the LHCb Scintillating Fiber Detector consists of multiple PCBs assembled in a unit called Read Out Box, capable of reading out 2048 channels with an output rate of 70 Gbps. There are three types of boards: PACIFIC, Clusterization and Master Board. The PACIFIC boards host PACIFIC ASICs, with pre-amplifier and comparator stages producing two bits of data per...
We will present the electronic and DAQ system being developed for TripleGEM detectors which will be installed in the CMS muon spectrometer. The microTCA system uses an Advanced Mezzanine Card equipped with an FPGA and the Versatile Link with the GBT chipset to link the front and back-end. On the detector an FPGA mezzanine board, the OptoHybrid, has to collect the data from the detector readout...
The TOFPET2 ASIC is a low-power, low-noise, readout and digitization chip for SiPMs sensors implemented in 110nm CMOS technology optimized for time-of-flight measurements. The circuit has 64 independent channels including quad-buffered TDCs and charge integration ADCs in each channel, and is an evolution of the TOFPET1 ASIC, which was developed in 130nm CMOS technology for Positron Emission...
Electronic systems located in LHC underground areas can suffer by radiation induced failures. The knowledge of the radiation levels around the LHC accelerator and the cause of faults permits to improve the LHC availability every year. The shielding, relocation and equipment upgrade are the ingredients to mitigate the radiation effects. A test protocol exists for the equipment upgrade which...
The design and measurement results of four ultra-low power 10-bit SAR ADCs, fabricated in CMOS 130~nm technology, are presented. All prototypes use very similar architecture with main difference in split in the capacitive DAC network. The prototypes are fully functional, achieve excellent linearity (DNL < 0.3 LSB and INL ~0.5 LSB), and show very good ENOB above 9.5 for 0.2 Nyquist input...
The LHCb Experiment will be upgraded to a trigger-less system reading out the full detector at 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator (VELO) will be a hybrid pixel detector read out by the VeloPix ASIC with on-chip zero-suppression. This paper will present the systems overview and design of the VELO on-detector electronics, including...
The CBM experiment at FAIR will use GBTX and Versatile link based readout systems for several subdetectors.
Particularly challenging is the readout of the silicon tracking system (STS) which requires features like a minimal number of frontend connections, AC coupling and time deterministic messages.
The paper gives a detailed description of the readout concept for the STS, emphasizing...
This paper presents a 4-chanel TDC chip demonstrator with the following features: 15-ps resolution, 1280 ns dynamic range, dead time < 20 ns, up to 10 MHz of sustained input rate per channel, around 60 mW of power consumption and very low area in a 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry which is based on a resistive...
We present designs and test results of two ASICs, VLAD and lpVLAD. Each is a 4-channel, 10-Gbps-per-channel VCSEL array driver fabricated in a 65 nm CMOS technology. lpVLAD deploys a novel high-efficient output structure to achieve a record low power consumption of 25 mW/ch when delivering 2 mA bias and 6 mA modulation currents at 10-Gbps. Eye diagrams of both two designs under post-layout...
The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe...
A prototype readout channel was manufactured in UMC CMOS 180 nm for the purpose of the CBM experiment at the FAIR accelerator. The channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, 6 bit SAR ADC (40 Msps, 1.5mW power consumption), digital peak detector and block of the time stamp registration. The control data, clock...
STS-XYTER2 is a new full-size CBM Silicon Tracking System and Muon Chamber prototype readout ASIC designed in UMC 180 nm CMOS technology. It is a self-triggered amplitude and time measurement chip implementing a digital back-end compatible with a GBTx-based data acquisition scheme with scalable data bandwidth. We present details on the front-end and back-end solutions used in this ASIC and...
For several years, a group of engineers and physicists from LAL and LPNHE have been working on the design of two front end ASICs dedicated to Charge Couple Devices (CCD). ASPIC (Analogue Signal Processing Integrated Circuit), designed in AMS CMOS 0.35µm 5V technology, is meant to readout and process the analog signals of CCDs. CABAC (Clocks And Biases ASIC for CCDs), designed in AMS CMOS...
Scalable Low Voltage Signaling (SLVS) Transmitter (Tx) and Receiver (Rx) IP blocks are designed in the UMC 180 nm CMOS technology as component of the readout ASIC for the muon chambers (MUCH) of the Compressed Baryonic Matter (CBM) experiment at FAIR (Darmstadt, Germany). These blocks are a prototype of the physical layer of the e-link interface that is used for ASIC-GBTx connection. The...
This paper presents a 10 Gbps serial link transmitter ASIC designed in a 65 nm CMOS technology. The ASIC mainly includes an LC-VCO PLL, a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 6-to-12 GHz tuning range and an RMS jitter of 0.67pS. The serializer has a deterministic jitter of 11 pS and a programmable output swing from 200mV to 800mV (pk-pk). The PLL...
We present design and test results of a dual-channel serializer ASIC, LOCx2, for detector front-end readout. LOCx2 interfaces an ASIC ADC, ADS5272 and ADS5294. LOCx2 may take data from any 12-bit or 14-bit, multiple channel ADCs with sampling rate from 32 to 43 MSPS. We also present the design of LOCx2-130, a drop-in backup to LOCx2 based a 0.13 µm bulk silicon CMOS process. Power consumption...
Immunity against possible random discharges inside active detector volume of the MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for...
Upgrades are planned for the for the CMS barrel ECAL readout electronics . One option for an upgraded pre-amplifier is an improved version of the existing multi-gain pre-amplifier (MGPA). The upgraded MGPA is designed for shorter shaping time to optimize noise performance with photo-detectors damaged by radiation. It also has the ability to identify pulses generated by charge deposited...
Many HEP applications require circuits to continuously operate over large temperature range. In particular, the DUNE experiment requires circuits be capable of operating at cryogenic temperature. We present a novel temperature-compensated triple-path PLL (TP-PLL) for this application. The TP-PLL is capable of automatically compensating its frequency as temperature changes while maintaining...
We present the development of uTRiG, a mixed signal Silicon
Photomultiplier readout ASIC in UMC 180nm CMOS technology, dedicated to
the Mu3e experiment. It extends the ultra-fast timing performance of
the STiCv3 chip with a fast digital readout for ultra-high rate
applications. The high timing performance of the silicon proven, fully
differential SiPM readout channels and 50 ps time binning...
Some pixel architectures designed in LFoundry 150 nm HV CMOS process for the ATLAS Inner Detector upgrade will be presented. These pixels can be readout standalone or can be connected to the FE-I4 readout chip via bump bonding or glue. Negative high voltage is applied to the HR (>2 kOhms.cm) substrate in order to deplete the DNW (Deep N-Well) charge collection diode, ensuring good charge...
This paper presents an 8 channel ASIC for SiPM anode readout. The Multiple Use SiPM Integrated Circuit (MUSIC) is based on a low input impedance current conveyor (patented). It provides a differential channel summation and individual SE (analog or ToT) channel readout. MUSIC is designed using AMS 0.35um SiGe technology. Full die simulation yields these specifications: 500MHz bandwidth for...
This paper presents a 10-bit 250-MS/s time-interleaved pipelined ADC. A distributed clocking scheme is developed to eliminate timing skew between channels without introducing load capacitance to the driving buffer. The channel offset and gain mismatch error is calibrated in digital domain. In addition, a switch-embedded opamp-sharing technique is developed to reduce ADC power consumption and...
We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct
charge sensor integrated 72x72 pixels each capable of directly collecting charge through exposed
metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of
the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through
comparators...
We successfully demonstrated simple and low cost 2.5 Gb/s optical wireless transmission at 10 cm distance, aiming to be employed in high-energy physics experiments using off-the-shelf VCSEL and PIN photodiode with proper ball lens. The measured tolerance to misalignment is around ±1mm at Bit Error Rate of 10^-12.
The Versatile Link project has developed a radiation-hard optical link for LHC phase 1 detector upgrades. The project has reached its final stage and we have launched the series production of the Versatile Transceivers (VTRx) and Versatile Twin Transmitters (VTTx). This paper provides an update of the production status and a detailed description and results of the quality assurance programme....
A novel, 2-step DC-DC conversion powering scheme will be used for the “2S” silicon strip modules of the HL-LHC CMS tracker. Each module is equipped with a service hybrid, which carries two DC-DC converters along with a LP-GBT and a VTRx+ module. The first DC-DC converter generates 2.5V, required for the opto-electronics, while the second stage converts 2.5V to 1.25V, required for all other...
The Belle II experiment will use a Silicon Vertex Detector based on DEPFET pixel (PXD) and double-sided microstrip (SVD) technology. In 2014 at a combined SVD/PXD beam test we observed electrical noise in the SVD system which caused many headaches for more than two years. Since then Electromagnetic Compatibility (EMC) tests using some of the best equipment available in an EMC tight hall, but...
A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (Shunt-LDO). Power consumption is studied at different stages of the...
The CMS Electromagnetic Calorimeter utilizes scintillating lead tungstate crystals, with avalanche photodiodes (APD) as photo-detectors in the barrel part. 1224 HV channels bias groups of 50 APD pairs, each at a voltage of about 380V. The APD gain dependence on the voltage is 3%/V. A stability of better than 60 mV is needed to have negligible impact on the calorimeter energy resolution. Until...
Paper presents the Silicon Tracking System low-voltage power system design starting from the power budget and noise spectrum requirements resulting from the front-end chip design (STS/MUCH-XYTER2). Power-supply rejection ratio simulation results, estimation on how the simulated and measured noise spectra of the voltage regulators would affect the front-end electronics, power budget and...
Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex. To achieve a high MTBF of the system, a set of industrial testers for the converters controls electronics is used. The paper is a follow-up after a similar paper at TWEPP2015, including more test platforms(Boundary-Scan) and the outcome after test phase in production. We report...
HEP experiments requirements lead to highly integrated systems with many electrical, mechanical and thermal constraints. A complex performance optimisation is required. High speed data transmission lines are designed, while simultaneously minimising radiation length. Methods to improve the signal integrity of point to point links and multi-drop configurations are described. FEA calculations...
The ATLAS Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL) that is read out via two boards: the Readout-Driver card (ROD) and the Back-of-Crate card (BOC). In this presentation we summarize first the experience of building and commissioning the boards to read out the ATLAS Pixel detector, with particular emphasis to the ROD card.
In addition, here it is...
The necessity to improve the accuracy of the Total Ionizing Dose (TID) measurements at CERNs’ radiation zones, has driven the research of new TID-measuring candidates. For this purpose, a TID Monitoring System (TIDMon) is designed, that investigates the effects of the TID on a Floating Gate Dosimeter (FGDOS) compared to Radiation-sensing Field-Effect Transistors (RadFETs). The monitoring...
Our work targets soft errors in embedded systems operating in particle accelerator physics experiments. We propose to use the safety mechanisms included in the low cost Cortex-R4F to mitigate Single Event Effects, as well as additional procedures to recover data from external memories. These procedures include making an interleaved backup of the program data by using the DMA controller. In...
The CMS pixel detector phase 1 upgrade in 2017 requires an upgraded DAQ to accept higher data rates. A new DAQ system has been developed based on a combination of custom and standard microTCA parts. Custom mezzanines on FC7 AMCs provide a front-end driver for readout, and front-end controller for configuration, clock and trigger. The DAQ system is undergoing a series of integration tests...
The TORCH detector to provide low-momentum particle identification is an R&D project, combining Time- of Flight and Cherenkov techniques to achieve charged particle pi/K/p separation up to 10 GeV/c. The measurement requires a timing resolution of 70ps for single photons. Based a scalable design, a Time of Flight (TOF) measurement system has been developed to instrument a novel customized...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per...
In continuous readout systems of particle physics experiments, providing a common clock, time reference and the distribution of critical low latency messages to the processing and fronted layers of the readout is a crucial task. In the context of CBM, a versatile small form factor TFC interfacing FMC was developed, offering bidirectional twisted-pair (TP) links for communicating between TFC...
Towards development of a 10MGy rad-hard ASIC, evaluation of innovative 3D integration technology and CMOS - active edge pixel sensor characterization, a versatile DAQ system is presented. Based on a Saprtan 6 PCIe board, an FMC mezzanine card is developed providing a 68-channel digital input. Featuring automatic bi-directionality and variable output level (0.9V - 4.8V) with high impedance...
For the CMS and TOTEM Precision Proton Spectrometer Project, a digital readout board was designed to take front-end data of the Diamond Detectors and Quartz Timing Cherenkov Detectors, reformat the data timing packets, and transmit them to the CMS and TOTEM data acquisition systems through optical data links. This board is capable of having HPTDC or SAMPIC mezzanines for high-resolution timing...
In the Phase 1 Upgrade of the CMS Hadron Calorimeters, the ngFEC is the system responsible for distributing the LHC clock, the synchronization signals and the slow controls to the frontend electronics using a GBT bidirectional link. It is based on the FC7, a μTCA AMC developed at CERN and built around the Xilinx Kintex-7 FPGA. Its main features are: a fixed latency for fast signals across...
The AdvancedTCA (ATCA) standard has been selected as the hardware platform for the upgrade of the back-end electronic of the CMS and ATLAS experiments of the Large Hadron Collider (LHC). In this context, the electronics systems for experiments group for experiments at CERN is running a project to evaluate, specify, design and support xTCA equipment. As part of this project, an Intelligent...
The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to DAQ. To prototype various aspects of this readout system of the ITS, an FPGA...
We present the design and the performance of a silicon strip telescope that we have built and recently used as reference tracking system for prototype sensor characterisation. The telescope was operated on beam at the CERN SPS and also using cosmic rays in the laboratory. We will describe the data acquisition system, based on a custom electronic board that we have developed, and the online...
Systems designed to control and monitor particles detectors often make use of a back-end server to interact with the front-end electronics and to deliver the DAQ interface and real-time information to the user. We propose to port the functionalities of the back-end server to web interfaces and to the front-end electronics by implementing them on a dual soft-core processor : one core running an...
The Global Trigger is the final decision stage of the Level-1 Trigger of the CMS Experiment at the LHC. Previously implemented in VME, it has been redesigned and completely rebuilt in microTCA technology, using the Virtex-7 FPGA chip family. This allows implementing trigger algorithms close to the final analysis selection, combining different physical objects. The flexible and compact new...
AFP, the ATLAS Forward Proton consists of silicon detectors at 205 m and 217 m on each side of ATLAS. In 2016 two detectors in one side were installed. The FEI4 chips are read at 160 Mbps over the optical fibers. The DAQ system uses a FPGA board with Artix chip and a mezzanine card with RCE data processing module based on a Zynq chip with ARM processor running Linux.
In this contribution we...
We present the results for the prototype of a processor capable of reconstructing events in a silicon strip tracker at about 1 MHz rate with sub-microsecond latency. The processor is based on an advanced pattern-recognition algorithm, called “artificial retina”, inspired to the vision system of the mammals. We design and implement this processor on a DAQ board designed to run at 1 MHz event...
The Pulsar IIb is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs. In this talk we describe the Pulsar II hardware and its performance, such as the performance test results...
For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP, Russia) near threshold is necessary to measure the particles flight time in the LXe-calorimeter with accuracy of about 3ns. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the...
Background originating from events outside of the interaction point is going to play a major role in the upcoming Belle II experiment. In order to reduce this background a track trigger based on the reconstruction of an event's z position is employed on FPGAs. This paper presents the architecture and implementation of neural networks and supporting preprocessing that is going to be used at the...
After the Phase-I ATLAS upgrade the Tile calorimeter will have to provide its data via fast optical links to the new Feature Extractor (FEX) modules of the L1Calo trigger system. In order to provide the FEXes with digitised Tile data, new Tile Rear Extension (TREX) modules need to be developed and installed in the existing L1Calo PreProcessor system. The TREX modules are highly complex PCBs,...
Modern data acquisition and trigger systems require a throughput of several GB/s and latencies down to the microsecond level. In order to satisfy such requirements, we developed a heterogeneous system with FPGA-based readout cards and GPU-based computing nodes coupled by fast links. Remote DMA engines are used for direct communication between Xilinx FPGAs and GPUs from AMD / "DirectGMA" and...
Optical links are ubiquitous in particle physics data acquisition systems spanning experiment control, data-acquisition and trigger applications. With today’s computing power, future data acquisition systems could benefit from collecting data from large segments of the detectors and involve them in trigger systems. This places challenges on optical links for High Energy Physics requiring high...
The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 um process from TowerJazz. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process.
The DTU...
The ATLAS Level-1 Trigger system performs event selection using data from calorimeters and the muon spectrometer to reduce the LHC collision event rate down to about 100 kHz. Trigger decisions from the different systems are combined in the Central Trigger Processor for the final Level-1 decision. A new FPGAs-based AdvancedTCA sub-system was introduced to calculate in real time complex...
We report on our recent progress in developing an optical transmission system based on wavelength division multiplexing (WDM) to enhance the read-out data rate of future particle detectors. The design and experimental results of the prototype of a monolithically integrated multi-wavelength transmitter are presented as well as temperature studies of electro-optic modulators and optical...
A new CMS Tracker is under development for the High Luminosity LHC from 2025. It includes an outer tracker based on "PT-modules" which will construct stubs, built by correlating clusters in two closely spaced sensors. Reconstruction of tracks from stubs is required if the tracker is to contribute to the Level1 trigger under increased luminosity. A concept for an FPGA-based track finder using a...
Many experiments require high data rates, implying custom link design using transmission line theory.
Transmission line theory is presented including FEA analysis of energy dissipation in exemplar designs. The choice of transmission line designs are reviewed.
Transmission line design principals and testing equipment are presented. The characterisation techniques of time-domain reflectometry...
Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track finding algorithms, particularly for silicon based tracking triggers. In the talk we present our latest PRAM-based pattern recognition mezzanine card design which supports both ASIC and FPGA based PRAMs, and describe how the PRAM interface and FPGA...
The TTC-PON (Timing, Trigger and Control system based in passive optical networks) was first investigated in 2010 in order to replace the current TTC system, responsible for delivering the bunch clock, trigger and control commands to the LHC experiments. A new prototype of the TTC-PON system is now proposed, overcoming the limitations of the formerly presented solutions. A new upstream data...
Field-programmable gate arrays (FPGAs) based on flash memories provide a high radiation tolerance. We discuss potential application of the Microsemi IGLOO2 FPGAs in high energy experiments. We implement a 24 channel time-to-digital converter with a time binning of 0.78 ns and evaluate the performance. The time resolution is obtained to be 0.25 ns. The radiation tolerance against total ionizing...
In Run 3, the ATLAS Level-1 Calorimeter Trigger will be augmented by an Electron Feature Extractor (eFEX), to identify isolated e/g and t particles, and a Jet Feature Extractor (jFEX), to identify energetic jets and calculate various local energy sums. Each module accommodates more than 420 differential signals that can operate at up to 12.8 Gb/s, some routed over 20 cm between FPGAs....
The NA62 experiment aims to measure rare kaon decays, in order to precisely test the standard model. The RICH detector of the experiment is instrumental in charged-particle identification and in measurement of their crossing time, with a resolution better than 100ps. Here we describe the design of the Level-0 trigger system for the RICH, which provides a precise time reference by counting the...
This paper presents the results of an irradiation campaign up to 1 Grad on single transistors manufactured in a 28nm commercial CMOS technology. This technology is of interest for future upgrades for HL-LHC. NMOS transistors have been irradiated and electrical parameters have been measured. Moderate threshold voltage shift and sub-threshold slope degradation have been observed, while leakage...
Modern High Energy Physics Trigger Systems require high data throughput on the Gigabyte scale and latencies in the range of a few microseconds.
Traditionally, those requirements could only be met by expensive, dedicated hardware like FPGAs and ASICs.
However, GPUs provide high-performance and pose an affordable and easily programmable alternative.
In this paper we evaluate modern GPGPUs as...
H35Demo chips are HV-CMOS devices produced in the 350nm AMS technology with the purpose of inquiring the opportunity to introduce this technology in the next ATLAS tracker upgrade. Each chip includes four different pixel matrices and three test structures. The results of TCT (Transient Current Technique) and edge-TCT analysis on the test structures from with different substrate resistivity...
Results from the completed Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed in two stages, with the first running in 2015 for pp and Heavy Ions and the final stage for 2016 data-taking. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Stages of the upgrade were commissioned in parallel with...
The ATLAS detector at the LHC is in the process of integrating new components to handle the increased collision energies and luminosities being delivered since 2015. The Fast TracKer (FTK) is a hardware processor built to reconstruct tracks at a rate of up to 100 kHz and provide them to the high level trigger. FTK uses FPGA's to match inner detector hits with pre-defined track patterns stored...
In this contribution we present the design of a 8-channel amplifier-comparator chip specifically optimized to match the signals produced by Ultra-Fast Silicon Detectors (UFSD). The time resolution of the TOFFEE – UFSD system is expected to be around 30 ps. The chip is designed in UMC 110nm CMOS technology, it has a 2x2 mm area and it requires 40 mW per channel. It features LVDS outputs and...
The LHCb upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in triggerless mode, with full event selection being performed offline. The Vertex Locator (VELO) will be upgraded to a pixel device with a new dedicated ASIC, the VeloPix, a 130 nm technology chip with data driven and zero suppressed readout. The sensors are positione at just 5.1 mm from the LHC...
This paper describes the AM06 chip, a highly parallel processor for
pattern recognition in high energy physics. AM06 contains memory banks
that store up to 2^17 patterns made up of 8x18 bit words and integrates
SER/DES IP blocks for 2.4 Gb/s IO to avoid routing congestion.
AM06 combines custom memory arrays, standard logic cells and IP blocks
within a 168 mm^2 silicon area with 421 million...
In the context of investigating a more efficient rad-hard power distribution scheme for HL-LHC trackers modules based on switching DC/DC converters, we developed two new prototypes, upFEAST2 and DCDC2S. The combination of upFEAST2 and two DCDC2S can provide the three required voltages (2.5V for the opto-electronics, 1V for digital and 1.2V for analog circuitry).
DCDC2S and upFEAST2 are...
When scaling down CMOS towards smaller and smaller dimensions, the electrical fields inside the devices is increasing which leads to potential failures of the transistors. This can limit the lifetime of the circuits that are made in these technologies. As a result reliability is becoming more and more a fundamental limiting factor for the further downscaling of the technology. This lecture...
