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Mr Lukas Perktold (CERN)29/09/2011, 16:00ASICsPosterThe NA62 experiment needs to provide time stamping of individual particles to 200ps-rms or better per station. Bump-bonded to the pixel sensor each ASIC serves an array of 40 columns x 45 pixels. Discriminated signals from each pixel are sent to the lower edge of the ASIC to an array of time-to-digital converters (TDCs). The outputs of 5 pixels are multiplexed together yielding a total of 9...Go to contribution page
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Mr Claudio Gotti (INFN Milano Bicocca and Università di Firenze)29/09/2011, 16:00ASICsPosterAn integrated charge sensitive preamplifier was designed in 90 nm CMOS technology. The chip is part of the R&D effort towards the upgrade of the pixel sensors of the CMS detector. It was submitted in april 2010, and was received and tested in autumn 2010. In the design of the amplifier block, a single ended structure was preferred over a differential one, in order to achieve a lower noise....Go to contribution page
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Dr Hervé Chanal (Laboratoire de Physique Corpusculaire de Clermont-Ferrand), Mr Yannick Denis Zoccarato (Institut de Physique Nucleaire de Lyon (IPNL)-Universite Claude)29/09/2011, 16:00ASICsPosterFEAFS chip has been designed for a future sCMS Silicon Strip Tracker. Its primary function is to provide a 40 MHz selective readout of particle hits useful to establish the 100kHz hardware trigger of the experiment. To achieve this goal, the chip identifies clusters of limited number of activated strips and correlated in position in two closely superimposed sensors connected to the same chip....Go to contribution page
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Mr Maximilian Buechele (Physikalisches Institut der Albert-Ludwigs-Universitaet Freiburg)29/09/2011, 16:00LogicPosterThe GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted-clock-sampling method. A particular challenge of this algorithm is the predictable placement of the logic components and the uniform routing inside the...Go to contribution page
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Dr Riccardo Travaglini (INFN-Bologna)29/09/2011, 16:00SystemsPosterhe ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL).A new front-end ASIC has been foreseen (named FE-I4) and it will be readout with improved off-detector electronics. In particular, the new Read-Out Driver module (ROD) is a VME-based board designed to process a four-fold data throughput....Go to contribution page
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Mr Daniel Paer Erik Eriksson (Department of Physics-Stockholm University-Unknown)29/09/2011, 16:00SystemsPosterUpgrade plans for ATLAS hadronic calorimeter (TileCal) include full readout of all data to the counting room. We are developing a possible implementation of the future readout and trigger electronics aiming at a full functional demonstrator during Phase 0, starting from an existing functional test slice assembled using a combination of prototypes and emulators. Presently the first version of...Go to contribution page
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Giovanni Mazza (INFN sez. di Torino, Italy)29/09/2011, 16:00OptoPosterThe GigaBit Transceiver (GBT) project aims at the design of a radiation tolerant chip set for high speed optical data transmission. The chipset includes the GigaBit Laser Driver (GBLD), a radiation tolerant ASIC designed in a standard CMOS 130 nm technology. The GBLD is a laser driver designed to work to up to 5 Gb/s and capable to drive both VCSELs and some types of edge emitting lasers. The...Go to contribution page
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Jan Scheirich (Czech Technical University in Prague, Faculty of Electrical Engineering)29/09/2011, 16:00ASICsPosterThe DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor will be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. The DEPFET sensor requires switching and...Go to contribution page
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Mr Frédéric Druillole (CEA Saclay)29/09/2011, 16:00SystemsPosterTo prepare future experiment, we need to qualify new solid state detectors and gaseous TPC. From T2K experiment and GET project, we develop a small board constituted of two 64 AGET asic, a 4-channel pipeline adc and a smart commercial board called “AVNET minimodule” to sequence the acquisition and send data in TCP/IP mode through the Ethernet network. The size of the board is 15 cm x 8 cm....Go to contribution page
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Dr Yifan Yang (Université Libre de Bruxelles)29/09/2011, 16:00SystemsPosterThis talk describes a high speed ethernet-based data and clock network for applications which require an array of multiple sensor nodes distributed over distances of up to 250 m from a central hub. Speeds of up to 100 Mbit/sec and clock skew at the level of 50 ps are acheivable using commercially available network-grade twisted pair cables and low-power ethernet transceiver circuits. No...Go to contribution page
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Mr Andreas Ebling (J.G.U. Mainz)29/09/2011, 16:00LogicPosterThe existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based.\\ The LHC machine plans to bring the beam energy to the nominal value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged.\\ To cope with the...Go to contribution page
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Mr Tuomas Sakari Poikela (University of Turku / CERN)29/09/2011, 16:00ASICsPosterWe examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most...Go to contribution page
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Jerôme Pibernat (CENBG/CNRS/IN2P3)29/09/2011, 16:00ASICsPosterIn experiments with radioactive beams from heavy ions facilities it is shown that active targets and TPCs experimental methods are effective means to study nuclear spectroscopy. The principle advantages are good resolution, versatility and high luminosity. To address the needs of the nuclear Physics community we are in the process of developing a Generic Electronic system for TPCs (GET) to...Go to contribution page
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Mr David Pierre Martin (Lab. Phys. Nucl. Hautes Energies (LPNHE)-Univ. P. et Marie Curi)29/09/2011, 16:00ASICsPosterThe ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%. The architecture, chosen by LSST, is based on a “Correlated Double Sampling” with a “Dual Slope Integrator” method. Many modular tests benches have been developed to qualify this chip and...Go to contribution page
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Dr Sandro Bonacini (CERN)29/09/2011, 16:00RadiationPosterAs triple well technologies became available in recent years as an option for several submicron technologies, the question of their robustness against SEU with respect to single well versions has been asked, but a systematic comparison has been missing from the literature. This work present the first systematic comparison of the sensitivity to Single Event Upsets of latch cells designed in a...Go to contribution page
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Mr FU Yunan (Institut Pluridisciplinaire Hubert Curien)29/09/2011, 16:00PackagingPosterThe paper presents a design of CMOS Pixel Sensor (CPS) using the vertical integration technology (3DIT), expected to alleviate the most essential limitations of 2D-CPS. Our objective is to develop an intelligent architecture in order to meet the requirements of the innermost layer of the International Linear Collider (ILC) vertex detector, which are particularly demanding in spatial resolution...Go to contribution page
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Mr Jens Verbeeck (K.U.Leuven), Prof. Paul Leroux (K.U. Leuven)29/09/2011, 16:00ASICsPosterThe design of a radiation tolerant configurable discrete time signal conditioning circuit in 130nm CMOS technology for use with resistive sensors like strain gauge pressure sensors is presented. The circuit is intended to be used for remote handling in harsh environments in the International Experimental Thermonuclear fusion Reactor (ITER). The design features a 1.5V differential preamplifier...Go to contribution page
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Dr Tiankuan Liu (Southern Methodist University (US))29/09/2011, 16:00OptoPosterIn this paper we present the R&D towards cryogenic digital data links for a Liquid Argon Time Projection Chamber (LArTPC). An electrical data link with a commercial LVDS driver and a 20-meter CAT5E twisted pair can work up to 1 Gbps at liquid nitrogen temperature or 77 K. Components of a cryogenic optical data link, including a serializer ASIC, laser diodes, optical fibers, and optical...Go to contribution page
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Dr Remi Jean Noel Cornat (Laboratoire Leprince-Ringuet (LLR)-Ecole Polytechnique-Unknown)29/09/2011, 16:00SystemsPosterCalorimeters for a future International Linear Collider developed within the CALICE collaboration will feature about 10^8 channels. A scalable control and data acquisition system was developed. Is is based on GigaEthernet and a specific serial link packing slow control, fast control and read out data. Most of the hardware and firmware components are shared among the various detectors. The...Go to contribution page
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Georges Blanchot (CERN)29/09/2011, 16:00PowerPosterThe development at CERN of low noise DC-DC converters for the powering of front-end systems enables the implementation of efficient powering schemes for the physics experiments at the HL-LHC. Recent tests made on the ATLAS short strip tracker modules confirm the full electromagnetic compatibility of the DC-DC converter prototypes with front-end detectors. The integration of the converters in...Go to contribution page
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Dr Erdem Motuk (University College London)29/09/2011, 16:00SystemsPosterThe development of the Clock and Control (CC) hardware and firmware for the EuXFEL DAQ system is presented. The system exploits the data handling advances provided by the new telecommunication architecture standard for physics. The CC is responsible for synchronising the DAQ system to overall system timing. The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear...Go to contribution page
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Mr Martin Postranecky (Department of Physics and Astronomy, University College London)29/09/2011, 16:00SystemsPosterATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ("DAVE"). The unit was designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP functionality, with random trigger, simple and complex deadtime, ECR, BCR etc. being generated to give exactly...Go to contribution page
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John Coughlan (STFC Rutherford Appleton Laboratory)29/09/2011, 16:00SystemsPosterThe Train Builder is an Advanced Telecom ATCA based custom data acquisition system designed to provide a common readout system for the large 2D Mega-pixel detectors presently under construction for the European-XFEL facility in Hamburg. Each detector outputs 10 GBytes/sec of raw data over multiple 10 Gbps SFP+ optical links. The Train Builder DAQ system will merge detector link image fragments...Go to contribution page
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Olivier Raymond Bourrion (Laboratoire de Physique Subatomique et de Cosmologie (LPSC)-Univ)29/09/2011, 16:00ASICsPosterA front end ASIC has been designed to equip the µTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the “Time Over Threshold” information for each of those. This 64 digital information, sampled at a rate of...Go to contribution page
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Ivo Polak (Institute of Physics)29/09/2011, 16:00PowerPosterWe will present some new ideas on the design of different parts of DC/DC converter which operates on Very High Frequency. I show different topologies, and its power efficiency influence, which is being achieved during design stage of 2 years project called Brahms. There are recent interesting results, but not final solution yet. The presentation is focused to the perspective of power...Go to contribution page
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Mr Dominik Przyborowski (AGH University of Science and Technology)29/09/2011, 16:00ASICsPosterThe design and measurements of 8--bits DACs based on L--2L ladder architecture are presented. The main design goals were low power consumption and low area. Such features allow using the DAC for channel parameter trimming in multichannel readout system. The PMOS and NMOS based DACs are studied in wide range of biasing conditions and for two operation modes -- as current generator and current...Go to contribution page
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Christian Neher (University of California at Davis)29/09/2011, 16:00PackagingPosterAs silicon detectors in HEP require increasingly complex assembly procedures, the availability of a wide variety of interconnect technologies provides more options for overcoming obstacles in generic R&D. I present recent progress and challenges faced in various interconnect technologies: gold stud and double gold stud bonding, deposition and bonding of indium bumps, solder ball bonding and...Go to contribution page
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Sergio Gonzalez Sevilla (DPNC, University of Geneva)29/09/2011, 16:00SystemsPosterThe Large Hadron Collider (LHC) will extend its current physics programme by increasing the peak luminosity by one order of magnitude. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker. The super-module programme is an integration concept for the barrel short-strip region of the future ATLAS tracker in which double-sided silicon micro-strip modules are...Go to contribution page
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Mr Christian Irmler (HEPHY Vienna)29/09/2011, 16:00OptoPosterIn the Belle II SVD readout chain the analog singnals will be transmitted over long lines. This leads to signal distortion, caused by the frequency dependent transfer function of the cable and also by reflections, which occour whenever the line impedance changes. One possibility to compensate these effects is a dedicated filter at the receiver end. This presentation describes the approach to...Go to contribution page
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Mr Alan Prosser (Fermilab)29/09/2011, 16:00OptoPosterModern particle detectors utilize optical fiber links to deliver event data to upstream trigger and data processing systems. Future detector systems can benefit from the development of dense arrangements of high speed optical links emerging from industry advancements in transceiver technology. Supporting data transfers of up to 120 Gbps in each direction, optical engines permit assembly of the...Go to contribution page
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Dr Nicolas Pillet (Lab. de Physique Corpusculaire (LPC))29/09/2011, 16:00ASICsPosterThe ATLAS upgrade will require more efficient electronics to fulfil the new performances expected by the experiment. Concerning the readout electronics of the Tile Calorimeter, the replacement of the 3in1 board by an integrated circuit is under study. The proposed circuit is composed of a multi-gain current conveyor, followed by shapers, an integrator for the calibration and an...Go to contribution page
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Dr Ketil Røed (CERN)29/09/2011, 16:00RadiationPosterIn the main tracking detector of ALICE, the Time Projection Chamber (TPC), an SRAM based FPGA from Xilinx is implemented in the Readout Control Unit (RCU)of the front-end electronics and controls the read out of data from the detector. This paper will present the first measurements of single event upsets in this FPGA. The results will be compared to previous simulations and discussed in light...Go to contribution page
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Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)29/09/2011, 16:00LogicPosterThis poster describes the implementation of a flexible system for the electromagnetic calorimeter (ECAL) Off Detector (OD) electronics firmware update and the corresponding software tools designed to manage the update operation. The idea is to equip each ECAL VME64x crate with the new JTAG Distribution Board (JDB) that access XILINX and ALTERA FPGAs JTAG chains for trigger (TCC68/48) and data...Go to contribution page
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Dr Huaishen LI (IHEP, C.A.S.)29/09/2011, 16:00ASICsPosterThe upgrade of Beijing Synchrotron Radiation Facility(BSRF) need two-dimensional position-sensitive detection equipment to improve the experimental performance. New structures and new technology GEM detector, in particular, pixel-based(Pad) GEM detector, has good prospects in the domain of synchrotron radiation and high energy physics experiments for its simple structure, superior performance...Go to contribution page
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Mr Francesco Zappon (Nikhef)29/09/2011, 16:00ASICsPosterGOSSIPO-4 is a prototype chip featuring an array of high resolution Time to Digital Converters (TDC) with a PLL control that will be taped out on the 9th of August 2011. This prototype is the successor of GOSSIPO-3 test chip and the precursor of the 65k pixel TimePix3 chip. The prototype is being developed to test a set of new features that will be used in TimePix3, including a 8 pixel...Go to contribution page
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Dr David Cussans (University of Bristol)29/09/2011, 16:00ASICsPosterInitial tests the CBC binary readout chip connected to a sensor are presented.Go to contribution page
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Dr Pablo Vazquez Regueiro (University of Santiago de Compostela, IGFAE)29/09/2011, 16:00RadiationPosterThe Pixel Detector (PXD) of the Belle II experiment at superKEKB accelerator in Japan is based in the DEPFET technology. Two layers of 8+12 modules at a radius of 13 and 22 mm will give a spatial resolution below 10 µm. The radiation level expected in the first layer in ten years of operation is about 10 MRad of total ionizing dose. In order to study the tolerance of the DEPFET technology...Go to contribution page
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Mr Tobias Harion (Kirchhoff Institute for Physics)29/09/2011, 16:00ASICsPosterKLauS is an ASIC in AMS 350nm Bicmos Technology with 12 Silicion Photomultiplier (SiPM) readout channels. It is designed to be used in the plastic sintillator based Analog Hadron Calorimeter (AHCal) at a future Linear Collider. Its dynamic range reaches 200pC and SNR is better than 10 for single photon signal of very low gain SiPMs. The chip provides 2V bias tuning to compensate SiPM...Go to contribution page
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Paolo De Remigis (INFN)29/09/2011, 16:00SystemsPosterThe Micro Vertex Detector is the innermost part of the Panda experiment and is constituted of pixels and strips. The design foresees a triggerless data acquisition, and Topix is the current Asic solution for the pixel readout featuring more than 10k cells with a serial data output exploiting the GigaBit Transceiver project, at present under development at CERN, that will manage the data...Go to contribution page
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Dr Peter Wieczorek (GSI Darmstadt, Germany)29/09/2011, 16:00ASICsPosterFor the electromagnetic calorimeter of the PANDA - Experiment the ASIC – Design – Group of the GSI – Experiment – Electronics department developed an integrated preamplifier and shaper ASIC. The chip developed for spectroscopy using is optimized for the readout of large area avalanche photo diodes (LAAPD) with a capacitance of 280 pF and an event rate of 350 kHz. Each ASIC has two equivalent...Go to contribution page
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Mrs Nathalie Seguin-Moreau (LAL)29/09/2011, 16:00ASICsPosterMICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active part of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital...Go to contribution page
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Dr Babak Rahbaran (HEPHY Vienna--Institute of High Energy Physics Vienna)29/09/2011, 16:00TriggerPosterAt LHC 40 million collisions of proton bunches occur every second, resulting in about 800 million proton collisions. The Level-1 trigger, a custom designed electronics system based on FPGA technology and the VMEbus system, performs a quick on-line analysis of each collision every 25 ns and decides whether to reject or to accept it for further analysis. As part of the Global Trigger Upgrade,...Go to contribution page
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Mr Pavel Stejskal (CERN)29/09/2011, 16:00RadiationPosterOptical link components used in future particle physics experiments will typically be exposed to intense radiation fields during the lifetime of the experiment and the qualification of these components in terms of radiation tolerance is thus required. We have created a model that describes the degradation of the L-I characteristic of a semiconductor LASER undergoing irradiation with the...Go to contribution page
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Timo Tick (CERN)29/09/2011, 16:00PackagingPosterThe next generation hybrid pixel detectors in particle physics experiments require reduced mass budget, increased interconnection density and they need to be tileable to seamlessly cover large areas. These criteria cannot be fulfilled with present day interconnection techniques. As a result the particle physics community has recently put in a lot of effort to investigate and evaluate variety...Go to contribution page
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Mr Erik van der Bij (CERN)29/09/2011, 16:00SystemsPosterThe accelerator control systems at CERN will be renovated and many electronics modules like analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on VITA and PCI-SIG standards such as FMC, PCI Express and VME64x. The Wishbone specification is used as SOC bus. To attract partners, the projects are...Go to contribution page
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M. Citterio (INFN Milano)29/09/2011, 16:00PowerPosterThe paper describes power switching converters suitable for possible power supply distribution networks for the upgraded detectors at the High Luminosity LHC collider. The proposed topologies have been selected by considering their tolerance to the highly hostile environment where the converters will operate as well as their limited electromagnetic noise emission. The analysis focuses on the...Go to contribution page
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Maria Cristina Esteban Lallana (Instituto Tecnologico de Aragon)29/09/2011, 16:00PowerPosterThe characterization of electromagnetic noise of DC-DC converters is a critical issue that has been analyzed during the design phase of CMS tracker upgrade. Previous simulation studies showed important variations of conducted emission of DC-DC converters among impedances and power network topologies. Several tests have been performed on real DC-DC converters to validate the Pspice model and...Go to contribution page
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Andrea Brogna (Karlsruher Institut für Technologie, Institut für Prozessdatenverarbeitung und Elektronik)29/09/2011, 16:00PowerPosterWe discuss the power supply and distribution for new linear accelerators in particular with respect to the innovative architecture of the pulsing mode. The possibility to exploit the small duty-cycle becomes a critical factor to optimize the peak and mean power over the connections and cabling to reduce the loss, undesidered heating generation and interference and other sources of noise. We...Go to contribution page
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Dr Jan Troska (CERN PH/ESE)29/09/2011, 16:00OptoPosterThe CMS Pixel detector phase 1 upgrade calls for an optical readout system operating digitally at or above 320 Mb/s. Since the re-use of the existing link components as installed is excluded, we have designed a new Pixel Optohybrid (POH) for use within this system. We report on the design and choice of components as well as their measured performance. In particular, we have studied the...Go to contribution page
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Gianluca Traversi (University of Bergamo and INFN Pavia)29/09/2011, 16:00ASICsPosterIn a DNW MAPS a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. Various solutions complying with different sensor layout and pixel pitch have been fabricated in a planar (2D) 130nm CMOS technology. This work will discuss the design and characterization of deep N-well (DNW) monolithic active pixel sensors (MAPS)...Go to contribution page
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Mr Nicolai Schroer (ZITI, LS Informatik V, Heidelberg University, Mannheim)29/09/2011, 16:00SystemsPosterThe pixel detector of the ATLAS experiment at CERN will be upgraded with an additional layer (IBL) in 2013. To handle the data readout the currently used VME card pairs consisting of a back of crate card (BOC) and a read out driver (ROD) are being redesigned. We present details of the hardware design of the new BOC prototype. It takes advantage from modern FPGA technology and commercial...Go to contribution page
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Ms Eva Vilella (University of Barcelona)29/09/2011, 16:00SystemsPosterThe gated operation is proposed as an effective method to reduce and uniformize noise figures in particle tracking pixel detectors based on Geiger mode avalanche photodiodes for future linear colliders. A protoype based on a 3x3 array with the sensor and the front-end electronics monolithically integrated has been fabricated with the conventional HV-AMS 0.35µm technology. Experimental results...Go to contribution page
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Mikhail Matveev (Rice University)29/09/2011, 16:00LogicPosterWe present the status of hardware and software tools for remote access to Xilinx programmable devices in the Cathode Strip Chamber Endcap Muon Electronic System at the CMS experiment at CERN.Go to contribution page
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Dr Jan Troska (CERN PH/ESE)29/09/2011, 16:00OptoPosterThe Versatile Transceiver will be deployed on detectors that will be operated at the upgraded HL-LHC where the instantaneous luminosity will be increased by a factor of 5-10 with respect to the nominal LHC. All components housed at the front-ends must thus be immune to single-event upsets to a level compatible with the correct operation of the detector systems. We will carry out an...Go to contribution page
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Gisele Martin-Chassard (Unknown)29/09/2011, 16:00ASICsPosterThe SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10^19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which...Go to contribution page
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Mr Lukas Püllen (Bergische Universitaet Wuppertal)29/09/2011, 16:00SystemsPosterIn the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be an new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network...Go to contribution page
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Dr Elena Pedreschi (Sezione di Pisa (INFN)), Dr Franco Spinella (Sezione di Pisa (INFN))29/09/2011, 16:00SystemsPosterThe main goal of the NA62 experiment at the CERN SPS is to measure the branching ratio of the K+ → π+νν decay, collecting about 100 events in two years of data taking. The nature of the experiment puts stringent requirements on the trigger and data acquisition system: the efficient online selection of interesting events and loss-less readout at high rate will be key issues. Readout uniformity...Go to contribution page
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Dr Alexander Grillo (UCSC)29/09/2011, 16:00ProductionPosterThe Semi-Conductor Tracker in the ATLAS experiment at the Large Hadron Collider is potentially subject to various beam loss scenarios. It is important to understand what the effect of such an event would be on the operation of the SCT detector. Previous tests have shown the ABCD ASIC to be the weak point of the SCT modules when exposed to the intense radiation of a beam loss incident....Go to contribution page
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Mr Mikhail Lemarenko (Physikalisches Institut-Universitaet Bonn)29/09/2011, 16:00SystemsPosterA major upgrade of the current Japanese B-Factory (KEK-B) is planned by the fall of 2013. Together with this new machine (SuperKEK-B), also a new detector, BelleII, will be operated to fully exploit the higher luminosity (40 times larger than the previous experiment). One of the major changes in the new experiment will be the introduction of a new sub-detector, close to the interaction point,...Go to contribution page
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Dr Hans Muller (CERN), Dr José Francisco Toledo Alarcón (Valencia Polytechnic University)29/09/2011, 16:00SystemsPosterThe Scalable Readout System (SRS) was developed within RD51 collaboration as a multi-channel readout system, allowing ASICs, hybrids or discrete frontends with analog, binary or digital readout over a customizable link interface. User-specific frontends are linked to adapter cards which are straddle-mounted to Front-end Concentrator cards (FEC). The ensemble (Adapter + FEC card) forms a 6Ux220...Go to contribution page
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Mr Damien Thienpont (IN2P3/LAL)29/09/2011, 16:00ASICsPosterA low-power and low-area circular memory has been designed in a 130 nm technology. This prototype aims to be integrated into a plannar pixel sensors readout 3D integrated circuit for the future ATLAS high luminosity upgrade. Three types of memory cell have been designed: one with Typical transistors, an other with low-Vt transistors and the last one with custom enclosed transistors. The...Go to contribution page
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Vladimir Ryjov (CERN)29/09/2011, 16:00SystemsPosterThe NA62 experiment will be focused on precision tests of the Standard Model via studies of ultra-rare decays of the charged kaons. The high resolution Liquid Krypton (LKr) calorimeter of the NA48 experiment will provide a photon-veto with hermetic coverage from zero out to large angles from the decay region. The study of an upgraded readout system began in 2008. This paper presents the...Go to contribution page
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Dr David Gascon (Universidad de Barcelona)29/09/2011, 16:00ASICsPosterThe future international high energy gamma ray observatory, the Cherenkov telescope Array (CTA), will consist in an array of 50-100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photodetectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000...Go to contribution page
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Mr Jan Michel (Goethe University Frankfurt)29/09/2011, 16:00TriggerPosterThe data transport and trigger system of the HADES di-electron spectrometer operating at GSI, Germany was upgraded recently. The main goal was to substantially increase the event rate capabilities to reach trigger rates of up to 100 kHz and data rates of 400 MByte/s. The whole data communication system is based on FPGA-equipped platforms connected by optical links. Here, a custom network...Go to contribution page
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Mr Andrej Seljak (IJS Institute Ljubljana)29/09/2011, 16:00SystemsPosterWe are developing the readout electronics for the proximity focusing hybrid avalanche photon detector (HAPD), the baseline photon sensor of the Belle II aerogel RICH. The detector, positioned in the spectrometer forward direction inside the 1.5 T magnetic field, has to efficiently detect the single photons. The readout electronics has to digitize small analog signals and transfer them to the...Go to contribution page
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Dr Mauro Raggi (Laboratori Nazionali di Frascati (LNF)-Istituto Nazionale Fisic)29/09/2011, 16:00SystemsPosterThe branching ratio for the decay K+ -> pi+ nu anti-nu is sensitive to new physics; the NA62 experiment will measure it to within about 10%. To reject the dominant background from channels with final state photons, the large-angle vetoes (LAVs) must detect particles with 1-ns time resolution and 10% energy resolution over a very large energy range. Our custom readout board uses a...Go to contribution page
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Dr Giuseppe Giraudo (INFN-Torino)29/09/2011, 16:00PackagingPosterThe Micro Vertex Detector (the MVD) for the Panda experiment is optimized for the detection of the secondary vertices and for maximum acceptance close to the interaction point. The experimental set-up requires sophisticated solutions for the detector integration in order to maintain a stringent material budget. The thermal power produced by the “on board” read-out electronics is fast removed...Go to contribution page
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Mikihiko Nakao (KEK)29/09/2011, 16:00SystemsPosterAt Belle II, most of the digitization is made inside or near the detector, and the digitized data are collected via high-speed optical serial links. Each of the frontend electronics boards equips at least one FPGA for a unified data link implementation, and at the same time to receive a system clock, the level-1 trigger and other fast timing signals and provide fast status signals. These...Go to contribution page
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Mr Peter Lemmens (KVI, University of Groningen)29/09/2011, 16:00SystemsPosterThe PANDA collaboration at the future FAIR facility at Darmstadt, Germany, will employ antiproton annihilations to investigate yet undiscovered charm-mesons and glueballs. The rich physics program requires various sophisticated event-selection criteria based e.g. on invariant mass, secondary vertices, and time correlations. Therefore, the readout electronics is designed such that all detectors...Go to contribution page
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Dr Vasilii Kushpil (Academy of Sciences of the Czech Republic (ASCR))29/09/2011, 16:00ProductionPosterNew electronic single board tester described here allows us to test and compare basic characteristics of new types of the APD (SiPMD, MCAPD, GAPD). The tester was realized in a portable form with graphics LCD and three controls buttons. It can measure statical and dynamical characteristics of the APD. We applied virtual periphery concept for very fast and simple way to measure the S/N...Go to contribution page
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111. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgradeTiankuan Liu (Southern Methodist University (US))29/09/2011, 16:00ASICsPosterThe upgrade of ATLAS Liquid Argon (LAr) calorimeter readout calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. We are addressing the problem by iterative design previously reported at TWEPP with a commercial 0.25 μm silicon-on-sapphire CMOS technology we have evaluated to be...Go to contribution page
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Dr Roberto Ammendola (INFN Roma Tor Vergata)29/09/2011, 16:00LogicPosterWe present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level 0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on-board on DDR2 latency memories and readout upon reception of a Level...Go to contribution page
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Mr Peter Lemmens (KVI, University of Groningen)29/09/2011, 16:00LogicPosterCharm-meson resonances and yet undiscovered glueballs might reveal the origin of the hadronic mass spectrum. The PANDA collaboration at the future FAIR synchrotron facility at Darmstadt, Germany, will employ antiproton annihilations to investigate resonances in the charmonium mass region. In order to gain high flexibility for physics event selection, a trigger-less data-acquisition system is...Go to contribution page
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