Conveners
First Poster Session
- Ken Wyllie (CERN)
Peter Phillips
(STFC - Rutherford Appleton Lab. (GB))
23/09/2014, 16:30
ASICs
Poster
The first batch of wafers of ABC130, a Front End ASIC for the ATLAS Silicon Strip Upgrade in IBM 8RF 130nm CMOS technology, were received in November 2013. A design error with the bidirectional SLVS transceiver blocks was identified and corrected, then the design was resubmitted. The corrected wafers are expected to be delivered in June 2014.
The poster will describe the custom driver...
Dr
Christophe Flouzat
(CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
23/09/2014, 16:33
ASICs
Poster
The new 64-channel DREAM (Dead-timeless Readout Electronics ASIC for Micromรฉgas) chip has been designed to read the Micromรฉgas tracker of the CLAS12 experiment. Each channel associates a low noise very frontend part, optimized for large detector capacitances (150pF range), together with a 512-cell analogue memory, ensuring both a trigger latency and derandomization bufferization, allowing a...
Mr
Javier Rodriguez Samaniego
(IFIC)
23/09/2014, 16:34
Systems
Poster
NEW is the second phase of NEXT, an experiment aiming at searching neutrinoless double-beta decay. Neutrinoless events can only be told from very close energy background events by using to a topological signature produced at the SiPM tracking plane, making this one of the strongest features in NEXT: a high background rejection. The present work describes in detail the front-end electronics in...
Yasuyuki Horii
(Nagoya University (JP))
23/09/2014, 16:35
Trigger
Poster
The Level-1 trigger for muons in ATLAS is based on trigger chambers (RPCs, TGCs) with excellent time resolution which are able to identify muons coming from a particular beam crossing. It is proposed to use precision tracking chambers (MDTs) for improving the transverse momentum resolution at the Level-1 trigger for the phase II of the LHC, the so-called High-Luminosity LHC. We present the new...
yifan yang
(Universite Libre de Bruxelles)
23/09/2014, 16:36
Systems
Poster
We will present a multi-points wireless temperature monitoring system being designed for the optohybrid for the CMS forward moun detector upgrade project. Optohybrid is a readout board which will be installed inside CMS to control 24 front-end electronics chips and transfer the concentrated data to off-detector electronics through high speed optical fiber. An efficient cooling system is...
Karol Krizka
(University of Chicago (US))
23/09/2014, 16:37
Trigger
Poster
The ATLAS Fast TracKer is a hardware-based track finder for the ATLAS High Level Trigger. Pattern recognition and preliminary track fitting are performed by VME Processing Units consisting of an Associative Memory Board (AMB) containing custom associative memory chips for pattern recognition, and the Auxiliary Card (AUX), a powerful rear transition module which formats the data for the AMB...
Dmitry Osipov
(NRNU MEPHI)
23/09/2014, 16:38
ASICs
Poster
The design considerations on ADCs as a building block for mixed-signal read-out ASICs in high energy physics are presented. The choice of successive approximation architecture is justified as optimal in terms of a power-speed trade-off, arising in multi-channel data acquisition systems for up-to-date physical experiments. As an example, the development of an area-efficient SAR ADC in 180nm...
Christian Amstutz
(KIT - Karlsruhe Institute of Technology (DE))
23/09/2014, 16:39
Logic
Poster
A simulation framework has been developed to test and characterize algorithms, architectures and hardware implementations of the vastly complex track trigger processor foreseen for the high luminosity upgrade of the CMS experiment at LHC. High-level SystemC models of all system components and input data from physics simulations have been used to evaluate figures of merit, like delays or...
Eduard Atkin
(NRNU MEPHI)
23/09/2014, 16:42
ASICs
Poster
The goal of the NUCLEON satellite mission is the measurements of the elemental energy spectra of high-energy (10**11 -10**15 eV) cosmic rays. It requires a high dynamic range of the readout electronics. The silicon strip detectors were used, the readout ASIC developed and both placed on the ladder. The ADC, data control interface, detector loads, high voltage distributer and service...
Pedro Miguel Vicente Leitao
(FCT Fundacao para a Ciencia e a Tecnologia (PT))
23/09/2014, 16:43
ASICs
Poster
A radiation-tolerant ASIC is being designed for LHC clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR) with determinist phase and low jitter. It operates in two FM modes: either generating 40, 120 and 240MHz outputs (for GBT-FPGA applications) or providing 40, 80, 160 and 320 MHz (for TTC and eLinks applications). The CDR operates with 40, 80, 160 or 320Mbit/s data...
Jose Luis Sirvent Blasco
(University of Barcelona (ES))
23/09/2014, 16:45
Power
Poster
A high reliability Buck DC/DC converter, ready to be used on several CERN electronic boards equipped with FPGAs, has been designed and verified. Long lifetime design, according to CERN requirements, has been implemented by minimising component stress with 50% derating. It is a compact power supply module of 16 x 19 mm, which can deliver up to 6A with 95% efficiency.
Its main features include...
Dr
Liang Zhang
(Shandong University)
23/09/2014, 16:46
ASICs
Poster
The first CMOS pixel sensor prototype integrated with 4-bit column-level ADC for the outer layers of the ILC vertex detector has been fabricated and tested. The design is adapted to an original concept of minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. Inside each pixel an amplification stage with a correlated double sampling is used. At the bottom of...
Gilles De Lentdecker
(Universite Libre de Bruxelles (BE))
23/09/2014, 16:47
Systems
Poster
We will present the readout system being designed for triple-GEM detectors that should be installed in the CMS muon endcap system for the LHC high luminosity phase. The system takes full advantage of current generic developments introduced for the LHC upgrades: micro-TCA, MP7 and AMC13 boards, Versatile Link, GBT, etc. Some hardware components have to be specifically designed: the VFAT3 chip,...
Federico Alessio
(CERN)
23/09/2014, 16:48
Systems
Poster
The LHCb experiment is upgrading part of its detector and the entire readout system towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity and increase its trigger efficiency. In this paper, the new timing, trigger and control distribution system for such an upgrade is reviewed with particular attention given to the distribution of the...
Mehmet Ozgur Sahin
(Deutsches Elektronen-Synchrotron (DE))
23/09/2014, 16:49
Systems
Poster
The CMS hadron calorimeter detector control system provides 40.08 MHz LHC clock to the front end electronics as well as supplying synchronization signals and I2C communication. Pedestals and diagnostic bits are controlled, and temperatures and voltages are read out. SIPM temperatures are actively stabilized by temperature readback and generation of correction voltages to drive the Peltier...
Jim Hirschauer
(Fermi National Accelerator Lab. (US))
23/09/2014, 16:50
ASICs
Poster
The CMS experiment will upgrade the photodetection and readout systems of its hadron calorimeter through 2018. A central feature of this upgrade is the development of two new versions of the QIE, a custom ASIC for measurement of charge from detectors in high-rate environments. With 3 fC sensitivity, 17-bits of dynamic range, a time-to-digital converter with sub-nanosecond resolution, and...
Sebastian Stefan Feger
(CERN)
23/09/2014, 16:51
Production
Poster
This work presents the software environment surrounding the GBT chipset, addressing the requirements of GBTX, GBLD and GBT-SCA. The GBTX is a high speed bidirectional ASIC, implementing radiation hard optical links for high-energy physics experiments. Having more than 300 8-bit configuration registers, it poses challenges addressed by a wide variety of software components. This software keeps...
Konrad BRIGGL
(Heidelberg University)
23/09/2014, 16:53
ASICs
Poster
We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end "KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit resolution is required. For calibration purposes, a 12-bit quantization...
Mark Istvan Kovacs
(CERN)
23/09/2014, 16:54
Packaging
Poster
The upgrade of the CMS tracker for the HL-LHC is based on a binary readout scheme based on the CMS Binary Chip. The connectivity requirements of this flip-chip ASIC requires the use of high density interconnecting hybrids. Module integration studies indicated that a foldable flexible hybrid circuit results in an optimal module arrangement. A full module size HDI flexible hybrid was designed,...
Datao Gong
(Southern Methodist Univeristy)
23/09/2014, 16:55
ASICs
Poster
We present the design and test results of a digital encoder ASIC, LOCic, for high-speed serial data transmission in ATLAS LAr calorimeter readout upgrade. This chip implements a low latency and low overhead line code. The user data is scrambled and encoded into a 128-bit data frame including CRC for error detection. The encoder overhead is 12.5%. A 12-bit BCID information is embedded in the...
David Gascon
(University of Barcelona (ES))
23/09/2014, 16:56
ASICs
Poster
A versatile and reconfigurable ASIC implementing multiple concepts of low level trigger (L0) for Cherenkov telescopes is presented. Two different Level-0 approaches have been included in the L0 ASIC: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analog clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger...
Dr
Arno Gadola
(Physik-Institut, Universitรคt Zรผrich)
23/09/2014, 16:57
Systems
Poster
The Cherenkov Telescope Array (CTA) is the next generation ground-based observatory for cosmic gamma rays. The FlashCam camera for its mid-size telescope introduces a new concept, with a modest sampling rate of 250 MS/s, that enables a continuous digitization as well as event buffering and trigger processing using the same front-end FPGAs. The high performance Ethernet-based readout provides a...
Nicola Pozzobon
(Universita e INFN (IT))
23/09/2014, 16:58
Trigger
Poster
The High Luminosity LHC (HL-LHC) is expected to deliver a luminosity in excess of 5x10^34 cm^{-2}/s. The high eventrate places stringent requirements on the trigger. A key component of the CMS upgrade for the HL-LHC is a track trigger to identify tracks with transverse momentum above 2 GeV already at the first-level trigger within 5 us. This presentation will discuss a proposed track finding...
Gianluca Traversi
(Universita e INFN (IT))
23/09/2014, 16:59
ASICs
Poster
This work presents the design of a low-power, differential signaling, input/output data link in a 65 nm CMOS process for high-energy physics (HEP) experiments. The proposed driver is able to operate at 320 Mbps or 640 Mbps achieving a normalized power dissipation of 1.875 mW/Gbps. A pre-emphasis technique has been adopted to reduce the impedance mismatch between the driver output and the...
Alessandro Caratelli
(Sezione di Pisa (IT))
23/09/2014, 17:00
ASICs
Poster
This work describes a radiation tolerant, monitoring and control ASIC for applications in HEP experiments. The GBT-SCA is part of the GBT optical link chip-set. Its purpose is to distribute control and monitoring signals to the on-detector front-end electronics for the upgrades of the LHC experiments. It is designed employing radiation hardening techniques and is fabricated in a commercial...
Mr
Jean-Baptiste Cizel
(LLR/Weeroc)
23/09/2014, 17:01
ASICs
Poster
Building blocks in the Silicon On Insulator 0.18 ฮผm X-fab technology have been designed to study the future generation of SKIROC2 ASIC. These blocks are designed to characterize this technology as a possible candidate for the design of the final read-out ASIC of the Silicon Tungsten (SiW) Electromagnetic Calorimeter (ECAL) foreseen at the International Linear Collider. The performance of these...
Dr
Markus Friedl
(Austrian Academy of Sciences (AT))
23/09/2014, 17:02
Systems
Poster
At the heart of the Belle II experiment at KEK, there is a Vertex Detector composed of 2 layers of DEPFET pixels (PXD) and 4 layers of double-sided silicon strip detectors (SVD). The latter use APV25 front-end chips, originally developed for CMS, which are run in the so-called *multi-peak mode* that delivers several samples along the shaped waveform. Those are processed in the backend firmware...
Paolo Durante
(CERN)
23/09/2014, 17:03
Logic
Poster
We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN.
We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-express as an interconnect technology for high speed readout.
We show throughput measurements across the PCI-express bus in both directions, on Altera Stratix 5...
Sylvain Mico
(CERN)
23/09/2014, 17:04
Power
Poster
The LHC acceleratorโs first long shutdown period (LS1), in 2013-2014, has given the experiments the opportunity to perform planned upgrade and maintenance activities on systems and equipment. It has also been the right to conduct a preventive maintenance campaign on crate and power supply equipment which is foreseen to operate smoothly for another 4 to 8 years. This paper will present the...
Cairo Caplan
(CBPF - Brazilian Center for Physics Research (BR))
23/09/2014, 17:05
Logic
Poster
The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control...
Mitchell A. Cox
(University of the Witwatersrand)
23/09/2014, 17:06
Systems
Poster
The Large Hadron Collider at CERN generates enormous amounts of raw data which present a serious computing challenge. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design...
Stefano Magnoni
(Universidad de Oviedo (ES))
23/09/2014, 17:07
Radiation
Poster
CLIC is a world-wide collaboration to study the next โterascaleโ lepton collider, relying upon a very innovative concept of two-beam-acceleration. This accelerator, currently under study, will be composed of the subsequence of 21000 two-beam-modules. Each module requires more than 300 analogue and digital channels which need to be acquired and controlled in a synchronous way.
CLIC-ACM is the...
Dr
Dirk Wiedner
(Ruprecht-Karls-Universitaet Heidelberg (DE))
23/09/2014, 17:08
ASICs
Poster
Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay mu->eee. In order to reject both combinatorial and physics background, decay vertex position, decay time and particle momenta have to be precisely measured. A pixel tracker based on 50 um thin high voltage monolithic active pixel sensors (HV-MAPS) in a magnetic field will deliver precise vertex and...
Dr
Jinyuan Wu
(Fermilab)
23/09/2014, 17:09
Logic
Poster
Signals with various timing relations can be generated inside FPGA conveniently with internal phase lock loop
(PLL) blocks. When multiple PLL blocks are cascaded together. In this paper, clocks
generated by cascaded PLL with slightly difference in frequencies are studied. They are used to produce
pulse pairs with precise timing delay control at 0.98 ps/step. They are also used to...
Annika Rosner
(DESY)
23/09/2014, 17:10
Systems
Poster
For special needs at the European XFEL invented an RF-Backplane. It is an optional extension for the 9U crates in the MicroTCA.4 standard. The passive RTM backplane is suited for interconnection of high-precision RF and CLK signals for ฮผRTM and the new extended RTMs. It improves cable management and system reliability and offers more space for electronics. Furthermore with this backplane come...
Gary Drake
(Argonne National Laboratory (US))
23/09/2014, 17:11
Radiation
Poster
We present results from recent radiation tolerance tests that we have performed on prototype boards and components for the front-end electronics intended for the upgrade of the hadronic calorimeter (TileCal) for the ATLAS experiment at the LHC. The tests include Total Ionizing Dose (TID) tolerance, Non-Ionizing Energy Loss (NIEL) tolerance, and Single Event Effects (SEE) tolerance. We...
Filippo Costa
(CERN)
23/09/2014, 17:12
Systems
Poster
ALICE (A Large Ion Collider Experiment) is the detector system at the LHC (Large Hadron Collider) that studies the quark-gluon plasma. The information sent by the sub-detectors composing ALICE are read out by DATE (Data Acquisition and Test Environment), the ALICE data acquisition software, using hundreds of multi-mode optical links called DDLs (Detector Data Links). To cope with the higher...
Jose Carlos Rasteiro Da Silva
(LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)
23/09/2014, 17:13
Systems
Poster
The calorimeter trigger of the CMS experiment at the LHC uses Synchronization and Link Boards (SLB) to perform the synchronization of trigger primitives (TP) from the electromagnetic and hadronic calorimeters and transmit these TPs to the Regional Calorimeter Trigger (RCT). During the first long shutdown, the SLBs will be replaced by optical SLBs (oSLBs) and the receiver mezzanines (RM) in the...
Andrea Abba
(Universitร degli Studi e INFN Milano (IT))
23/09/2014, 17:14
Trigger
Poster
Our research aims to develop a specialized track processor capable of precisely reconstructing events with hundreds of charged-particle tracks in pixel and silicon strip detectors at 40 MHz. For this purpose we design and test a massively parallel, neurobiology-inspired, pattern-recognition algorithm. Here we present the R&D for a first prototype of silicon tracker with trigger capabilities...
Dr
Babak Rahbaran
(Austrian Academy of Sciences (AT))
23/09/2014, 17:15
Trigger
Poster
The Global Trigger (GT) is the final step of the CMS Level-1 Trigger and implements the โmenu'' of triggers, which is a set of selection requirements applied to the final list of objects (such as muons, electrons or jets) to trigger the readout of the detector and serve as basis for further calculations by the High Level Trigger. Operational experience in developing trigger menus from the...
Dr
Jaroslaw Szewinski
(NCBJ Swierk)
23/09/2014, 17:16
Systems
Poster
The MTCA electronics standard, except the high performance fast serial links on the backplane, provides also extensive management of the devices in crate.
Each AMC board must have MMC implemented to get power in the MTCA crate, which in many cases is barrier for new users to switch to MTCA.
This presentation/poster will show details and aspects of the MMC implementation developed at DESY for...
Nate Rider
(Cornell University)
23/09/2014, 17:17
Systems
Poster
We present the design of a 5 channel 800 MSPS uTCA based digitizer that will be deployed in the the Muon g-2 Experiment at Fermilab. The digitizer features 12-bit 800 MSPS digitizers with dedicated 1Gbit memory buffers. Multiple Xilinx Kintex-7 FPGAs provide the control and coordination within the digitizer. Provisions for a modular front end allow for application specific analog signal...
Thierry Romanteau
(Ecole Polytechnique (FR))
23/09/2014, 17:18
Systems
Poster
The CMS experiment implements a two-level online selection system. The first level is based on coarse information coming from the calorimeters and the muon detectors while the High Level Trigger combines fine-grain information from all sub-detectors. During Run II, the goal is to maintain the current thresholds (e.g., for electrons and photons) and improve the performance for the selection of...
