GEMINI is an integrated readout system designed for Triple-GEM detectors. To fully exploit the potential of this technology, GEMINI produces outputs for both arrival time and energy thanks to Time-over-Threshold (ToT) technique. This work presents an analysis of the effect of up-to-20 Mrad-TID absorbed by GEMINI chip in lab environment with X-rays. ToT data analysis before and after...
The ATLAS Inner Detector will be completely replaced by an all silicon tracker for the LHC upgrades in the mid 2020s. The increased resolution and data output rate of the innermost layers of the upgraded detector will require more cables that are low-mass and capable of multi-gigabit transmission.
An FPGA Mezzanine Card (FMC) was developed to interface with an FPGA and a cable bundle to...
The nEXO project is designed to search for the 0vฮฒฮฒ process of 136Xe. It requires high reliability and small volume in the readout electronic system. This research is to improve the integration and the reliability of the circuit. The core chip of the system is a highly integrated programmable chip based on SIP which include two ADC dies and a FPGA die. The complete system is constructed by...
SAR converters are usually the natural choice to implement monitoring ADCs. Additional circuits for calibration are needed to compensate process variations which become more important for large resolutions and deep-submicron technologies. This paper presents a 12-bits second-order incremental sigma delta converter for TimePix4 fabricated in TSCM 65nm. It does not need calibration and is robust...
The proposed CEPC presents new challenges for the pixel detector in terms of cell size and functionality. A high data rate digital design and readout architecture of a MAPS prototype for the CEPC vertex detector is presented. The column drain based readout architecture, benefiting from the ALPIDE and FE-I3 approach, has been implemented to achieve high spatial resolution, fast readout, and low...
Ultra-compact electronics is required for the control and readout of the Silicon-Tungsten electromagnetic calorimeter of the future ILD detector (CALICE collaboration). Prototypes have been designed years ago, comprising the ASUs (Active Sensor Units) located inside the detector Slab and housing the front-end ASICs, and an external part for controlling the system and reading out physics data....
A low-power front-end with on-chip fast pulse generation and customized SAR ADC is developed for SiPM readout design. The on-chip fast pulse generation improves the timing resolution without the need of extra I/O pins. The proposed SAR ADC, reusing the SiPM charge integrator and eliminating the power-hungry charging sensing amplifier, consumes significantly less power compared with...
ALTIROC2 is an ASIC designed to readout a pixel matrix of 15 x 15 Low Gain Avalanche Diodes (LGAD) for the High-Granularity Timing Detector in ATLAS. It measures the TOT and TOA with a resolution of tens of ps for each detected hit. Data are temporally stored in a buffer able to cope with latencies up to 35ยตs. The ASIC also measures the luminosity of each bunch crossing with two different time...
For the Phase-2 upgrade of ATLAS and CMS tracking detectors, a new pixel readout chip, with 50x50 um2 pixel pitch, is being designed in 65 nm CMOS technology by the RD53 collaboration. A large-scale demonstrator chip called RD53A, containing design variations in the pixel matrix, among which three different analog front ends, is now available. A dedicated program of testing and detailed...
The CMS electromagnetic calorimeter (ECAL) will be upgraded to maintain detector performance in the challenging environment of the High Luminosity LHC. The front-end readout electronics of the ECAL barrel will be replaced, while maintaining the existing crystals and avalanche photodiodes (APDs). Moreover, the upgrade will optimize the timing resolution of the system. The new front-end...
COLDATA is the third of three chips designed for operation within the Liquid Argon cryostat of the Deep Underground Neutrino Experiment (DUNE). It is the point-of-contact between the warm, external DUNE DAQ system and the cryogenically-cooled Front-end Boards. All information from warm-to-cold and from cold-to-warm passes through COLDATA. As such, it implements data concentration and frame...
A serial power scheme will be used for the new inner tracking detector for the Phase-II upgrade of the ATLAS experiment. New elements are required to operate and monitor a serially powered detector, including a detector control system (DCS), constant current sources and front-end electronics with shunt regulators. A demonstrator for the outer barrel is built at CERN to verify the concept and...
For the CERN LHC Run 3, the ALICE experiment completely redesigned the Inner Tracking System, which now consists of seven cylindrical layers instrumented with 24120 Monolithic Active Pixel Sensors, covering an area of $10m^2$.
The ITS is controlled and read out by 192 custom Readout Units, which employ commercial SRAM-based FPGAs and will operate in an ionising radiation field, requiring...
Jiangmen Underground Neutrino observatory (JUNO) is a neutrino medium baseline experiment constructing in China, with the main goal to determine the neutrino mass hierarchy. A large liquid scintillator volume instrumented by around 20000 large photomultiplier tubes will detect the antineutrinos issued from nuclear reactors.The JUNO electronics system has mainly two parts: the front-end system...
FELIX, the PCIe based framework has been used in the DAQ system of ATLAS Phase-I upgrade and the APA (Anode Plane Assemblies) readout in Single-Phase ProtoDUNE experiment. For the ATLAS HL-LHC upgrade, the fiber optical links from front-ends will have higher speed. This manuscript introduces a FELIX demonstrator board with PCIe interface designed for the HL-LHC upgrade. In this board, 25+ Gbps...
The Phase-2 CMS tracker back-end processing system is composed by two types of Detector, Trigger, and Control (DTC) boards interfacing the inner and outer tracker, and by the Track Finding Processor (TFP) board performing level-1 track reconstruction from the outer tracker data. Several groups are building hardware to prove key and novel technologies needed in the back-end processing system....
The UFSD group of Turin is working at the development of custom front-end electronics for the read-out of thin silicon sensors with moderate internal gain, aiming at high-precision time tagging applications. The development of specific ASIC for timing at INFN-Torino started in 2016. The first two ASIC prototypes, TOFFEE and ABACUS, have been successfully tested in our laboratories and at...
Ten โslice testโ triple-GEM detectors were installed into the CMS endcap in 2017. Data was recorded in 2017-2018, using both cosmic ray muons and LHC collisions. During the slice test, a loss of VFAT2 input channels was observed, with two detectors exhibiting rapidly-increasing channel loss beginning mid-2018.
Concurrent investigations into the cause of the channel loss were launched,...
We present an innovative and expandable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits. The implementation uses a new interleaved placement approach in comparison to a generally used bulk 3-bank constraining method. To optimally constrain the placement of sequential cells as well as combinational cells. The TMR netlist information is...
Single Event Effects represent one of the main challenges for digital designs exposed to ionizing particles in high energy physics detectors. Radiation hardening techniques are based on redundancy, leading to a significant increase in power consumption and area overhead. This contribution will present the SEE hardening techniques adopted in the pixel and strip readout ASICs of the PS-modules...
The lpGBT transceiver is a radiation tolerant ASIC designed to be used in High Energy Physics detector systems. It aggregates data from up to 28 eLinks to one high-speed link running at 5.12 or 10.24Gbps. In the downlink direction, it can be used for timing and trigger distribution by demultiplexing the incoming downlink bitstream running at 2.56Gbps onto up to 16 eLinks. Moreover, the lpGBT...
TCP has been widely used in readout systems. SiTCP is hardware-based TCP stack for Gigabit Ethernet, it realizes direct access and transfer of the data up to 949 Mbps in the memory of FPGA by utilizing TCP communication. The data rate multiplies with the development of pixel detectors for smaller pixels and higher frame-rates. The existing GbE design is no longer satisfied the requirement of...
To further improve the existing Quench Detection System (QDS) of individually powered magnets installed in the Large Hadron Collider (LHC), a new radiation tolerant electronic board was developed. The board provides three signal acquisition channels able to acquire with different and configurable signal resolution and acquisition rate the analog signals of different properties.
These...
The Institute of Electronic Systems (ISE) of shall design and deliver hundreds of pieces of various control, signal distribution, and safety modules to be used at the European Spallation Source research facility by the Low-Level RF control, Phase Reference, and Beam Diagnostic systems. This contribution presents the design, as well as strategies and results of acceptance testing of selected...
For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP, Russia) near threshold is necessary to measure the particles flight time in the LXe-calorimeter with accuracy of about 3ns. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the...
The MAROC chip was dedicated to MaPMT readout, and its third generation was backup solution in the front-end electronics of the RICH-LHCb Upgrade. Given the expected radiation environment for RICH, the MAROC3 was tested with 35 MeV proton beam at the Nuclear Physics Institute in Juelich, Germany. Investigated samples had the behavior recorded using a dedicated test bench. An increasing in...
The Vertex Locator of the LHCb will be upgraded in 2020. As the installation is approaching all the electronics have to be verified and tested. In this poster, the final test setup for all the components and the procedures accomplished will be described. Problems detected and solutions adopted will be explained.
This process goes from visual inspection test of the different boards or bare...
Silicon Photomultipliers (SiPM) are beginning to be actively used in high-energy physics experiments (CMS, LHCb, ATLAS in CERN), therefore careful study of the effect of high radiation fields on the operation of these devices is necessary. This work studies the effect of irradiation with fast neutrons on the work of SiPM (manufacturing: Hamamatsu Photonics K.K.) with an active area of 1 $mm^2$...
The RD53A read-out chip (65 nm CMOS) is a large-scale demonstrator for ATLAS and CMS phase 2 pixel upgrades. It is one of the key elements of the serial powering scheme for the next generation of pixel detectors. The susceptibility of the RD53A chip with respect to external EM noise has an impact on the integration strategies (grounding and shielding schemes) and operating conditions of future...
The Daughterboard (DB) is the readout link and control board that interfaces the front-end and off-detector electronics for the HL-LHC of the the ATLAS Tile Calorimeter. The DB sends high-speed readout of digitized PMT samples, while receiving and distributing configuration, control and LHC timing. A redundant design, Xilinx SEM, TMR, FEC and CRC strategies minimize single failure points while...
The compact structure of the HGTD proposed for the High Luminosity ATLAS detector upgrade at the CERN LHC requires a design to match the tight mechanical and electrical constraints. Our solution with a flexible printed circuit manages the signals to read out and control the modules, to bias the sensors with high voltage and to power the ASIC. It is crucial to match the characteristic impedance...
The Endcap Timing Readout Chip (ETROC), being developed for the CMS Endcap Timing Layer (ETL) for HL-LHC, is presented. Each endcap will be instrumented with a two-disk system of MIP-sensitive LGAD silicon devices to be read out by ETROCs for precision timing measurements. The ETROC is designed to handle a 16ร16 pixel cell matrix, each pixel cell being 1.3x1.3 mm^2 to match the LGAD sensor...
This paper presents the design and test results for the line driver (eTx) and the line receiver (eRx) in the lpGBT, fabricated in 65 nm CMOS technology. The two circuits implement the physical layer of the bi-directional eLink interface of the lpGBT. The eTx is a single-ended-to-differential driver with programmable pre-emphasis and driving current. The eRx is a differential-to-single-ended...
The Cavity Simulator reproduces the behavior of superconducting cavities and high power amplifiers used in the medium and high beta sections of European Spallation Source (ESS) linac. The device is foreseen to be used for tests and development of the ESSโs LLRF control system. High-performance Xilinx Kintex Ultrascale FPGA runs dedicated firmware, which performs all calculations including the...
A front-end ASIC for 4D tracking is presented. The circuit includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time-to-digital converter. A prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of a project aiming at reaching a high resolution both in space and in time, to provide front-end circuitry suitable for...
The first level (L0) muon trigger of the ATLAS experiment will be upgraded to operate at the High Luminosity LHC.
The selectivity of the current L0 muon trigger is limited by the moderate spatial resolution of RPC and TGC. The MDT chambers currently used for precision tracking will be therefore included to improve the momentum resolution and the redundancy.
A hardware demonstrator of...
The presentation summarizes the powering concept of the Silicon Tracking System for the future CBM experiment at FAIR/Germany. Efficient powering is an important task with the goal to minimize power dissipation and heat development. Also the limited space for power cable routing has to be taken into account. Chosen solutions determine the necessary cooling and cabling effort and therefore have...
The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics and relative applications. The experiments at the HIRFL-CSR drive the development of new detectors. Aiming to reduce the developing time and cost of each detector system, a Versatile Readout Platform (VRP) has been designed as a tentative common readout platform for the...
Results from the Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed before the 2016 data-taking and the system served until end of Run II in 2018. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Innovations are introduced, such as embedded linux on trigger processing boards and simultaneous...
This paper describes the deployment and optimization process of triple-module redundancy (TMR) under high design constraints against single-event upset (SEU) and single-event transient (SET). It includes modeling of single-event effects (SEE) pulses with TCAD mesh model, TMR deployment strategies, and verification methods. The simulation result shows that the prototype with optimized TMR...
The High Voltage (HV) system of TileCal, the ATLAS central hadron calorimeter, needs to be upgraded during the so called Phase II Upgrade of the LHC for the HL-LHC. In thw proposed solution, the HV regulation boards are moved away from the detector and deployed in the counting room, safe from radiation damages and with permanent access for maintenance. This option requires a new layout with...
The VMM3a is a System on Chip (SoC) custom Application Specific Integrated Circuit (ASIC). It will be used as the front ASIC for both Micromegas and sTGC detectors of the ATLAS Muon New Small Wheels upgrade at CERN. Due to its highly configurable parameters, it has been proposed a variety of tracking detectors and another experiments. It is fabricated in the 130nm Global Foundries 8RF-DM...
We present a 32-channel data acquisition system using the PSEC4A chip and initial applications as a readout system for neutron detectors at Sandiaโs Z Pulsed-Power Facility. The PSEC4A is an 8-channel, 10 GSa/s waveform recording ASIC with an analog bandwidth of 1.9 GHz, which also incorporates multi-event buffering to reduce latency induced by close-in-time triggers. In the 32-channel...
High Voltage-CMOS (HV-CMOS) sensors are the sensor technology of choice for the pixel tracker in the Mu3e experiment at PSI in Switzerland. In this contribution, timing resolution down to 0.5 ns is obtained. Simultaneously, power consumption is held below 28 ฮผW in a pixel size of 60 ฮผm2, enabling 4D tracking in a high-density array. Timing errors due to signal amplitude variations considered...
The ATLAS experiment will get a new inner tracker (ITk) during the phase II upgrade. The innermost part will be a pixel detector. A new Detector Control System (DCS) is being developed to provide control and monitoring of the ITk pixel detector. The DCS Controller is a CANopen based Application Specific Integrated Circuit foreseen to independently monitor a serial power chain. The final chip...
A high-density electrode array is being developed for Neutrinoless Double-Beta Decay search in high-pressure gaseous TPC. A sensor, Topmetal-S, is designed to have mm-sized electrode, followed by an amplifier and an ADC based on a 0.35um CMOS process. The Topmetal-S array can collect charge directly without gas avalanche gain to achieve high energy and spatial resolution simultaneously. To...
A mixed-signal ASIC developed to readout silicon photomultipliers (SiPM) at low temperature is presented. The chip is designed in a 110 nm CMOS technology. Both single photon counting and Time-over-Threshold (ToT) operating modes are supported. In single photon counting mode an event rate of up to 5 MHz per channel can be accommodated. The time resolution is 50 ps and the target power...
In the 2018 summer the PolarQuEEEst experiment accomplished a measurement
of cosmic rays flux in the Arctic. The detector, installed on a sailboat, was based on
scintillation tiles read by a total of 16 SiPM.
A multi-channel board (called TRB) has been designed to process the discriminated SiPM signals providing self-trigger capability and
time-to-digital conversion. It was based on a...
Results of analyzes of Time-of-Arrival measurements with Low-Gain-Avalanche-Diode sensors were carried out for the amplitude or time-over-threshold corrected leading edge measurements and for practical realization of Constant-Fraction-Discrimination based on ideal delay and RC-type low-pass filtering delay. The Expected current waveforms, resulting from modeling of a sensor and application of...
The design of the Level-0 endcap muon trigger system for the ATLAS experiment at HL-LHC and the status of the development are presented. The new system reconstructs muon candidates with an improved momentum resolution by combining signals from various subdetectors. The trigger efficiency is estimated with Monte-Carlo simulation to be >90%. The trigger rate is also estimated with proton-proton...
ATLASPIX3 is a 2cm x 2cm HVCMOS sensor designed to meet the specifications of layer 4, ATLAS inner tracker. ATLASPIX3 is a depleted monolithic CMOS pixel detector. The chip size allows the construction of quad modules of equal size as that of hybrid sensors. ATLASPIX3 supports triggered readout. The hit information is transmitted via 1.28 Gbit/s. The clock, trigger and configuration bits are...
The detector module of the Silicon Tracking System (STS) of the Compressed Baryonic Matter (CBM) experiment at FAIR (GSI) consists of large double-sided silicon microstrip sensors with a size up to 124 mm x 62 mm. Due to material budget constraints, the sensors are connected to the read-out electronics by long flexible microcables. As the manual assembly of the modules is time-consuming and...
LHCb detector is a general purpose experiment instrumented in the forward region
at the LHC, specialized in b- and c- physics, new physics and CP violation. The Vertex
Locator (VELO) detector is being upgraded along with the rest of the tracking system
and readout architecture during 2019-2020. The aim of this poster is to present the
architecture of the control and readout firmware on the...
SUPIX-1 is the first version of high spatial resolution monolithic active pixel detector prototype led by Shandong University Pixel Group which serves for CEPC tracker system. The chip has 18ฮผm epi-layer with the resistance of 1kฮฉยทcm using TowerJazz 0.18 ฮผm technology. Each chip has 9 sub-matrices, 64 rows by 16 columns for each matrix, which gives 16 parallel analog outputs with rolling...
CaRIBOu is a flexible data acquisition system for prototyping silicon pixel detectors. The core of the system consists of the Control and Readout (CaR) board, a versatile module providing the hardware environment for various target ASICs, including powering and slow-control infrastructure and high-speed full-duplex GTx links up to 12.5 Gbps. The CaR board connects to a Zynq system-on-chip...
Coming developments in X-ray photon sources will increase signal rate and intensity. Similar performance improvements are needed in a new multi-mega pixel imager. Its readout ASIC is to be based on charge-integration, be compatible with different sensor types, include adaptive-gain (to achieve single-photon resolution and high dynamic range), radiation-hard solutions and circuits for rapid...
We will present the design and the performance of two drivers in 65 nm TSMC technology, for Silicon Photonics Mach-Zehnder Modulator (MZM) devices, able to withstand radiation levels of up few 1016 n/cm2 and ~0.5 - 1 Grad. The drivers use a CML architecture and are optimized for >500 Mrad and a target a bit rate between 5 to 10 Gbps. They have been tested up to 800 Mrad showing about 25%...
This work is concerned with the design and the characterization of digital-to-analog current converters, developed in a 65 nm CMOS technology, conceived for threshold tuning of front-end channels at the HL-LHC experiment upgrades.
Two DAC structures were integrated in a small prototype chip, that was submitted in August 2018 in the framework of the RD53 developments. The prototype has been...
This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error....
The pixel-strip modules for the CMS Tracker Phase Two Upgrade for the HL-LHC integrate a readout hybrid (PS-ROH) for the control and data acquisition link. This hybrid is based on the new, low power and compact gigabit transceiver (lpGBT) and the Versatile Transceiver VTRx+ specifically designed for the upgrade. A characterization board was first designed to qualify the design rules and the...
Xilinx Zynq SoCs are used by the CMS TDAQ in its back-end electronics since LHC Run-2, between 2015-2018. For the Phase 2 upgrade of the LHC, about 1000 devices will be deployed, comparable to the number of High Level Trigger (HLT) nodes today. This scale presents challenges for the SoC integration in the experiment network, system administration, network management, booting process and root...
During the current major LHC shutdown (2019-2021), the ATLAS experiment at CERN is moving to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX functions as a router between custom serial links and a commodity switch network, which uses industry-standard technologies to communicate with data...
In this work, we present a customized pn depletion type Mach-Zehnder modulator (MZM) as well as a fully integrated wavelength division multiplexing (WDM) transmitter design with the merits of high bandwidth and radiation hardness, aiming to upgrade the optical data transmission of future detector systems. A detailed characterization of the modulators on modulation efficiency and RF response...
The Concentrator Integrated Circuit ASIC is a front-end chip for both Pixel-Strip and Strip-Strip modules of the future Phase-2 CMS Outer Tracker upgrade. It collects the digital data coming from eight upstream front-end chips, formats the signal in data packets containing the trigger information from eight bunch crossings and the raw data from events passing the first trigger level, and...
The upcoming upgrade of the readout system of the ATLAS experiment at the LHC at CERN is based on the Front-End LInk eXchange (FELIX) system. As part of this upgrade, approximately 120 custom PCIe cards are being produced by an industrial partner, based on a hardware design developed within the collaboration. Such a large production requires detailed Quality Assurance/Quality Control...
For the Long Shutdown 2 upgrade of the ALICE experiment, a new Inner Tracking System (ITS) is under development, based on the ALPIDE Monolitihic Active Pixel Sensor (MAPS) chip.
Data readout from the ALPIDE chips is performed by 192 Readout Units (RU), which are also responsible for trigger distribution, monitoring, configuration, and control of the sensor chips. Monitoring and control of...
KARATE (KArlsruher high RAte TEst) is a new system to stress the readout chain of strip modules for the future CMS Outer Tracker at HL LHC. The readout chain of a module starts with CMS Binary Chips (CBC) connected simultaneously to two sensors. The sparsified output is send out via an optical link. KARATE injects patterns with varying pulse heights, occupancies and trigger rates into the CBC...
Multimode interferometers (MMI) are key components for high-bandwidth transceivers in upgrading the data transmission of future detector systems. We present 2 conventional high-performance MMIs fabricated on a 250nm SOI platform with different splitting ratios which operate as 50:50 power splitter for Mach-Zehnder modulators and as 86:14 power splitter for loop control in future transceiver...
We successfully developed, built and tested a low power and stand alone DAQ system to be used with RPCs to measure the muonic component of air showers in the framework of MARTA. The MARTA system includes a front-end readout, high voltage, detector monitoring and a central unit to manage the different components of the system. The front-end is based on the MAROC ASIC coupled to an FPGA...
In this article we describe the measurement results on an โAARDVARCโ prototype in 130 nm. AARDVARC is a multi-channel waveform digitizing and processing Application Specific Integrated Circuit (ASIC) front-end. We report on various performance metrics: fast sampling (10-14 Gsa/s), deep storage (32K samples), timing resolution (better than 5ps), low power consumption (<100mW/channel).
Reliable measurement of clock signal parameters is important in precise-timing applications. Such parameters include frequency, phase, duty cycle and channel-to-channel skew. Especially in applications in which test time for multiple channels is a significant factor, efficient parallelization of measurements is crucial, while often coming with significant extra cost. This work presents an...
The KINTEX-7 FPGA is to be used in the new digital readout of the upgraded LHCb-RICH sub-detectors. This summary presents the measurements done to evaluate the reliability of this FPGA under ionizing radiation exposure with different types of particle beams: ions, protons and X-rays. Single-event effect cross-sections for critical resources - such as Flip-Flops, RAM blocks, configuration...
Triple-GEM has been adopted for the GE2/1 upgrade of the forward โจmuon detector at CMS for the High Luminosity LHC. GE2/1 chambers are segmented in 4 modules. Each module is equipped with the Optohybrid (OH) interfaced to 12 VFAT3 ASICs. The OH uses GBTs for the readout path and is equipped with a Xilinx Artix-7 FPGA for the trigger data processing.
In this presentation we report on our...
Modern VLSI technology allows the development of new class X-ray imaging detectors capable of capturing an image in various energy ranges in one shot. Such spectroscopic imaging detectors have a high demand for the spatial and energy resolution of individual photons. With decreasing size of pixels, the charge cloud generated by the primary photon interaction, and in high-Z materials also by...
The CMS Outer Tracker at HL-LHC will have to cope with 300 pile-up events per bunch crossing and to improved tracking performance while operating at a trigger rate up to $\mathrm{1~MHz}$. The front-end electronics readout chain consists of sensor readout ASICs connected to a data concentrator ASIC featuring zero-suppression. This contribution presents the methodology and the analysis work for...
At INFN-Torino, ASICs for readout applications of detectors were designed in several technologies, and are now under development. The 110 nm CMOS UMC technology is applied too. This technology has been chosen for its lower cost with respect to IBM or TSMC, even if there was not a systematic characterization for what concerns the radiation tolerance. Obviously, it is important to know the...
The COMET detector will include a electromagnetic calorimeter (ECal). The ECal signals will used for energy deposition measurement and for triggering. For triggering, the calorimeters signals will transformed into special short-shaped analog signals. These signals will then digitally processed with special algorithm, which allows one to obtain a set of logic signals necessary for event...
The Compressed Baryonic Matter experiment (CBM) will study rare probes in a heavy-ion environment at high interaction rates of up to 10 MHz. The observation of detached vertices requires a topological trigger, which is realized in software. CBM opted for a free-running readout, for reasons similar to LHC-b. The primary beam is delivered by a slow extraction synchrotron. To be able to operate...
VICE++ is a FPGA-based unit with interfaces compatible with the upgrade Very
Front End (VFE) and Front End (FE) boards. Once equipped with the appropriate firmware, it act as a test unit for debugging and tuning of different versions
of VFE and FE prototypes, and as a building block of the QC/QA systems for VFE and FE production. FPGA power allow run lpGBT-FPGA firmware, hence the unit can...
We present tests with a scanning micro-focus photon beam of the miniMALTA DMAPS prototype developed for ATLAS ITk. Tests were carried out at Diamond Light Source which provided a 2um beamspot to be scanned in 1um steps. This allows the in pixel efficiency to be measured directly with high statistics. Three pixel design variations were measured, the standard design, a deeper p well design and...
We will discuss the feasibility of a system capturing Level-1 intermediate data at the LHC beam-crossing rate of 40 MHz and carrying out online analyses based on these data. This 40 MHz scouting system has the potential to enable the study of otherwise inaccessible signatures. In such a system, data from the Level-1 trigger is preprocessed in an FPGA before being transferred to a computer for...
We present an overview of the approach of the Mu2e experiment at Fermilab to address radiation tolerance issues in the front-end electronics. The campaign includes simulations, specifications, testing, and mitigation strategies. The tests include tolerance measurements of Total Ionizing Dose (TID), Non-Ionizing Energy Loss (NIEL), and Single Event Effects (SEE). We describe how the...
Within the last years, the VMM and Timepix3 ASICs were implemented into the general purpose Scalable Readout System (SRS). Both flavours of the SRS will be presented. They are continuously improved and extended to increase their field of application.
Already with prototypes of these systems, detectors for different applications were read out during test beams of R&D towards the employment in...
