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Alex Kluge (CERN)20/09/2021, 11:20Oral
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Stella Orfanelli (CERN)20/09/2021, 11:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
A new Silicon Tracker will be built for the Phase 2 Upgrade of the CMS experiment. The innermost part, called the Inner Tracker, will be featuring high-granularity pixelated silicon sensors and will need to cope with extreme radiation levels and hit rates. The pixel electronics system is based on innovative solutions such as a new pixel ASIC developed by the RD53 collaboration, the novel...
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Fabrice Gensolen (Aix Marseille Univ, CNRS/IN2P3, CPPM, Marseille, France)20/09/2021, 12:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
To meet new TDAQ buffering requirements and withstand the high expected radiation doses at the high-luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. Developments of low-power preamplifiers and shapers and of a low-power 40 MHz 14-bit ADCs are ongoing. The signals will be sent at 40 MHz to the off-detector electronics, where FPGAs connected through...
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Luigi Vigani (Ruprecht Karls Universitaet Heidelberg (DE))20/09/2021, 12:20Systems, Planning, Installation, Commissioning and Running ExperienceOral
The Mu3e experiment searches for the lepton flavour violating decay µ→ eee with an ultimate aimed sensitivity of 1 event in 10^16 decays. This goal can only be achieved by reducing the material budget per tracking layer to X/X0 ≈ 0.1%. For this purpose, the vertex detector is based on HV-MAPS thinned to 50 µm. Also, the powering and data transmission is performed by means of kapton-aluminum...
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Dr Rui Zou (Cornell University (US))20/09/2021, 12:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
The challenging conditions of High-Luminosity LHC (HL-LHC) require tailored hardware designs for the trigger and data acquisition systems. The Apollo platform features a "Service Module" (SM) with a powerful system-on-module (SoM) computer that provides standard ATCA communications and application-specific "Command Module"s (CM) with large FPGAs and high speed optical fiber links. The CMS...
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Lars Rickard Strom (Deutsches Elektronen-Synchrotron (DE))20/09/2021, 14:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
The building blocks of the upgraded ATLAS Strip Tracker for HL-LHC are modules that host silicon sensors and front-end ASICs. The modules are mounted on carbon-fibre substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card on each substructure connects up to 28 differential data lines at 640 Mbit/s to lpGBT and VL+ ASICs that provide data serialisation and 10 GBit/s...
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Nadja Strobbe (University of Minnesota (US))20/09/2021, 14:20Systems, Planning, Installation, Commissioning and Running ExperienceOral
The frontend readout system for the silicon section of the CMS Phase II Endcap Calorimeter faces unique challenges due to the high channel count and associated bandwidth, limited physical space, as well as radiation tolerance requirements. This presentation will give an overview of the frontend electronics design and will discuss the recent experience obtained from the first test system that...
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Ioannis Mesolongitis (University of West Attica (GR))20/09/2021, 14:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
RPC detectors are used to trigger muons in the ATLAS Muon Spectrometer barrel region. The foreseen HL-LHC operation imposes replacing their trigger and readout electronics with a data collector and transmitter (DCT) system, which implements the LPGBT optical link to handle data bandwidth up to 10.24Gb/s. A testing system will be implemented to assess all DCT prototypes and mass production....
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Matthew Noy (CERN)20/09/2021, 15:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
An overview of the electronics readout/trigger architecture for the CMS HGCAL will be given. To respond to physics performance requirements, data rates, trigger-primitive generation and radiation tolerance has been extremely challenging. Each HGCAL endcap includes ∼300m² of active silicon in 50 layers, with a largely inhomogenous layout with limited commonality between layers. An agile,...
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Pierre-Alexandre Petitjean, Pierre-Alexandre Petitjean (Université Libre de Bruxelles)20/09/2021, 15:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
The main goal of the Jiangmen Underground Neutrino Observatory (JUNO) under construction in China is to determine the neutrino mass hierarchy. The detector consists of 20 ktons of liquid scintillator instrumented by 17612 20-inch photomultiplier tubes, and 25600 3-inch small PMTs, with photocathode coverage of 77%. The electronics system is separated into two main parts. The front-end system,...
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Nikitas Loukas (University of Notre Dame (US))20/09/2021, 16:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
For the Phase 2 of the LHC, the central electromagnetic (EB) and hadronic (HCAL) calorimeters of the CMS experiment require a new back-end electronics for its readout. The first version of the ATCA-based blade, the Barrel calorimeter processor (BCPv1), has been developed with a large flexibility to allow evaluation of the different strategies. The performance of the optical links as well as...
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Roberta Arcidiacono (Universita e INFN Torino (IT))20/09/2021, 16:20Systems, Planning, Installation, Commissioning and Running ExperienceOral
Future particle trackers will have to measure concurrently position and time with unprecedented resolutions, approximately 5 microns and 10 ps respectively. A promising good candidate are the AC-LGADs, silicon sensors of novel design, with internal gain and an AC-coupled resistive read-out to achieve signal sharing among pads. This design leads to a drastic reduction of read-out channels, has...
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Mark Istvan Kovacs (CERN)20/09/2021, 16:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
Sixteen thousand 2S front-end hybrids and twelve thousand PS front-end hybrids will be produced for the CMS Tracker Phase-2 Upgrade. The hybrids consist of flip-chips, passives and mechanical components mounted on a flexible substrate, laminated onto carbon-fibre stiffeners with thermal expansion compensators. In the prototyping phase, several critical issues have been solved to manufacture...
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Angelos Zografos (CERN)20/09/2021, 17:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
The CMS Tracker Phase 2 Upgrade modules integrate DCDC powering stages and an optical transceiver to power and control the front-end hybrids. The strip-strip (2S) module contains a Service Hybrid (2S-SEH) with two stage DC-DC power conversion, an lpGBT with optical interface (VTRx+), high voltage biasing and temperature sensor ports. The pixel-strip (PS) module utilizes a separate two stage...
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Vladimir Sidorenko (Karlsruhe Institute of Technology)21/09/2021, 11:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
The Compressed Baryonic Matter (CBM) experiment is designed to handle interaction rates of up to 10 MHz and up to 1 TB/s of raw data generated. With free-streaming data acquisition in the experiment and beam intensity fluctuations, it is expected that occasional data bursts will surpass bandwidth capabilities of the Data Acquisition System (DAQ) system. In order to preserve event data, the...
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Jeroen Hegeman (CERN)21/09/2021, 12:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
The CMS detector will undergo a major upgrade for Phase-2 of the LHC program: the HiLumi LHC. The Phase-2 CMS back-end electronics will be based on the ATCA standard, with node boards receiving the detector data from the front-ends via custom,
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radiation-tolerant, optical links. An ATCA hub board, the DAQ and Timing Hub, will provide the interface between the back-end nodes and the central... -
Michael Lupberger (University of Bonn (DE))21/09/2021, 12:20Systems, Planning, Installation, Commissioning and Running ExperienceOral
When the RD51 collaboration formed in 2008, the community initiated efforts for a standardised common readout system, the Scalable Readout System (SRS). The APV25 chip, originally designed for the CMS silicon strip detector, was the working horse within the first decade reading out gaseous detectors. Meanwhile, the VMM chip has taken over and further ASICs were (Timepix, SiPMs) or are...
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Frans Schreuder, Frans Schreuder (Nikhef National institute for subatomic physics (NL))21/09/2021, 12:40Systems, Planning, Installation, Commissioning and Running ExperienceOral
The Front-End Link eXchange (FELIX) system is a new ATLAS DAQ component designed
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to for detector readout in the High-Luminosity LHC era. FELIX acts as the interface
between the data acquisition, detector and trigger timing systems. FELIX routes data between
custom serial links from front-end electronics to data collection and processing components
via a commodity switched network. This... -
Ola Slettevoll Groettvik (CERN)21/09/2021, 14:00Systems, Planning, Installation, Commissioning and Running ExperienceOral
The ALICE Inner Tracking System has gone through a significant upgrade for the upcoming third running period of the CERN LHC. The new detector consists of seven layers of high-granularity pixel sensors, while 192 custom FPGA-based readout units control the sensors and transmit the data upstream for analysis. This contribution describes the current system status and the expertise gained by...
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Dr Arne Christoph Reimers (Universitaet Zuerich (CH))21/09/2021, 14:20
The entire CMS silicon pixel detector will be replaced to operate at High Luminosity LHC. The novel scheme of serial powering will be deployed to power the pixel modules and new technologies will be used for a high bandwidth readout system. In this contribution the new TEPX detector will be presented, with particular focus on a novel concept to provide both power and data connectivity to the...
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Stefano Caregari (National Central University (TW))21/09/2021, 14:40
A high power density resonant switched capacitor DC-DC converter (rPOL2V5) has been developed as a possible alternative to the bPOL2V5, of particular interest to the CMS High-Granularity Calorimeter (HGCAL) due to the relatively compact 12nH air-core inductor that it requires. The converter is based on an ASIC developed in a 130nm CMOS technology. It is powered by a 2.5V input, it can supply a...
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Pablo Daniel Antoszczuk (CERN)21/09/2021, 15:00
Two new radiation-hard DCDC converters are in development, which tolerate a higher input voltage (up to 48V) and provide a larger output power compared to existing solutions. They are called bPOL48V and rPOL48V, and they employ Gallium Nitride devices. bPOL48V can provide 12A of output current with 90% efficiency and is close to production readiness, while rPOL48V is in an early stage of...
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Theoni Prousalidi (National Technical Univ. of Athens (GR))21/09/2021, 15:40
Future upgrades of CERN Experiments will require low power optical data links to support ever-increasing data-rates at ever-higher radiation levels. Silicon Photonics is a CMOS optoelectronics technology compatible with such requirements. We present the results of an optical transceiver proof of concept based on a Silicon Photonic Integrated Circuit coupled to existing radiation tolerant ASICs.
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Mr Xing Huang (Southern Methodist University (SMU))21/09/2021, 16:00
QTRx is an optical transceiver for particle physics experiments. The transmitters, each at 10 Gbps, are based on QLDD and 1x4 VCSEL array. The receivers, with data rates between 2.56 Gbps and 10 Gbps, are based on QTIA and 1x4 photodiode array, GaAs or InGaAs. QTRx is 20 mm × 10 mm × 5 mm and couples to an MT fiber connector. Preliminary tests indicate that QTRx meets design data rates with a...
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Tiankuan Liu (Southern Methodist University (US))21/09/2021, 16:20
A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board. The board has 22 simplex optical links to transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector...
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Grace Cummings (University of Virginia)21/09/2021, 16:40
The Compact Muon Solenoid (CMS) Phase 1 Hadron Calorimeter Upgrade (HCAL) saw the first large-scale use of VTRx modules, optical transceivers designed to be radiation and magnetic field tolerant. During Run II of the Large Hadron Collider, the CMS HCAL experienced a short period of communication loss that revealed a manufacturing weakness in the VTRx affecting nearly half of the communication...
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Mr Herve Mathez (Centre National de la Recherche Scientifique (FR))21/09/2021, 17:20
The aim of this work is to develop an internal PLL for ASIC developments which integrates time measurement or which requires an internal clock in the range of GigaHertz. For future upgrades in High Energy Physic detectors experiments, time measurement becomes a decisive element, which will make it possible to reduce the data flow and improve the spatial accuracy of the interaction point. This...
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Arthur Serazetdinov (National Research Nuclear University MEPhI)21/09/2021, 17:20
2.56 Gbps CMOS CML-transceiver is presented. The key feature of the design is capability of working with a specific inductive load at both power consumption and radiation tolerance constraints. The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron (Dubna).
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Michela Greco (INFN- Torino; University of Torino)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
An innovative Cylindrical Gas Electron Multiplier (CGEM) detector is under construction for the upgrade of the inner tracker of the BESIII experiment. A novel system has been worked out for the readout, including a new ASIC, dubbed TIGER, designed for the amplification and digitization of the CGEM output signals. The data output by TIGER are collected and processed by a first FPGA-based...
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Thomas Gardiner (STFC)21/09/2021, 17:20
While the potential of PAM4 is becoming more practical, many designs still choose the NRZ approach. This paper presents a customisable dual-mode PAM4/NRZ transmitter IP (with 4/2-tap channel equalisation) deployable in multiple CMOS technologies. IP has been fabricated in 65nm (28Gbps/14Gbps), 180nm (10Gbps/5Gbps) technologies. A radiation-hardened 65nm (20Gbps/10Gbps) flavour is in active...
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Holger Flemming (GSI Helmholtzzentrum für Schwerionenforschung GmbH)21/09/2021, 17:20
A set of highly integrated read out ASICs with a common digitising and data aquisition back end but different front ends is currently under development at the GSI electronics department. The concept consists in using an analogue transient recorder stage for an efficient application of the area and power consuming analogue to digital converter. A focus of these ASICs is the read out of...
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Luigi Calligaris (UNESP - Universidade Estadual Paulista (BR))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
We present the development of an Intelligent Platform Management Controller mezzanine in a Mini DIMM form factor for use in electronic boards compliant to the Advanced Telecommunication Computing Architecture standard. The module is based on an STMicroelectronics STM32H745 microcontroller running the OpenIPMC open-source software, and its design has been published under open-source hardware...
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Adeel Syed Ali Shah (UNIMIB)21/09/2021, 17:20
Front-End-Electronics are utilized by ATLAS muon chamber (MDT) to detect charge and give information regarding charge arrival time and amount of charge being detected. Read-Out-Electronics along with being robust, should operate faster, be area and power efficient. This paper presents improved version of AFE, ASD designed in 130nm technology, that is actually used for MDT chambers of ATLAS...
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Tianxing Wang (University of Science and Technology of China)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The data acquisition system is a vital component in the high-energy physics experiment. To reduce duplication of work during development, D-Matrix, a generic platform, has been developed as a unified software/hardware streaming DAQ system and will be used in CSR External-target Experiments in HIRFL-CSR. Its philosophy is to abstract different tasks in the stream processing and encapsulate them...
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Pavel Ivanov (NRNU MEPhI), Dmitry Normanov (NRNU MEPHI)21/09/2021, 17:20
This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 MHz to 50 MHz and generates an output signal ranging from 400 MHz to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28nm CMOS technology of TSMC. The...
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Guilherme Tomio Saito (Universidade de Sao Paulo (BR))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
We describe a modular data acquisition system developed as the foundation of a cosmic ray detector network. Each detector setup is composed of an independent hardware device that can be controlled and read out through the Internet. This device is designed to acquire and process the signal of up to eight different detector planes. Each of these detector planes uses plastic scintillator slabs...
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Rui Gao (University of Oxford (GB))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The TORCH detector provides low-momentum particle identification, combining Time of Flight (TOF) and Cherenkov techniques to achieve charged particle pi/K/p separation between 2-20 GeV/c over a flight distance of 10m. The measurement requires a timing resolution of 70ps for single Cherenkov photons. For precision photon detection, customised Micro-Channel Plate Photomultiplier Tubes (MCP-PMTs)...
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Datao Gong (Southern Methodist University (US))21/09/2021, 17:20
We present the test results of the ETROC PLL prototype chip. This chip is based on the latest version of ljCDR from the lpGBT project and is designed to test ljCDR in its PLL mode as the clock generator for the CMS Endcap Timing Layer readout chip (ETROC). An automatic frequency calibration (AFC) block with the data protector is implemented for LC-VCO calibration. Triple Modular Redundancy...
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Ms Gabriela Cabrera Castellano (CERN), Mr Robert Grimmer (CERN), Mr Peter Haynes (CERN)21/09/2021, 17:20
The power converters at CERN deliver a broad range of complex functionalities to assure the correct magnetic field throughout the beam acceleration cycle. The power converter controls are composed of remotely programmable electronics, however such flexibility is also vulnerable to regression that requires thorough testing. Further, testing requires a significant investment in infrastructure to...
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Florent Bernon (Aix Marseille Universite (FR))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
Liquid argon (LAr) sampling calorimeters are employed by ATLAS for all electromagnetic calorimetry in the pseudo-rapidity region |η| < 3.2, and for hadronic and forward calorimetry in the region from |η| = 1.5 to |η| = 4.9. Phase-I detector upgrades began after the end of ATLAS Run-2. New trigger readout electronics of the LAr Calorimeter have been developed. Installation began at the start...
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Dmitry Eliseev (Rheinisch Westfaelische Tech. Hoch. (DE))21/09/2021, 17:20
In recent years, some minor issues were observed during operation of CMS Muon specific TM7 blade-boards, which are data concentrators for the hit-data from Drift-Tube chambers. These blade-boards reside in the uTCA crates in the service cavern of CMS. Talk presents a recently developed test-board, which is used as an inexpensive substitution of TM7. The developed test-board implements a Module...
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Oliver Kortner (Max-Planck-Institut fur Physik (DE))21/09/2021, 17:20
The front-end electronics of the ATLAS muon drift-tube chambers will be upgraded in the experiment's phase-II upgrade to comply with the new trigger and read-out scheme at the HL-LHC. A new amplifier shaper discriminator chip was developed in 130 nm Global Foundries technology for this upgrade. A preproduction of 7500 chips was launched in 2019 and tested in 2020. The functionality of the...
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Sebastien Viret (Centre National de la Recherche Scientifique (FR))21/09/2021, 17:20
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. A first prototype, CIC1, was tested successfully in early 2019 and was...
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Barbara Alvarez Gonzalez (Universidad de Oviedo (ES))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
To tolerate the High Luminosity LHC (HL-LHC) data taking conditions on the detector electronics of the CMS Drift Tubes (DT) chambers need to be replaced during Long Shutdown 3. The first prototype of the HL-LHC electronics for the On detector Board for the DT chambers (OBDT) have been installed in CMS connected to the DT chambers of one out of sixty sectors and integrated in the central data...
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Romain GAIOR (LPNHE)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
We present the status of the DAMIC-M (Dark Matter In CCD at Modane) electronics and acquisition system. This first version controls a skipper CCD and measure the pixel charge with a single electron resolution. It was designed to allow optimization with respect to clocking and readout parameters to achieve the best tradeoff between noise and readout speed. We present the implementation of the...
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Mr Daniel Blasco Serrano (CERN)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
A novel DCS front-end interface for slow control, composed of two devices, the Embedded Monitoring and Control Interface (EMCI) and the Embedded Monitoring Processor (EMP), is presented. The EMCI, based on the lpGBT and the VTRx+, is placed in a radiation hard environment and is connected to multiple front-ends via eLinks. Up to 12 different EMCIs can transmit data via optical fibre to a...
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Maria Robles Manzano (Johannes Gutenberg Universitaet Mainz (DE))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The High Granularity Timing Detector for the ATLAS upgrade is under construction to meet the challenges of the HL-LHC. The silicon detectors along with the electronics are installed in two double-sided disks per end-cap and consist of basic units (called modules) connected to the peripheral electronics by Flexible Printed Circuit cables. The reduced space between disks and the positioning...
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Daniel Gomez de Gracia (ULB)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
In the scope of the Jiangmen Underground Neutrino Observatory (JUNO) project, 6 back-end card (BEC) mezzanines connected to one BEC base board are in charge of compensating the attenuated incoming data from 48 front-end channels over 48 100-meters-long ethernet cables. Each of the mezzanines has 16 equalizers that may be subject to overheating. It is important to monitor their temperature in...
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Ms Li Zhang (Southern Methodist University and Central China Normal University)21/09/2021, 17:20
Abstract: GBS20 is a transmitter ASIC for particle physics experiments. Two serializers each at 5.12 or 10.24 Gbps share a 5.12 GHz PLL clock. The serializers’ output is combined to a PAM4 signal that drives a VCSEL. The input data channels, each at 1.28 Gbps, is scrambled by a PRBS7 that is also the internal test pattern generator. Preliminary tests indicate that the prototype works at 10.24...
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Dr Caleb James Smith (The University of Kansas (US))21/09/2021, 17:20
The CMS collaboration is building a new inner tracking pixel detector for the High-Luminosity LHC. Each pixel chip will be controlled with a single serial input stream at 160 Mbps and will send out data via four CML 1.28 Gbps outputs. The modules will be connected with up to 1.6 m long low-mass electrical links to the low power gigabit transceivers (lpGBT) and versatile transceivers (VTRx+)...
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Gabriel Saffier-Ewing21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
Low-Gain Avalanche Detectors (LGADs) are thin silicon detectors with moderate internal signal amplification yielding excellent time resolution of close to 10’s ps. AC-LGADs (aka Resistive Silicon Detectors RSD) have un-segmented gain layer and N-layer, and a di-electric layer separating the metal readout pads, guaranteeing a 100% fill-factor. The high spatial precision of few 10‘s µm is...
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Dr Alexander Klujev (Deutsches Elektronen-Synchrotron)21/09/2021, 17:20
The European XFEL facility delivers bunches of high brilliance pulses with a unique time structure, which requires a specially designed photon detectors for taking and recording the high quality scientific data. The Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector developed to cope with crucial requirements like 4.5 MHz frame rate and a dynamic range of...
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Simone Cammarata (Università di Pisa & INFN Pisa (IT))21/09/2021, 17:20
Custom silicon photonics intensity modulators for data readout in particle detectors will be presented together with preliminary experimental results. A variety of devices has been designed to explore the technological requirements to achieve data rate up to 25 Gb/s while sustaining extremely high dose levels (1 Grad total ionizing dose). Packaging constraints have been carefully considered to...
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Mr Abderrahmane GHIMOUZ (Univ. Grenoble Alpes, Grenoble INP, CNRS, LPSC-IN2P3), Mr Fatah Ellah Rarbi (Univ. Grenoble Alpes, CNRS, LPSC-IN2P3, Grenoble INP), Fatah Ellah Rarbi (Centre National de la Recherche Scientifique (FR))21/09/2021, 17:20
This paper describes the design and testing results of an 8 channels preamplifier-discriminator circuit based on a resistive feedback Transimpedance Amplifier architecture and a Leading-Edge Discriminator stage for fast high-accuracy time measurement systems. The circuit has been designed in a 130 nm CMOS technology. It is intended to be used as a Front-End-Electronics for measuring the Time...
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Michal Kruszewski (Warsaw University of Technology)21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
Although software and firmware co-simulation is gaining popularity, it is still not widely used in the FPGA designs.
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This work presents easy and structured approach for software and firmware co-simulation for bus centric designs.
The proposed approach is very modular and software language agnostic.
The only requirement is that the firmware design is accessible via some kind of bus.
The concept... -
Stephen Butalla (Florida Institute of Technology (US))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
With the projected five-fold increase in instantaneous luminosity resulting from the High Luminosity upgrade of the Large Hadron Collider, the CMS experiment is in the process of upgrading its muon spectrometer. Two triple-GEM detector systems—the GE2/1, which is currently in the early mass-production phase, and the ME0, currently in the prototyping phase—are undergoing frontend electronics...
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Dominik Górni (Brookhaven National Laboratory)21/09/2021, 17:20
A new data driven readout architecture for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz’ arbiters thanks to which there is no imposed prioritization and protection against glitches during readout is provided. The system allows not only reading the pixel activity, but also retrieving additional data, both analog and...
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Samuel Powell (University of Liverpool (GB))21/09/2021, 17:20
The CERN-RD50 collaboration aims to develop and study High Voltage-CMOS (HV-CMOS) sensors for use in very high luminosity colliders. Measurements will be presented for the RD50-MPW2 chip, a prototype HV-CMOS pixel detector with an active matrix of 8 x 8 pixels. The active matrix is tested with injection pulses, a radioactive source and a proton beam. This talk will cover the FPGA based DAQ...
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Sergio Gomez Fernandez (University of Barcelona (ES))21/09/2021, 17:20
This work presents the 8-channel FastIC ASIC developed in CMOS 65nm technology suitable for the readout of positive and negative polarity sensors in High Energy Physics experiments, Cherenkov detectors and Time-of-Flight systems. The front-end can be configured to perform analog summation of up to 4 single-ended channels before discrimination in view of exploiting area segmentation. The...
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Stavros Mallios (CERN)21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
During the High-Luminosity phase of the LHC, the CMS endcap calorimeter will be replaced by the High-Granularity Calorimeter (HGCAL). A first firmware for the back-end DAQ system of the CMS Phase-2 upgrade HGCAL was implemented in the Serenity ATCA hardware. The system is responsible not only for the readout of the detector but also for its slow control and timing. To facilitate system...
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Federico Fary (University of Milano-Bicocca)21/09/2021, 17:20
This work introduces design and simulation validation, of a monolithic setup, based on a current amplifier, for accurate gate current measurement in NMOS devices integrated in 28nm technology. The Devices-Under-Test (DUTs) include transistors with gate width between 60μm and 300μm and length between 400nm and 1μm. Current in the DUT is amplified by a 100x factor, with an accuracy above 90%....
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Weigang Yin (Brookhaven National Laboratory (US))21/09/2021, 17:20
In the ATLAS Phase-II upgrade, Global Trigger is a new subsystem that will bring event filter-like capability to the Level-0 trigger system. A common hardware platform in ATCA form factor named Global Common Module (GCM) is proposed to be configured as nodes in the Global Trigger. To mitigate the risk and simplify the GCM hardware design, a Generic Rear Transition Module (GRM) is developed....
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Kosmas Adamidis (University of Ioannina (GR))21/09/2021, 17:20
The Phase-2 CMS Level-1 Trigger and associated upstream systems consist of more than 20,000 25Gb/s optical links, transferring almost a Pb/s synchronously between different back-end processing nodes. The stable operation of these links is essential to avoid the injection of an erroneous signals into the trigger path, potentially leading to a flood of false triggers.
The Hermes protocol,...
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Krister Leonart Haugen (Norwegian University of Science and Technology (NTNU) (NO))21/09/2021, 17:20
The lower conduction power losses and the positive temperature coefficient that favours parallel connections, make Silicon Carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) to be an excellent replacement of existing Silicon insulated gate bipolar transistors (IGBTs) technology. These characteristics combined with high switching frequency operation, enables the design...
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Vlad-Mihai Placinta (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO))21/09/2021, 17:20
This work outlines the measurements done to evaluate the second SPACIROC generation in ionizing radiation environments, i.e., particle beams: ions, protons, and X-rays. The SPACIROCs are front-end ASICs designed for the readout requirements of photomultiplier technologies like: SiPMs, MaPMTs. Several radiation-induced effects were observed but they proved to be benign application-wise. The...
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Mr Aamir Irshad (Universite Libre de Bruxelles (BE))21/09/2021, 17:20
VFAT3 is the 128-channel charge-sensitive front-end chip explicitly designed for the CMS GEM phase-2 upgrades. LHC is undergoing major upgrades for HL-LHC where the particle rate is expected to increase up to 5 times. It is therefore necessary to monitor the evolution of the VFAT3 response due to aging in the radiation environment by total ionizing dose (TID) tests. The device operation could...
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Mr Liangliang Han (Nanjing University (CN))21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
The CERN developed radiation-tolerant data transmission chip lpGBT will be used on the peripheral electronics board (PEB) of High Granularity Timing Detector (HGTD) in ATLAS. In order to configure the lpGBT on the PEB, we designed a dedicated isolated USB programmer. Compared with the 2 existing lpGBT configuration toolkits, piGBT and CERN USB-I2C dongle, the programmer has very good...
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Peter Wieczorek (GSI Darmstadt, Germany)21/09/2021, 17:20
The ASIC design group at GSI developed an Amplifier With Adaptive Gain Setting (AWAGS) chip. The input stage based on a folded cascode architecture followed by a single-ended to differential conversion and output buffers. In difference to usual designs the capacitive feedback is divided in five capacitances with different values. Starting with the smallest one the capacitances were adaptively...
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Nemer Chiedde (Centre National de la Recherche Scientifique (FR))21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
Within the Phase-II upgrade of the LHC, the readout electronics of the ATLAS LAr Calorimeters is prepared for high luminosity operation expecting a pile-up of up to 200 simultaneous pp interactions. Real-time processing of digitized pulses sampled at 40 MHz is thus performed using FPGAs.
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To cope with the signal pile-up, new machine learning approaches are explored that outperform the optimal... -
Hui Zhang (Karlsruhe Institute of Technology (KIT))21/09/2021, 17:20
A monolithic pixel sensor named HVMAPS25 has been implemented in a 180nm HVCMOS technology. The pixel size is 25µm x 35µm. The pixel electronics contains a fast and low power charge sensitive amplifier, comparator, threshold tune DAC and a digital circuit that measure the arrival time of the hit with 10 bit resolution, <10ns bin width, and the amplitude (ToT) with 6 bit resolution.
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The sensor... -
Zijun Xu (SLAC National Accelerator Laboratory (US))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The RCE (Reconfigurable Cluster Element) platform is a general-purpose system-on-chip data acquisition system, which is broadly deployed in various experiments, including ATLAS. A new generation of bench-top RCE system, based on Xilinx UltraScale+ MPSoC, is developed to support the Rd53a/b module and system testing with high performance. The RCE system also serves as the primary platform for...
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Hugo Hernandez Herrera (Federal University of Minas Gerais)21/09/2021, 17:20
We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 4fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to...
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Francesco Costanza (Centre National de la Recherche Scientifique (FR))21/09/2021, 17:20
PANDORE is the environmental box that is going to be used for the quality control (QC) of loaded local supports of the ATLAS ITk Pixel Outer Barrel (OB) at LAPP. First PANDORE, its interlock system, diphasic CO2 cooling station, and data acquisition system are described. Subsequently, the results of the qualification tests are shown. Given the complexity of the OB system, several other loading...
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Karol Krizka (Lawrence Berkeley National Lab. (US))21/09/2021, 17:20
The Inner Tracker silicon strip detector (ITk Strips) is a part of the ATLAS upgrade for the HL-LHC. It employs a parallel powering scheme for the high voltage sensor bias and the low voltage to power readout ASIC’s. This design requires on-module DCDC conversion and high voltage switching. These are implemented on the Powerboard using a buck converter (bPOL12V) to drop the low voltage, a...
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Andres Guillermo Delannoy Sotomayor (University of Tennessee (US))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The Pixel Luminosity Telescope (PLT) is a silicon pixel detector dedicated to luminosity measurement at the CMS experiment. It is arranged into 16 "telescopes" of three planes each, with eight telescopes arranged around the beam pipe at either end of the CMS detector, outside the pixel endcap. In the talk, the commissioning, calibration, operational history, and performance of the detector...
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Matteo Turisini (Sapienza Universita e INFN, Roma I (IT))21/09/2021, 17:20
In 2021 the NA62 experiment at CERN is restarting data taking with upgraded instrumentation. In this framework we present the commissioning test of the new L0 trigger processor offering enhanced bandwidth, updated interconnection technology and increased logic capabilities with respect to its predecessor. We also present the latest performances of two computing-intense additional components...
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Elia Arturo Vallicelli (University of Milano Bicocca)21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
Proton-Sound-Detectors (ProSDs) sense (at <1 ms latency) the thermoacoustic signal generated by the fast energy deposition at the Bragg peak of proton beams penetrating energy absorbers.
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ProSDs are especially promising for experimental monitoring of high pulse rate (FLASH) hadron therapy treatments working in-sync with the beam.
This paper presents a mixed-signal detector capable of sensing... -
Dr Wojciech Zabolotny (Institute of Electronic Systems, Warsaw University of Technology)21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
Modern DAQ systems typically use the FPGA-based PCIe cards to concentrate and deliver the data to a computer used as an entry node of the data processing network.
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This paper presents a QEMU-based methodology for the co-development of the FPGA-based hardware part, the Linux kernel driver, and the data receiving application. That approach enables quick verification of the FPGA firmware... -
Ms Hanhan Sun (Southern Methodist University)21/09/2021, 17:20
The Quad Transimpedance and limiting Amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode to look for the optimal coupling. A charge pump...
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Mr Andrew Young (SLAC National Accelerator Laboratory (US))21/09/2021, 17:20
Abstract
The high radiation dose and the cold environment at the HL-LHC pixel detector regions presents serious challenges for the survival of optical components. Radiation hard twinax cables are developed for the ATLAS ITk pixel data transmission within the pixel detector volume for up to 6m before transitioning to optical links at larger radius where radiation dose is reduced to...
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Maria Mironova (University of Oxford (GB))21/09/2021, 17:20
The ITkPixV1 chip is the pre-production pixel readout chip for the Phase-2 Upgrade of the ATLAS experiment at the HL-LHC. The harsh environment of HL-LHC, including a peak luminosity of 5x10^34cm-2s-1 and an estimated total ionising dose (TID) of more than 500 Mrad throughout its lifetime is placing strong requirements on the radiation tolerance of the chip. This contribution outlines...
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Eduardo Valdes Santurio (Stockholm University (SE))21/09/2021, 17:20
The upgrade of the ATLAS TileCal for the HL-LHC uses a Daughterboard that serves as a hub interfacing the on-detector with the off-detector electronics. The Daughterboard design features ProASIC FPGAs, Kintex Ultrascale FPGAs and CERN GBTx ASICs. The design minimizes single points of failure and radiation damage by employing a double-redundant scheme, using TMR and Xilinx SEM strategies,...
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Dr Waqar Ahmed (University of Houston)21/09/2021, 17:20
The design and development of a High Voltage distribution system (HVDS), Smart Switch (SS) which acts as a Demultiplexer, to distribute one high voltage(HV) input into six High Voltage output channels. It provides, and independently voltage and current monitors. Each output channel of the SS has independent, ON-OFF, current and HV monitoring, as well as filtration, isolation, and a...
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Dr Wojciech Zabolotny (Institute of Electronic Systems, Warsaw University of Technology)21/09/2021, 17:20
The SMX chip is a front-end ASIC dedicated for the readout of STS and MUCH detectors in the CBM experiment.
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The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure the quality.
The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard.
In the standalone... -
Mr Markus Gruber (University of Bonn (DE))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
Based on Timepix3 several detector types can be built by combining it with a sensor or a photolithographically postprocessed gas amplification stage. With these combinations applications like beam telescopes and gas-based X-ray detectors can be realized.
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The detectors can range from single- to multichip and from low- to high-rate applications, thus a modular and scalable system is needed. It... -
Bruno Sanches (EPUSP)21/09/2021, 17:20
This work analyses seven different alternatives to implement an ADC based on the successive approximation register (SAR) architecture. The influence of the encoding is taken into account while evaluating the importance of its reset approach. Different protection strategies against single event upsets are addressed, including the comparison of per module and per cell triplication. All versions...
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Mykyta Haranko (CERN)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The CMS BRIL project upgrades its instrumentation for the Phase-2 detector to provide high-precision luminosity and beam-induced background measurements. A part of the CMS Inner Tracker - the Tracker Endcap Pixel Detector (TEPX) - will allocate a fraction of the read-out bandwidth for luminometry. In the talk, the advantages and implications of the proposed approach are highlighted. A...
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Iacopo Longarini (Sapienza Universita e INFN, Roma I (IT))21/09/2021, 17:20
The ATLAS Muon System will be upgraded for the High-Luminosity phase of LHC. Its new on-detector electronics should withstand a non-ionizing dose equivalent to 10^13 n/cm2 (1 MeV eq on Si) and have a negligible rate of single-event effects. Commercial low-dropout (LDO) voltage regulators have been considered as a practical solution for powering on-detector electronics. We present results from...
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Alex Kluge (CERN)21/09/2021, 17:20Poster
Test poster description
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Alexander Josef Pauls (RWTH Aachen University (DE))21/09/2021, 17:20
In the context of the second phase of the CMS Outer Tracker upgrade two complementary systems for the testing of the service hybrids for two-sided silicon strip modules are presented. To enable prototype testing and long term active thermal cycling during series production a dedicated test board for stand-alone operation has been produced. In addition, a test card compatible with a production...
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Saeed Taghavirad (Science and Technology Facilities Council STFC (GB))21/09/2021, 17:20
In Run 3, the ATLAS Level-1 Calorimeter Trigger (L1Calo) will be augmented by an Electron Feature Extractor (eFEX), which will identify isolated electron/photon and tau particles. Each eFEX module accommodates 424 signals at 11.2 Gb/s. Three generations of eFEX have been manufactured, and the design, manufacturing, and testing processes have been optimised. The firmware for the eFEX is managed...
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Eric Buschmann (CERN)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
Caribou is a flexible open-source DAQ system designed for laboratory and high-
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rate beam tests and easy integration of new silicon-pixel detector prototypes. It
uses common hardware, firmware and software components that can be shared
across different projects, thereby reducing the development effort and cost for
such readout systems significantly. -
Shiming Yuan (University of Bergen (NO))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The ALICE detector is undergoing an upgrade for Run 3 at the LHC. A new Inner Tracking System is part of this upgrade. The upgraded ALICE ITS features the ALPIDE, a Monolithic Active Pixel Sensor. Due to IC fabrication variations and radiation damages, the threshold values for the ALPIDE chips in ITS need to be measured and adjusted periodically to ensure the quality of data-taking. The...
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117. The Fast Beam Condition Monitor as a standalone luminometer of the CMS experiment at the HL-LHCMohammad Sedghi (Isfahan University of Technology (IR))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
In the Phase-2 CMS upgrade, a luminosity uncertainty of 1% is targeted. To achieve this goal, measurements from multiple luminometers with orthogonal systematics are required. A standalone luminometer, the Fast Beam Condition Monitor (FBCM) is being designed for online bunch-by-bunch luminosity measurement. Its fast timing properties also enable the measurement of beam induced background. In...
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Holger Flemming (GSI Helmholtzzentrum für Schwerionenforschung GmbH)21/09/2021, 17:20
A front end and trigger circuit was developed at GSI which is foreseen to be used in a transient recording read out ASIC. It consists of an input buffer with configurable low pass characteristics and a trigger which could be operated as leading edge discriminator as well as switched capacitor trigger which is sensitive to the first derivative of the input signal. The front end was produced on...
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Guillermo Loustau De Linares (University of Massachusetts (US))21/09/2021, 17:20
The novel MDT Trigger Processor (MDTTP) is a fundamental component of the ATLAS Level-0 Muon trigger upgrade, designed to meet High-Luminosity LHC requirements. The MDTTP will use MDT hits to improve the momentum resolution of muon candidates provided by RPC and TGC detectors and to reduce the fake rate.
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A hardware demonstrator has been developed based on the Apollo ATCA platform.
The... -
Dr Keida Kanxheri (INFN - National Institute for Nuclear Physics)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
The FOOT (FragmentatiOn Of Target) multi-detector experiment aims at improving the accuracy of oncological hadrontherapy for tumor treatment. It studies the nuclear fragmentation due to the interactions of charged particle beams with patient tissues. Among the several FOOT detectors, the silicon Microstrip Detector is part of the charged-ions-tracking magnetic spectrometer. Here we describe...
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Roberto Ammendola (INFN e Universita Roma Tor Vergata (IT))21/09/2021, 17:20
The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay $K^+\rightarrow\pi^+\nu\bar{\nu}$. The calorimeter level 0 trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 trigger processor, readout data is collected to be sent to L1 software trigger level. We present the novel...
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Elena Pedreschi (Universita & INFN Pisa (IT))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
This paper describes design and performance of the new Digitizer ReAdout Controller of the Mu2e electromagnetic calorimeter, which consists of two 674 CsI crystal annular matrices readout by SiPMs. The 20-channel board performs a 200 MHz sampling of the SiPM signals transmitted by the front-end electronics. The operation in the Mu2e harsh environment, with an expected total ionizing dose of...
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Tigran Mkrtchyan (Ruprecht Karls Universitaet Heidelberg (DE))21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
In order to meet the requirements for the High Luminosity-Large Hadron Collider (HL-LHC), a completely new architecture will be used to redesign the readout electronics of the ATLAS Tile Calorimeter (TileCal) system for the ATLAS Phase-II Upgrade. In the new Trigger and Data AcQuisition (TDAQ) architecture, the output signals of the Tile detector cells will be digitized in the front-end...
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Daniel Hernandez Montesinos (GBTx - BE Group)21/09/2021, 17:20
The Versatile Link Plus Demonstrator Board (VLDB+) is a board designed by CERN’s EP-ESE group to provide an evaluation kit for the new Versatile Link ecosystem (VL+). This reference design gathers three custom and radiation hard devices, namely, the Low-Power Gigabit Transceiver (lpGBT), the Versatile Link Plus Transceiver (VTRx+) and the FEASTMP DCDCs. These components are common to some of...
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Lukas Krystofiak (Juelich Research Centre), Florian Rössing (Forschungszentrum Jülich GmbH (FZJ))21/09/2021, 17:20
Chip design, is a lengthy process, which comes with high development efforts and costs and is a crucial milestone for the overall success of the project. Readout electronics for particle detectors resemble each other to a high degree, thus developing a software-adaptable receiver chain covering a large range of application scenarios is an attractive concept. With a generic approach, designed...
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Panagiotis Gkountoumis (CERN)21/09/2021, 17:20
The low radiation levels on the outer rim of the New Small Wheels of the the ATLAS experiment gave the opportunity of utilizing commercial FPGAs for the trigger electronics of the sTGC detectors. The demanding requirements of the Xilinx FPGA transceivers in terms of jitter imposed the development of an ultra-low jitter clock distribution scheme. This scheme includes a custom board placed in...
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Agostinho Da Silva Gomes (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)21/09/2021, 17:20
The high voltage (HV) system of TileCal, the ATLAS central hadron calorimeter, is being upgraded for the HL-LHC, in the so called Phase II Upgrade. In the new configuration for the upgrade, the HV regulation boards are not located inside the detector anymore, they are deployed far from the radiation in a room where there is permanent access for maintenance. This option requires a large number...
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Mr Leonid Epshteyn (Budker Institute of Nuclear Physics)21/09/2021, 17:20
In 2017, the luminosity at the VEPP-2000 collider at the Budker Institute of Nuclear Physics SB RAS, Novosibirsk, has increased. In this regard, it was decided to upgrade the trigger system of the CMD-3 detector. For this, the development of a device called the “Final Decision Block” was started. In this paper, we consider the designing and debugging process of the created block, as well as...
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Mr Adithya Pulli (CERN)21/09/2021, 17:20
The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification...
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Ricardo Luz (Argonne National Laboratory (US))21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
The FrontEnd LInk eXchange (FELIX) is an FPGA-based data router designed to interface custom detector readout systems, and commodity switched networks as part of the ongoing upgrade of the ATLAS experiment at CERN. FELIX relies on synchronous data aggregation with GBT and lpGBT protocols to control and readout multiple detector front-ends. To facilitate validation and benchmarking, we designed...
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Lioubov Jokhovets (Forschungszentrum Jülich GmbH)21/09/2021, 17:20Programmable Logic, Design Tools and MethodsPoster
A high density data acquisition system integrating over 2000 channels inside of a single OpenVPX crate is intended to be used in different applications e.g. gaseous or scintillator-based particle detectors. 14 payload slots, controller and data concentrator communicate one with other via multi-gigabit backplane. Each payload slot consists of a front module for digital and a rear transition...
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Torben Mehner (KIT - Karlsruhe Institute of Technology (DE)), Luis Ardila (KIT-IPE)21/09/2021, 17:20Systems, Planning, Installation, Commissioning and Running ExperiencePoster
In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family ATCA blades.
In this talk, we present the current revision of both Serenity baseboards and the developments on the MPSoC...
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Gianmario Bergamin (CERN)22/09/2021, 11:40
The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that...
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Dominik Koukola (CERN)22/09/2021, 12:00
Following the RD53A demonstrator, the ItkPix (ATLAS) and CROC (CMS) pixel readout chips are being developed within the RD53 collaboration for the HL-LHC pixel detector upgrades of the two experiments. The two chips are based on a common design, called RD53B, in 65nm CMOS technology and are optimized for very high rate (3GHz/cm2) and radiation levels (>500Mrad). The ATLAS pre-production chip...
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Attiq Ur Rehman (University of Bergen (NO))22/09/2021, 12:20
The RD53B pixel readout chip has been submitted for fabrication, meeting specifications of the ATLAS and the CMS experiments for HL-LHC upgrades. Performance characterization of a readout chip in terms of link data rate, average readout latency and efficiency of hit data is essential to evaluate operation of pixel sensors at an extreme interaction rate. At the same time it is complex due to...
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Mr Frederic Dulucq (OMEGA - Ecole Polytechnique - CNRS/IN2P3)22/09/2021, 12:40
For the CMS HGCAL, the final version of the 72-channel front-end ASIC (HGCROC3) was submitted in December 2020. HGCROC3 includes low-noise/high-gain preamplifier/shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge measurement over the linear range of the preamplifier. In the saturation range a discriminator and TDC provide the charge information from TOT (200ns dynamic range, 50ps...
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Thomas Zimmerman (Fermi National Accelerator Lab. (US))22/09/2021, 14:00
Silicon detectors with excellent time resolution will play a critical role in future collider experiments, providing a new tool in event reconstruction. The Low Gain Avalanche Detectors (LGAD) have been demonstrated to provide the required time resolution and radiation tolerance. We will present the FCFD0 ASIC developed to read out LGAD signals. The FCFD0 utilizes Constant Fraction...
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Dr Roma BUGIEL (IPHC)22/09/2021, 14:20
The Micro-Vertex Detector of the CBM experiment at FAIR/GSI requires very light detector stations equipped with highly granular and thin pixel sensors adapted to hostile running conditions. A specific CMOS pixel sensor, called MIMOSIS, is being developed for this purpose. Inspired by the ALPIDE sensor equipping the ALICE ITS, its design is adapted to higher hit rate and radiation tolerance....
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Lorenzo Piccolo (INFN Torino)22/09/2021, 14:40
This work presents the first measurements on the Time SPOT1ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32×32 channels hybrid-pixel matrix. Targeted to 4D-Tracking applications in High Energy Physics experiments, the system aims to achieve a timing resolution of 30 ps or better at a maximum event rate of 3 MHz/channel with a Data Driven...
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Alejandro David Martinez Rojas (INFN - National Institute for Nuclear Physics), Marco Ferrero (Universita e INFN Torino (IT))22/09/2021, 15:00
We present the first results obtained with the FAST2 family of ASICs. The FAST2 ASIC family, designed in the 110 nm CMOS technology, has been optimized for the read-out of Ultra-Fast Silicon Detectors, aiming to achieve a combined total time resolution of less than 40 ps. In the FAST2 family, the ASIC (FAST2_A) presents 16 channels and has only the amplification stage with a timing jitter...
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Sarath Kundumattathil Mohanan (Bergische Universitaet Wuppertal (DE))22/09/2021, 15:40
The front-end electronics of Ionization chamber for radiation protection demands challenging sensitivity requirements in the femtoampere range and a wide dynamic range. This work details the development trajectory that culminated in a single chip solution with current measurement capability spanning nine decades. The various Application Specific Integrated Circuits designed in the Radiation...
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Gianni Mazza (Universita e INFN Torino (IT))22/09/2021, 16:00
The readout electronics for the CMS Electromagnetic Calorimeter is
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undergoing a re-design in order to cope with the LHC ugrade.
In particular, a fourfold increase in the sampling frequency
(from 40 to 160 MS/s) is required. Therefore a new readout ASIC
has been developed.
The ASIC, named LiTE-DTU, is designed in a CMOS 65 nm technology.
The LiTE-DTU embeds two 12 bits, 160 MS/s ADCs, a... -
Tiehui Ted Liu (Fermi National Accelerator Lab. (US))22/09/2021, 16:20
The Endcap Timing Readout Chip (ETROC) is being developed for the CMS MTD Endcap Timing Layer (ETL) for the HL-LHC, to process LGAD signals with time resolution down to 30ps per track. The ETROC1 is the first full chain precision timing prototype, including preamplifier and discriminator, as well as a new low power TDC design that performs time-of-arrival (TOA) and time-over-threshold (TOT)...
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Prof. Yahya Tousi (The University of Minnesota)22/09/2021, 16:40
The use of precision timing measurements will be a major tool at the HL-LHC, where it will be used to suppress pile-up and to search for long-lived particles. To control a reference clock with sub-picosecond accuracy, we have fabricated in the TSMC 65nm process a digitally controlled phase shifter. It is composed of a chain of 66 cells, each with a digitally controlled planar wave guide with...
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Tahereh Sadat Niknejad (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)23/09/2021, 11:40
TOFHIR2 is the front-end ASIC for the barrel timing layer (BTL) of the MIP timing detector for the CMS upgrade for HL-LHC, aiming at 30-60 ps resolution throughout HL-LHC lifetime. The BTL consists of LYSO:Ce crystals coupled to SiPMs which will suffer radiation damage. Relative to the first version of the front-end ASIC (TOFHIR2A), TOFHIR2X implements improved circuitry for mitigation of the...
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Jiaguo Zhang (Paul Scherrer Institut)23/09/2021, 12:00
Gotthard-II is a charge-integrating microstrip detector developed for experiments and diagnostics at free-electron lasers using hard X-rays of 5 keV–20 keV. Its potential scientific applications include X-ray absorption/emission spectroscopy, energy dispersive experiments, as well as veto signal generation for pixel detectors. The Gotthard-II ASIC has been designed in several optimization...
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Davide Cieri (Max Planck Society (DE))23/09/2021, 12:20
Handling HDL project development within large collaborations presents many challenges in terms of maintenance and versioning, due to the lack of standardized procedures. Hog (HDL on git) is a tcl-based open-source management tool, created to simplify HDL project development and management by exploiting git and Gitlab Continuous Integration (CI).
Hog is compatible with the major HDL IDEs...
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Chaowaroj Wanotayaroj (CERN)23/09/2021, 12:40
With the ever-increasing amount of data from HEP experiments, the transmission rates must keep up. To mitigate the exponential growth of the total loss due to the increased frequency, the 4-Level Pulse-amplitude Modulation (PAM-4) could be envisaged, allowing to reach 56 Gbps or even 112 Gbps in extremely high-end applications. A system using PAM-4 encoders and transceivers has been built...
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Tong Xu (Argonne National Laboratory (US))23/09/2021, 14:00
The Hough-transform-based FPGA track processing is considered for the trigger system of the ATLAS detector at the Large Hadron Collider at CERN as a part of the upgrade for the High-Luminosity program. The prototype firmware has been developed to evaluate system size. The track processing is organized as a pipeline to increase data processing and clock rates. This Hough transform accumulator...
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Jean-Baptiste Sauvan (Centre National de la Recherche Scientifique (FR))23/09/2021, 14:20
A first version of the firmware blocks of the trigger primitive generator for the CMS endcap calorimeter upgrade (HGCAL) are being implemented, in order to assess the FPGA resource requirements and dimension the system. For the development of some of these blocks, a data-driven design flow is used to automate the production of multiple firmware variants based on VHDL and HLS C/C++ templates....
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Matei Vasile (IFIN-HH (RO))23/09/2021, 14:40
The FELIX system is used as an interface between front-end electronics and commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. RDMA communication is implemented using software on both end of the links. Exploring opportunities to improve data throughput as part of...
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Dr Franco Spinella (INFN Pisa (IT)), Franco Spinella (Universita & INFN Pisa (IT))23/09/2021, 15:00
The Mu2e calorimeter and read-out electronics are hosted inside the superconducting magnet cryostat and exposed to an intense flux of ionizing and non-ionizing particles. The performance of a number of components is compromised by radiation damage. This includes the scintillating crystals and silicon photomultipliers (SiPM) whose performance degrades proportionally to both dose and neutrons...
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Jelena Lalic (CERN)23/09/2021, 15:40
The RD53B chip for HL-LHC upgrades of ATLAS and CMS needs to provide reliable operation in a radiation hostile environment with inevitable Single Event Effects. To answer the challenge, substantial efforts are made to protect and evaluate the critical parts of digital logic with different TMR schemes and to characterize the on-chip CDR. Cross-section for each TMR scheme and its effective SEE...
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Aleksandra Dimitrievska (Lawrence Berkeley National Lab. (US))23/09/2021, 16:00
To test the performance of the future pixel readout chip in the harsh High Luminosity LHC (HL-LHC) environment, an irradiation experiment has been setup with gaseous Kr-85 beta source with dose rate of about 7 rad/s. This setup was designed to emulate as closely as possible operation in the HL-LHC conditions of the ATLAS detector inner layer, including temperature, radiation, and continuous...
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Milou Van Rijnbach (University of Oslo (NO))23/09/2021, 16:20
The MALTA family of depleted monolithic Pixel sensors produced in TowerJazz 180 nm CMOS technology target radiation hard applications for the HL-LHC and beyond. Several process modifications and front-end improvements have resulted in radiation hardness up to 2e15 n/cm2 and time resolution below 2 ns, with uniform charge collection efficiency across the Pixel of size 36.4 x 36.4 um2 with a 3...
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Mr Aamir Irshad (Universite Libre de Bruxelles (BE))23/09/2021, 16:40
The CMS detector will see the replacement of its existing endcap calorimeter with a new high granularity calorimeter (HGCAL), which will need to withstand much higher radiation levels than the present endcaps. This poses tight constraints on the front-end electronics, including the powering chain. As part of this chain, a low-dropout linear regulator (LDO) has been designed and prototyped for...
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10. Integration and commissioning of the ATLAS Muon-to-Central-Trigger-Processor Interface for Run-3Sabrina Perrella (CERN)24/09/2021, 11:40
The Muon-to-Central Trigger Processor Interface (MUCTPI) was completely redesigned as part of the ATLAS Level-1 trigger upgrade for Run 3 of the LHC. The new system is implemented as a single ATCA module, using three large state-of-the-art FPGAs and high-density fibre-optic modules. 208 high‑speed links receive trigger information from the muon trigger detectors, while 60 links are used to...
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Michail Bachtis (University of California Los Angeles (US))24/09/2021, 12:00
The throughput and processing requirements of the CMS L1 Trigger for HL-LHC require platforms with high-end FPGAs and many high speed optical links. The Ocean platform features the largest ZYNQ Ultrascale+ SoC and 72 transceivers connected to on-board optics reaching rates up to 28 Gbps. The Octopus^2 design targeted for the CMS Muon Trigger at HL-LHC features a Virtex Ultrascale+ 13P FPGA in...
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Filiberto Bonini (Brookhaven National Laboratory (US))24/09/2021, 12:20
The HL-LHC will start operations in 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined. Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition system. Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The hardware implementation...
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Brent Yates (Ohio State University (US))24/09/2021, 12:40
The High-Luminosity LHC will put significant demands on trigger systems. To control trigger thresholds, the CMS Collaboration is designing a novel Level-1 track trigger. The Outer Tracker will use modules with pairs of sensor layers to read out hits compatible with charged particles above 2-3 GeV. The system will combine these front-end trigger primitives to reconstruct tracks, providing a...
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Federico Lazzari (Universita di Siena & INFN Pisa (IT))24/09/2021, 14:00
In Run-3 beginning in 2022, the LHCb software trigger will start reconstructing events at the LHC average crossing rate of 30 MHz. Within the upgraded DAQ system, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction, in view of future runs at even higher luminosities.
One such solution is a highly-parallelized custom tracking processor...
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Jinyuan Wu (Fermi National Accelerator Lab. (US))24/09/2021, 14:20
An exercise of implementing and testing a 3D track segment seeding engine core based on the Tiny Triplet Finder in a low-cost FPGA device is reported. The seeding engine is designed to preselect and group hits (stubs) from cylindrical detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hugh transform space for r-z view and a Tiny Triplet Finder for r-phi...
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Siyuan Sun (University of Michigan (US))24/09/2021, 14:40
The present ATLAS innermost endcap muon station will be replaced by a New Small Wheel (NSW) detector to handle large trigger and readout data rates expected at high luminosity LHC runs. Two new detector technologies, Resistive Micromegas (MM) and small-strip Thin Gap Chambers (sTGC), will be used for triggering and tracking. A common readout path and two separate trigger paths are developed....
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Federico De Benedetti (Università degli Studi e INFN Milano (IT))24/09/2021, 15:00
Abstract: We present a detailed description of the design, prototyping and production of the hybrid circuits for the front-end electronics of the Upstream Tracker at LHCb. The multilayer flexible circuits are design to host the front-end chips, ensure a low radiation length and withstand the harsh environment conditions of the data taking.
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James Michael Botte (Carleton University (CA))24/09/2021, 15:40
To instrument the 60 million ATLAS ITk Strips Sensor channels, CERN developed the mixed-signal ABCStar front-end readout ASIC. Over 350,000 devices on 753 wafers containing 466 ASICs each will be extensively tested to provide the chips required for sensor modules. Carleton achieved a 3-10 times improvement in throughput, without compromising test coverage or data collection, by developing new...
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Irene Mateos Dominguez (CERN)24/09/2021, 16:00
Up to fifty thousand front-end and service hybrids are required for the CMS Tracker Phase Two Upgrade. These hybrids, which are built on carbon fibre stiffened circuits and contain several flip-chip ASICs, will be glued in module structures, making repairs almost impossible. Due to their complexity, testing within production is a very important aspect. A multiplexed testing infrastructure,...
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Nour El Houda Guettouche (Centre National de la Recherche Scientifique (FR))24/09/2021, 16:20
The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC designed to implement multipurpose high-speed bidirectional serial links in HEP experiments. Having more than 320 programmable registers, the ASIC is highly configurable. Its test must cover a large variety of functionalities which will be validated at three different power-supply voltages, two temperatures and over more...
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Alex Kluge (CERN)24/09/2021, 16:40Oral
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