Neurons in the brain interact with each other through electrical and chemical signals. These interactions determine how the brain detects and processes information. Simultaneous detection of the activity of many neurons is crucial for understanding the brain function. I will describe electrical and optical methods of interacting with neural networks developed with SCIPP’s participation. I...
The Linac Coherent Light Source (LCLS) is in the midst of a major upgrade called LCLS-II [1]. This upgrade will add a 4 GeV continuous-wave superconducting electron accelerator to the LCLS complex, delivering a 10,000-fold increase in repetition rate and average x-ray brightness. Currently scheduled to achieve first light in 2020, LCLS-II will enable a broad range of experiments over a 0.2 to...
A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC. This upgrade will allow to reconstruct within a few microseconds charged particle tracks with transverse momentum above 3 GeV, for use in the Level-1 trigger. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, reconstructing tracks using an...
Being a proposed solution for the digital boards of the upgraded LHCb RICH sub-detectors, SRAM-based FPGA devices have become widely used in high energy physics experiments. These studies aim to present the radiation hardness measurements done on the KINTEX-7 FPGA during irradiation with protons, X-rays and ions beams. For multiple values of the total ionising dose, linear energy transfer and...
As part of the program for the upgrade of the ATLAS inner tracker for the High Luminosity LHC, irradiations have been carried out with 60Co gamma source. The measurements characterize the increase in the leakage current in the 130 nm-technology readout chips. The current as a function of total ionizing dose has been studied under different conditions: dose rate, temperature, power applied to...
The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at CERN will be upgraded for run 3 of the LHC. The current system, a full 9U VME crate, will be replaced by a single AdvancedTCA blade, based on state-of-the-art FPGA technology and high-density ribbon fibre-optic transmitters and receivers. The module uses a System-on-Chip (SoC) with a processor running an...
Abstract:
The RD53 collaboration was established to develop the next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS process is adopted in order to satisfy the high level of integration requirement. The SEU immunity for this highly scaled process should be carefully considered because the device...
To cope with the enhanced luminosity delivered by the Large Hadron Collider in 2021, the ATLAS experiment has planned a major upgrade. The first level trigger based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (FEXs), each optimized to trigger on different physics objects. This presentation is focused on the jet FEX.
The main...
The CBC3 is the latest version of the CMS Binary Chip for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon micro-strip sensors with aligned micro-strips. On-chip logic...
The present small wheel muon detector at ATLAS will be replaced with a New Small Wheel (NSW) detector to handle the expected rate at the increase in data rates and harsh radiation environment expected at the LHC. Resistive Micromegas and small-strip Think Gap Chambers will be used to provide both trigger and tracking primitives. A new trigger and readout system is developed for the NSW...
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL–LHC experiments. The PLL features a novel LC-oscillator...
NEBuLA is a large band autonomous digitiser under development, with use cases in radio astronomy.
We present the scientific rationale and the specifications of the project, We describe the board overall architecture,
the implementation of the different links: synchronisation, command, control and data transfer. We present
the solution adopted to fulfil the main requirement of the project...
The DAQ of the CLICpix2 readout chip is based on the Control And Readout Inner tracking BOard (CaRIBOu). CaRIBOu is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The...
ATLAS Muon-Drift-Tubes spatial resolution-&-efficiency depend on drift-time resolution, noise levels, and accurate threshold setting. A new 130nm read-out device is developed and optimized, for the required time resolution, to guarantee rise-times below 10ns, with acceptable time-slewing effects. Moreover, the large chain-amplification results in increased sensitivity to any disturbance...
The design and implementation of demonstrator front-end electronics for Micromegas detectors to be employed in the New Small Wheel, an ATLAS muon spectrometer upgrade, are presented. The demonstrator has 512 Micromegas detector channels as input. Signal processing and digitization utilize a custom ASIC developed by Brookhaven National Lab. Configuration, control and Ethernet readout...
Single Event Effects (SEEs) comprising of Single Event Upsets (SEUs) and Single Event Transients (SETs) corrupts the data in storage nodes/registers. Triple Modular redundancy (TMR) with clock delay insertion is a system level technique that counters SEEs in storage nodes. However, such an implementation is not straight forward in standard cell based digital design which uses cad tools like...
As a prototype of DUNE far detector, ProtoDUNE-SP single phase LAr TPC will sit in H4 beam line at CERN to study detector response to particles. It consists of 6 full-size APAs plus 2 CPAs, with total 15,360 TPC readout channels. The front-end readout electronics is comprised of cold electronics and warm interface electronics. The integral design concept of APA, cold electronics, feed-through,...
ALICE is preparing a major upgrade for 2021.
Subdetectors upgrading their counting room DAQ electronics will use a
common hardware to receive physics data: the Common Readout Unit (CRU).
The same CRU will also distribute the LHC clock and trigger to many of
the upgrading subdetectors (~7800 front end cards).
Requirements are strict: for the clock the allowed jitter (RMS) is
typically <300ps,...
For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low- jitter clock. Compared to the old board, the DRM2 is able to cope with...
First full size 2S module prototypes for the CMS Phase-2 Tracker Upgrade have been assembled. With two sensors with realistic geometries and 16 CBC2 readout chips on two front-end hybrids, the characteristics of these complex objects can be studied.
A microTCA based readout system was developed to test multiple front-end hybrids simultaneously. Therefore the concurrent information of the full...
Image sensor innovation continues after more than 50 years of development. New image sensor markets are being developed while old markets continue to grow. Higher performance and lower cost image sensors are enabling these new applications. Although CMOS image sensors dominate the market, CCDs and other novel image sensors continue to be developed. In this talk we discuss trends in image...
The Time of Propagation (TOP) detector is a novel Cherenkov barrel particle identification system built for the Belle II detector upgrade based on quartz radiator bars read out by Micro-Channel Plate PMTs. The readout electronics of the TOP system are built around a switched capacitor array waveform sampling ASIC operating at 2.7GSa/s. Acquired waveforms are processed in real time in...
ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and the readout electronics is 30 ps/MIP. Each analog channel of the ASIC must exhibit an extremely low jitter noise to ensure this challenging time resolution, while keeping a low power...
The LHCb Experiment will be upgraded to a trigger-less system reading out the full detector at 40
MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator
(VELO) will be a hybrid pixel detector read out by the "VeloPix" ASIC with on-chip zero-suppression.
This talk will present the systems overview and design of the VELO on-detector electronics...
The design and measurement results of a waveform digitizer based on the Switched Capacitor Array (SCA) architecture, fabricated in CMOS 180 nm technology, are presented. The prototype ASIC containing two channels inside is fully functional at a sampling rate of 2 Gsps with an analogue -3 dB bandwidth of more than 400 MHz. Each channel integrates 128 sampling cells and a ramp-compare ADC. With...
The High-Luminosity LHC (HL-LHC) is planned to start the operation in 2026 with an instantaneous luminosity of 7.5 x 1034 cm-2s-1. To cope with the event rate higher than that of LHC, the trigger and readout electronics of ATLAS Thin Gap Chamber will be replaced and an advanced muon trigger with fast tracking will be implemented. A frontend board prototype was developed and the functions for...
Following the first LHC collisions seen and recorded by CMS in 2009, the DAQ hardware went through a major upgrade during LS1 (2013-2014) and new detectors have been connected during the 2016-2017 winter shutdown. Now, LS2 (2019-2020) and LS3 (2024-mid 2026) are actively prepared. This paper shows how CMS DAQ hardware has evolved from the beginning and will continue to evolve in order to meet...
The MuTRiG chip, which is dedicated to the Mu3e experiment, is a 32 channel
mixed-signal Silicon Photomultiplier readout ASIC with high timing precision
and high event rate capability designed and fabricated in UMC 180 nm CMOS
technology. It combines the excellent timing performance of the fully
differential analog front-ends and the 50 ps time binning TDCs with a high
event rate capability...
Radiation-induced degradation and soft errors in electronics are important reliability issues for various space, defense and commercial applications. The continual miniaturization of CMOS technologies and the introduction of multi-gate device structures to mitigate short channel effects have had mixed consequences for radiation tolerance. The aim of this presentation is to review the current...
Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to...
SALT is a 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It
will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial
output data. SALT is designed in CMOS 130~nm process and uses a novel architecture comprising of analogue
front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit...
During the High Luminosity LHC, to maintain a managable trigger rate and achieve its physics goals,the CMS detector will need charged particle tracking at the hardware trigger level. The tracklet approach is a track-finding algorithm based on a road-search algorithm that has been implemented on commercially available FPGA technology. This algorithm has achieved high performance in...
For the HGCAL calorimeter upgrade of CMS, two test vehicles were submitted in 2016. They provide the main building blocks of the future ASIC that will read out 50 pF Si-sensors over 10 pC dynamic range. The first test-vehicle features several variants of low-noise, dual-input-polarity current-sensitive preamplifiers. The second test vehicle has eight channels of the full analog-chain :...
We present the latest results on the prototype of a tracking processor capable of reconstructing events in a silicon-strip tracker at about 40 MHz event rate with sub-microsecond latency. The processor is based on an advanced pattern-recognition algorithm, called “artificial retina”, inspired to the vision system of the mammals. We design and implement this processor on a board equipped with...
CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 $\mu m^2$. It is fully functional, can work at low thresholds down to 250e$^-$ and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex...
We present a serial link transmitter designed for CMOS pixel sensors in a 0.18 µm CMOS Technology. The transmitter includes a digital interface block with Reed-Solomon encoder, a Phase-Locked Loop (PLL), a serializer and a Current Mode Logic (CML) driver with pre-emphasis. Functionalities of the transmitter is verified by simulation, consuming 174 mW from a 1.8 V power supply. The transmitter...
A 4-channel parallel 56 Gb/s optical receiver for VCSEL-based optical links is presented. The receiver has been manufactured in a standard 65nm-CMOS process. Simulation results with layout parasites and a model of a wire-bonded photo diode demonstrate that the single channel works at bit rate of 14 Gb/s and has an input sensitivity of better than 20 uApp, an input-referred noise of 2.3 uArms...
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground experiment based on a 20,000 ton liquid scintillator with the one main objective to determine the neutrino mass hierarchy. The signal detection is performed by photomultipliers with directly attached readout electronics. The central component for the digitization process is a receiver chip with a low power...
Large area silicon trackers with excellent time and position resolution are now considered in the upgrade programs of the ATLAS and CMS detectors.
In this contribution we present the development of a custom ASIC chip meant to be bump-bonded to segmented Ultra-Fast Silicon Detector, aiming to achieve a combined time resolution of $\sigma \sim$ 30 ps.
The ASIC is implemented in standard...
We present the design and characterization of a CMOS pixel direct charge sensor, Topmetal-IIa, fabricated in a standard 0.35$\mu$m CMOS process. The sensor features a $45\times216$ pixel array with a 40$\mu$m pixel pitch which collects and measures external charge directly through exposed metal electrodes in the topmost metal layer. Each pixel contains a low-noise charge-sensitive...
The Liquid Argon Pixel (LArPix) prototype ASIC implements 32 channels of analog front end circuitry and backend digitizers at a power consumption of less than 50 uW/channel. LArPix is envisioned as a component of a potential DUNE near detector TPC module. Demanding noise, power, and dynamic range requirements are imposed by myriad particle interaction scenarios. Widely varying track...
This paper presents a HV/HR-MAPS detector designed in the framework of the HVCMOS collaboration for the ATLAS Inner Tracker update in the HL-LHC era. It was fabricated with a 150 nm HVCMOS process which includes a layer to isolate the bulk of PMOS transistors from the collecting node of the sensor. All front-end electronics are integrated inside the pixel, which is of only 50 µm x 50 µm, and...
After having commissioned the readout electronics currently implemented in the Insertable B-Layer, Layer 1 and Layer 2 of the ATLAS Pixel Detector (B-Layer and Disk readout electronics in under commissioning), we have designed and fabricated a new readout electronic board looking at the upgrade of the LHC pixel detectors. A couple of PCI_express-based prototype boards, namely PCI-ROD featuring...
The ALICE experiment at the LHC plans an upgrade of its TPC, due to the expected high Pb-Pb collision-rate after the shutdown of LHC in 2018. In the upgraded TPC, Gas Electron Multiplier (GEM) chambers and continuous readout system will replace MWPC chambers and conventional triggered readout, respectively. In the continuous readout, GEM signals will be processed using 32 channels of SAMPA...
The digitization stage of the main electromagnetic calorimeter of the CBELSA/TAPS experiment in Bonn (Germany) is being equipped with custom 80 MSPS, 14 bit Sampling-ADCs. Onboard data processing with FPGAs allows determination of the signal characteristics, reducing the data substantially. The readout of the unprocessed sampling data allows offline analysis and refinement of the...
Large aperture MCP based UV single photon imaging detectors are commonly used in space applications. NASA granted,the development of new detector with a geometrical acceptance up to a 100x100 mm, as well as ASICs for the construction its readout system. We developed the detector and ASIC chips which enabled the construction of it's readout system. The system is composed of fast, low noise and...
The prototype Barrel module design, for the Phase II upgrade of the of the new Inner Tracker (ITk) detector at the LHC, has adopted an integrated low mass assembly featuring single-sided flexible circuits, with readout ASICs, glued to the silicon strip sensor. Further integration has been achieved by the attachment of module DCDC powering, HV sensor biasing switch and autonomous monitoring and...
The increase of luminosity foreseen for the Phase-II HL-LHC upgrades calls for new solutions to fight against the expected pile-up effects. One approach is to measure very accurately the time of arrival of the particles with a resolution of few tens of picoseconds. In addition, a spatial granularity better than a few millimeter will be needed to obtain a fake jet rejection rate acceptable for...
The silicon-strip system in the ATLAS ITk detector has individual sensor modules mounted on staves to provide integrated solution for mechanical support, power, cooling, and data transmission. The data and power are transmitted to individual modules on polyimide tapes placed on thermo-mechanical stave cores. The 1.4 m long tapes transmit module data at rates up to 640 Mbps, several multi-drop...
This work presents the design and characterization of a SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications. The prototype chip was designed and fabricated in the framework of the CHIPIX65 project and was completely characterized. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal...
We present designs and test results of two radiation-tolerant VCSEL array driver ASICs fabricated in 65 nm CMOS technology, VLAD28 and VLAD14. VLAD28 is a 4 × 28-Gbps driver, delivering 2 mA bias and 5 mA modulation currents with a power consumption of 90 mW/ch. VLAD14 is a low-power 4 × 14-Gbps driver, delivering 2 mA and 6 mA modulation with a power consumption of 44 mW/ch. The two drivers...
One of the crucial parts of the proposed low occupancy Timing Vertex Detector (TVD) is a waveform sampling ASIC denoted the RFpix. It is being developed to sample and digitize voltage pulses and enable measurements of their arrival times with a timing resolution of 100fs or less. To achieve this, the RFpix needs to have an analog bandwidth of 3GHz and a sampling speed of 20GS/s. In this paper,...
Currently there is a lot of activity in R&D for future colliders. Multiple detector prototypes are being tested, each with different requirements for data acquisition and monitoring, which has generated different ad-hoc software solutions. We present [DQM4HEP][1], a generic C++11 framework for online monitoring for particle physics experiments, and results obtained at several testbeams with...
The upgrade of the ALICE Inner Tracking System uses a newly developed Monolithic Active Pixel Sensor (ALPIDE) which will populate 7 tracking layers surrounding the interaction point. Chips communicate with the readout electronics using a 1.2 Gb/s data link and a 40 Mb/s control link. Event data are transmitted to the readout electronics over microstrips on a Flexible Printed Circuit and a 5m...
In the Large Hadron Collider (LHC), the cryogenics instrumentation infrastructure uses fuse-protected high-voltage isolated temperature transducer cards. Spurious faults were observed at their miniature silver fuses during the periods 2008-2010 and 2014-2016 and a study was launched to understand the underlying failure mechanism.
The study uses data from Scanning Electron Microscopy (SEM),...
High efficiency, radiation hard, hybrid GaN and CMOS integrated module DC-to-DC converter has been designed. The integrated, compact, low-mass, single-module DC-DC converter solution has an input voltage of 18V regulated down to an output voltage of 1.4V, with 5A maximum load current. It exhibits >80% efficiency. Discrete GaN transistors are used for the power stage, and the controller...
This paper proposes a novel 2.56 Gbps radiation hardened by design LVDS/SLVS like receiver for use in transmission systems requiring timing accuracy. The circuit, designed in a commercial 65 nm CMOS technology, uses a replica receiver with charge pump feedback. This feedback loop equalizes the propagation delay of the outputs rising and falling edge, independent of total ionizing dose (TID)...
Monolithic Active Pixel Sensors are becoming increasingly attractive for the next generation High Energy Physics experiments. For this reason several R&D are ongoing in different laboratories to improve the performance of conventional MAPS.
In this context we present a flexible readout electronics specifically developed for the detailed characterization of MAPS. The prototype ASIC has been...
The future of connectivity is wireless, and the HEP community is not an exception. The demand for high capacity data transfer continues to increase every year at a significant rate. For example the tracking detectors require readout systems with several thousand links that has to handle a data transfer of multiple-gigabit/s each. We propose to use the millimeter-wave band between (57-66 GHz)....
The CMS ECAL barrel electronics will be upgraded for the HL-LHC to meet the latency and bandwidth requirements of the Phase-II Level-1 trigger system. The front-end electronics will mitigate the increasing noise from the avalanche photodiodes (APDs), discriminate against anomalous APD signals and provide improved timing information. The foreseen solution is to replace the current...
A new inner tracking detector (ITk) for the Phase-II upgrade of the ATLAS experiment is in development. A serial power scheme is foreseen for the pixel detector. This requires a new detector control system (DCS) to monitor and control the pixel modules in the serial power chain.
The Pixel Serial Power Protection (PSPP) chip is an ASIC for this purpose. It operates parallel to the modules and...
A quad chip module hybrid—assembled with FE-I4 chips—has been fabricated to test performance in a serially powered module chain as would be used in the upgraded ATLAS pixel layer at the High Luminosity LHC. This poster present results of the development of a flex circuit board interface for the quad chip modules and system integration tests of modules installed on an I-beam. Experience from...
Radiation tolerant serial links for high-speed data transmission in High Energy Physics experiments have been developed at INFN-Pisa and UCSB in a commercial 65nm CMOS technology: 2Gbps Standard-Cell based Serializer and Deserializer and custom 3GHz SLVS Driver and Receiver. Results of test and characterization of the last version of the circuit prototypes produced in the second half of 2016...
The SSA is a silicon-strip readout ASIC for the hybrid Pixel-Strip detector of the CMS Outer Tracker High Luminosity LHC (HL-LHC) Phase II upgrade. It is a 120-channel ASIC with double-threshold binary readout architecture, utilizing a quick hit cluster finding logic to provide encoded hit information for particle momentum discrimination to the Macro Pixel ASIC (MPA) at the bunch crossing rate...
The project of the LHCb upgrade foresees a replacement of the whole acquisition system of the detector to allow a full readout at 40 MHz. The development of a new control board, called the 3CU for the electromagnetic and hadronic calorimeters was proposed. This board receives commands from the main LHCb control system and sends them through the backplane to the front-end boards. Each...
We present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel serializer ASIC for detector front-end readout. LOCx2-130 consists of two serializer channels with custom encoders and each channel operates at 4.8 Gbps. The ASIC is fabricated with a commercial 130-nm CMOS process and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a bit...
Two optical link data transmission ASICs have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I upgrade. The latency of each ASIC and its corresponding receiver implemented in the back-end FPGA, are critically specified to be less than 150 ns. We present the latency measurements of two ASICs. The optical link latency measurement results indicate that both ASICs achieve their...
We present the quality assurance (QA) test of LOCx2, a low-latency, low-overhead transmitter ASIC for the ATLAS Liquid Argon Calorimeter Phase-I upgrade. In the QA test we will screen about 7000 LOCx2 chips to ensure their basic functionality. The QA test system, including two printed circuit boards, firmware, software, are under development. All tests are automatically conducted and...
A VCSEL driver ASIC, LOCld, has been designed for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade. In total about 7000 chips have been produced and are in packaging process. We present the quality assurance test aiming at screening all functional chips before they are assembled into optical transmitter modules. A detailed test procedure is proposed. A dedicated test board has been designed...
This paper reports the development of a high resolution, low power, and adjustable in frequency Time-to-Digital Converter (TDC), based on two vernier Ring Oscillators (RO) made of standard XOR cells. The TDC is aimed at exploiting the excellent timing performance of the multigap Resistive Plate Chambers (RPC). The frequency of each RO is adjustable thanks to a 9-bit register from 340MHz to...
We present two designs of a dual-channel VCSEL driver ASIC, named LOCld130 and LOCld65, aiming for the upgrade of ATLAS Liquid Argon Calorimeter. Each channel of the driver operates at 5 Gbps or 10 Gbps respectively. They are implemented in commercial 130 nm and 65 nm CMOS technologies. In typical case the 5 Gbps driver dissipates 56 mW/channel (VCSEL included) and the 10 Gbps 58 mW/channel....
The ATLAS ITk is working to deliver a new Inner Tracking detector for use at HL-LHC. The strip tracker community has recently constructed partially loaded, double sided demonstrator staves using the HCC / ABC130 chipset in 130nm CMOS technology. Mindful of the need to maximise power efficiency whilst minimising the cost and material of associated cable plant, the system design includes the...
A compact-size, 64-channel, 80 MSPS, 14-bit dynamic range ADC module for the scintillating electromagnetic calorimeter of PANDA was developed, tested in various detector readout set-ups and are currently in mass production phase. The module performs signal filtration, extract important signal parameters and allow for resolving and parametrizing overlapping pulses. Processed data are pushed to...
We report on the design and performance of UFSD (Ultra-Fast Silicon Detectors) and their challenge for electronics systems. UFSD are segmented thin Low-gain Avalanche Detectors (LGAD) with measured time resolution of 30ps.
The combined accurate measurement of time and position for charged particle in UFSD offers unique physics capabilities such that they are being considered for use in the...
A unified platform combining a low noise 64-channel power supply with environmental monitoring and a high data rate transmission system, rated up to 1.2 Gbps/sec, has been developed for commissioning of the ATLAS ITk silicon strip hybrids. The power supply with 10mV peak-to-peak noise, implements 3kV isolation and software control. Humidity, temperature, voltage and current are monitored for...
The AdvancedTCA standard has been selected as one hardware platform for the upgrades of the back-end electronics of the CMS and ATLAS experiments of the Large Hadron Collider. In this context, the CERN EP-ESE group has designed and produced an IPMC mezzanine card for the management of AdvancedTCA blades. This paper presents the CERN-IPMC hardware and the software environment to be used for its...
R&D studies of readout electronics systems for accelerator based neutrino experiments have been carried out since 2008. The CMOS based cryogenic readout electronics is the enabling technology for giant (> 10kT) LAr TPC (Liquid Argon Time Projection Chamber) in neutrino experiments, which also has potential to be used in other noble liquid TPC based experiments (dark matter search, neutrino-...
In 2016, a TTC-PON (Timing, Trigger and Control system based on Passive Optical Networks) demonstrator was presented at TWEPP as an alternative to replace the TTC system, currently responsible for delivering timing, trigger and control commands in the LHC experiments. Towards a deployment foreseen for ALICE phase-1 upgrade, the system has been consolidated through flexible software...
We report on the measurements performed on the full custom ASIC TOFFEE designed to read out Ultra Fast Silicon Detectors (UFSD). The ASIC has been tested in laboratory with custom test boards and an infrared laser hitting the sensor and emulating a minimum ionizing particle signal.
Laser measurements showed that a time resolution of less than 50 ps is achievable with a 10 fC signal.
We will...
The H35DEMO chip is a HV/HR-MAPS demonstrator of 18.49 mm x 24.4 mm, fabricated with a 0.35 µm HVCMOS process from AMS in four different substrate resistivities. The chip is divided into four independent matrices with a pixel size of 50 µm x 250 µm. Two of the matrices include all the digital readout electronics at the periphery. This contribution describes the two standalone matrices of the...
We present the readout system being designed for triple-GEM detectors to be installed in 2019-2020 in the CMS muon endcap for HL-LHC. Beginning of 2017, 10 triple-GEMs have been installed in CMS. These detectors are read-out with the VFAT2 chip while its next version, the VFAT3, is under characterization. The rest of the readout system is very similar between the 2017 and the final version:...
During the extended year-end technical stop 2016/17 the CMS Pixel Detector has been replaced. The new Phase 1 Pixel Detector is designed for a luminosity that could exceed L = 2x10^34 cm^-2 s^-1. With one additional layer in the barrel and the forward region of the new detector, combined with the higher hit rates as the LHC luminosity increases, these conditions called for an upgrade of the...
Using FPGA technology for event building tasks in high-energy physics experiments reduces costs and increases reliability of DAQ systems. In 2014, the COMPASS experiment at CERN’s SPS commissioned a novel, intelligent, FPGA-based DAQ (iFDAQ) in which event building is entirely performed by FPGA cards. The highly scalable system is designed to cope with an on-spill data rate of 1.5 GB/s and a...
Modern data acquisition techniques employed in particle physics create large amounts of digital data that must be transmitted to remote electronics and computers for further processing. Increasingly, bandwidth requirements preclude the use of PCB traces and traditional copper cabling, even for modest interconnection length. Fortunately, novel copper and optical flyover solutions are being...
- General news from the CERN Foundry Service Team (10min)
- Single Event Latchup in 130nm circuits (10min)
- Stability of the TID response of 130 and 65nm technologies (5min)
- Total Ionising Dose response of 65nm MOSFETs irradiated to ultra-high doses (40min)
- Plans for the simulation of irradiated transistors in 65nm CMOS (5min)
- Plans for the evaluation of the TID effects in 40 and 28nm...
10 to 15 mns contribution + discussion
Recent advances in light detectors has led to the introduction of a number of highly pixelated but compact photomultiplier tubes. These PMTs require compact readout electronics that directly couple to the PMTs, are high performance and can provide timing resolution on par with the PMT. In this paper we propose a compact readout device for the Hamamatsu H13700 PMT with 256 pixels. The design is...
Mini-EUSO is a telescope and detector designed by the JEM-EUSO Collaboration to observe the UV emission of the Earth from the vantage point of the International Space Station (ISS) in an Earth orbit of around 400 Km. The main goal of the mission is to map the Earth in the UV, thus increasing the technological readiness level of future EUSO experiments and to lay the basis for the detection of...
Readout chips of hybrid Pixel detectors use low power amplifier and threshold discrimination to sense and digitise charge deposited in semiconductor sensor. Due to variability in CMOS transistors each pixel circuit needs to be calibrated individually to achieve response uniformity. Traditionally this is addressed by programmable threshold trimming in each pixel. In this presentation a...
The ALICE Central Trigger Processor (CTP) is going to be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing Control (TTC) system based on a Passive Optical Network (PON) system. The new trigger system has been designed as dead time free and able to transmit trigger data at 9.6 Gbps. A new universal trigger board has been designed, where by changing the FMC card,...
The AdvancedTCA (ATCA) telecom industry standard has been selected as the hardware platform for the “Phase-II Upgrade” of ATLAS at the Large Hadron Collider (LHC) at CERN.
In November 2014 a project dedicated to the study of the impact of the ATCA integration in the actual counting rooms was launched analyzing the impact on the cooling infrastructures. A spare rack equipped with two ATCA...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per...
The first implementation of Machine Learning inside a Level 1 trigger system at the LHC is presented. The Endcap Muon Track Finder at CMS uses Boosted Decision Trees to infer the momentum of muons based on 25 variables. All combinations of variables represented by 2^30 distinct patterns are evaluated using regression BDTs, whose output is stored in 2 GB look-up tables. These BDTs take...
The Pixel Luminosity Telescope (PLT) is a dedicated system for luminosity measurement at the CMS experiment using silicon pixel sensors. It was installed during LS1 and has been providing luminosity measurements throughout Run 2. The online bunch-by-bunch luminosity measurement employs the "fast-or" capability of the pixel readout chip (PSI46) to quickly identify likely tracks at the full...
ATLAS Experiment has reworked and upgraded some systems during the 2014-2016 LHC shut down and the Pixel Detector has inserted an additional layer: the Insertable B-Layer. The layers 1 and 2 have been also upgraded, using the same BOC and ROD cards designed for IBL, while maintaining the detector unchanged. Now the efforts focus on the upgrade of the B-Layer and the Disks, again leaving the...
In the framework of the ALICE experiment upgrade at HL-LHC, the whole electronics of the existing Muon Tracking Chambers (MCH) will be refactored with a new frontend chip and the associated readout electronics. This paper presents the design of the dedicated concentration cards ‘SOLAR’ to ensure the readout of 30,000 frontend chips. Based on the CERN GBTx and FEAST DCDC chips, allowing to work...
With ever-increasing luminosity at the LHC, optimum online data selection is getting more and more important. While in the case of some experiments (LHCb/ALICE) this task is being completely transferred to computer farms, the others - ATLAS/CMS - will not be able to do this in the medium-term future for technological, detector-related reasons. Therefore, these experiments pursue the...
The CRU (Common Readout Unit) is the new readout card that will be used in ALICE during Run 3.The card will receive detector data and it will store the information in the memory of the PC through DMA. To handle the high data throughput an Altera Arria 10 FPGA has been installed on the CRU.A custom DMA controller has been developed to optimize the DMA data transfer reducing the CPU utilization....
At the high-luminosity upgrade of the LHC (HL-LHC), the electromagnetic calorimeter of CMS (ECAL) will have to cope with a challenging increase in the number of interactions per bunch crossing and radiation levels. The ECAL front-end readout electronics was completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a...
At the high-luminosity upgrade of the LHC (HL-LHC), the electromagnetic calorimeter of CMS (ECAL) will have to cope with an increase in the number of interactions per bunch crossing and radiation levels. CMS implements a sophisticated two-level triggering system composed of the Level-1, instrumented by custom-designed hardware boards, and a software High-Level-Trigger. The off-detector...
We have developed a 2nd generation high resistivity CMOS process, suited for integration of complimentary pixel circuitry. High charge collection efficiency can be maintained after neutron irradiation up to 1016 neq/cm2 when applying a depletion voltage to the backside of the 50 µm thick devices. Results measured with a 15 µm MAPS detector, fabricated in this technology, will be...
The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40-80 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS...
A testbeam telescope, based on the ATLAS IBL silicon pixel modules, has been built to investigate the possibility of using the CMOS technology in the HL-LHC upgrade of ITk. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between different front-ends and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed...
The ATLAS first-level Endcap Muon trigger in LHC Run-3 will
identify muons by combining data from the Thin-Gap chamber detector (TGC) and a new detector, called the New-Small-Wheel (NSW). In order to handle data from both TGC and NSW, new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger...
The Silicon Vertex Detector of the Belle II Experiment at the KEK in Tsukuba, Japan, consists of 172 double-sided strip sensors. They are read out by 1748 APV25 chips, and the analogue data are sent out of the radiation zone to 48 modules which convert them to digital. FPGAs then compensate line signal distortions using digital finite impulse response filters and detect data frames from the...
A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics was developed to test and validate the architecture of front-end driver (FED) firmware. The emulation, implemented on the CERN GLIB uTCA platform, drives optical transmitters to the back-end electronics. The firmware emulates the complex functions of the readout chips and Token Bit Managers and allows for...
During first long stoppage (LS1) of the LHC, the Central Trigger Processor (CTP) of the ATLAS experiment has been upgraded. In addition to enriched functionality, it resulted in increasing the CTP input-output latency by 75 ns (3 cycles@40 MHz). The ALFA triggers were no longer early enough to contribute to the global ATLAS triggering. A dedicated input board, speeding up the ALFA signal...
The contribution shows possibilities of the readout for Timepix3 (Ethernet Embedded Readout Interface for Timepix3 – called Katherine) for a wide range of applications. The architecture and features of the system are described in detail. The stress is laid on the usage of more readouts in a telescope configuration, where more Timepix3 sensors are operated and their time-dependent functions are...
We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS muon spectrometer. The processor will fit candidate muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an...
This paper will present the irradiation test results performed on the first two prototypes (MPW1 and V2) for the new readout ASIC (SAMPA). The SAMPA chip is aimed to be used in the ALICE Time Projection Chamber detector (TPC) and ALICE Muon Chamber (MCH) detector during RUN3 starting in 2021. The irradiation tests have been performed using proton beams of 180 MeV.
A next generation control infrastructure to be used in Advanced TCA (ATCA) blades at CMS experiment is being designed and tested. Several ATCA systems are being prepared for the High-Luminosity LHC (HL-LHC) and will be installed at CMS during technical stops. The next generation control infrastructure will provide all the necessary hardware, firmware and software required in these systems,...
Readout Electronics for the First Large HV-MAPS Chip for Mu3e
Mu3e is an upcoming experiment searching for charged lepton flavor violation in the rare decay mu->eee. A silicon pixel tracker based on 50 um thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1T magnetic field will deliver precise vertex and momentum information. The MuPix HV-MAPS chip combines pixel sensor cells...
The instantaneous luminosity of the LHC at CERN will be increased up to a factor of seven with respect to the original design value to explore higher energy scale. The first station of the ATLAS muon end-cap Small Wheel system need to replaced by a New Small Wheel (NSW) detector. The NSW provide precise track segment information to the muon Level-1 trigger to reduce fake triggers. This...
For the LS2 upgrade of the ITS detector in the ALICE experiment at the LHC,
a novel pixel detector chip, the ALPIDE chip, has been developed. In the event
of busy ALPIDE chips in the ITS detector, the readout electronics may need
to take appropriate action to minimize loss of data. A lightweight, statistical
simulation model for the ALPIDE/ITS has been designed using the...
In the context of the ATLAS Phase-II upgrade, new front-end electronics is developed, which reads out the detector at higher bandwidth due to finer granularity and higher occupancy.
Because of the high bandwidth requirements, new concepts are needed for the ATLAS ITk readout system. A new scalable approach based on many rather simple nodes is proposed to support lab setups, testing sites as...
During the ATLAS Phase-I upgrade, the global feature extractor (gFEX) will be designed to maintain the trigger acceptance against the increasing luminosity for the ATLAS Level-1 calorimeter trigger system. The prototypes v1 and v2 have been designed and tested in 2015 and 2016 respectively. With the lessons learned, a pre-production board with three UltraScale+ FPGAs and one ZYNQ UltraScale+,...
The End-Of-Substructure Card (EoS) is the interface between the building block of the ITk Strip Tracker and the outside world. All the control and command signals, the data and the power will be passing through it. The card concept is built around using the lpGBT chip set and the VTRx optical link. The EoS will handle up to 28 640 MBit data links and 10 GBit Downlinks and Uplinks. It will be...
Our work aims at improving the performances of the NA62 low-level trigger implementing a real-time stream processing architecture based on an orchestrated combination of heterogeneous computing devices (CPUs, FPGAs and GPUs).
To enable it we devised NaNet, a FPGA-based PCI-Express Network Interface Card with processing and GPUDirect capabilities, which supports multiple link technologies...
The LHCb experiment is currently engaged in an upgrade effort that will implement a trigger-less 40 MHz readout system. The upgraded Front-End Electronics profits from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new and final version of the firmware core that transmits slow control information from the...
The TrainBuilder is an ATCA based data acquisition system developed at the STFC Rutherford Appleton Laboratory to provide readout for each of three Mega-pixel detectors at the European-XFEL Hamburg. Each Train Builder system constructs over 5,000 detector images per second using FPGAs with DDR2 data buffering and an analogue crosspoint switch architecture; thereby processing 10 GBytes/sec of...
Yet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb/s bandwidth of the next generation readout chip in development by the RD53 collaboration for...
Metallic magnetic calorimeters (MMC) are new cryogenic detectors that offer a high resolution of single eV, a signal rise time of below 100 ns, a dynamic spectrum of several 10 keV and an almost optimal linearity. MMCs are of high interest for many experiments, such as dark matter detection or neutrino mass specification. Since pixel arrays of the sensor are read out at GHz-Frequency and each...
Single-Event Upsets (SEUs) in the configuration memory of a 28 nm FPGA, used in the PANDA electromagnetic calorimeter, have been studied. Results from neutron and proton irradiations are presented. A GEANT4-based Monte Carlo simulation of SEU mechanisms in nanometric silicon volumes has been developed for studies of the energy dependence. At PANDA, a neutron flux of $1\cdot10^2$ cm$^{−2}$...
The upgrade of the Compact Muon Solenoid (CMS) crystal electromagnetic calorimeter (ECAL), which will operate at the High Luminosity Large Hadron Collider (HL-LHC), will achieve a timing resolution of around 30 ps for high energy photons and electrons. We will discuss the benefits of precision timing for the ECAL event reconstruction at HL-LHC. Simulation studies on the timing properties of...
The outer radii of the inner tracker (ITk) for the Phase-II Upgrade of the ATLAS experiment will consist of groups of silicon strip sensors mounted on common support structures. Lack of space creates a need to remotely disable a failing sensor from the common HV bus. We have developed circuitry consisting of a GaNFET transistor and a HV Multiplier circuit to disable a failed sensor. We will...
Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the...
In the past two decades, there has been numerous attempts to take advantage of semiconductor solutions, broadly defined, to create high-performance biosensors and bio-molecular detection devices. The goal has always been to create molecular diagnostics technologies that offer the cost efficiency, miniaturization capabilities, and manufacturing robustness of consumer electronics devices. The...
TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal...
We present a theoretical analysis, simulation and implementation results of an FPGA-based wireless Time Interval Measurement (TIM) system. The TIM features a single channel TDC with a Serial Peripheral Interface (SPI) and wireless transmission. The TDC is based on the Vernier ring oscillator method to achieve both high resolution and wide dynamic range. The TDC architecture with an SPI is...
The GBT-FPGA, part of the GBT project framework, is a VHDL-based IP designed to offer a back-end counterpart to the GBTX ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the HEP experiments. In this context, a new module named GBT-SC has been designed and...
This work presents a Depleted Monolithic Active Pixel Sensor (DMAPS) prototype manufactured in LFoundry 150 nm CMOS process. The described device, named LF-Monopix01, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of ATLAS Inner Tracker upgrade for High Luminosity LHC. Implementing such device in the detector will result...
For the Phase II Upgrade of LHC, new hybrid silicon pixel detectors are required for charged particle tracking. The RD53 collaboration is currently designing a large-scale prototype sensor readout chip “RD53A”, which will be available soon. The SiLab group at the University of Bonn is highly involved in testing/verification and several chip design tasks.
A modular and versatile test- and...
We present the latest results of the FE65-P2 pixel readout test chip. This is a 64 by 64 pixel matrix on 50 um by 50 um pitch, produced in 65nm CMOS technology at the end of 2015. FE65-P2 was designed to demonstrate small pixel performance and stable operation down to 500 electron threshold even with the front end pixel amplifiers embedded in a synthesized logic environment. The FE65-P2...
The ATLAS experiment at CERN plans to upgrade its Inner Tracking system for the High-Luminosity LHC in 2026. After the ALPIDE monolithic sensor for the ALICE ITS was successfully implemented a 180nm CMOS Imaging Sensor technology, the process was modified to combine full sensor depletion with a low sensor capacitance (~2.5fF), for increased radiation tolerance and low analog power consumption....
High-performance analog-to-digital converters (ADCs) are becoming essential
building blocks in many applications including optical communications, high-speed test
equipment such as real-time oscilloscopes, and high-energy particle physics, etc. While several ADC architectures have been proposed, SAR (Successive Approximation Register) has become the de facto preferred design, because of its...
The upgraded CMS Level-1 trigger is designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). During the technical stop at the beginning of 2016, all the electronic boards of the CMS Level-1 trigger have been replaced and the upgraded electronics tested, and commissioned with data. The upgrade of both the Stage-1 and...
A Real-Time demonstrator based on the ATCA Pulsar-IIB custom board and on the Pattern Recognition Mezzanine (PRM) board has been developed as a flexible platform to test and characterize low-latency algorithms for track reconstruction and L1 Trigger generation in future High Energy Physics experiments. The demonstrator has been extensively used to test and characterize the Track-Trigger...
A prototype second-stage buck DC-DC converter has been designed in 130nm CMOS and fully characterized. This circuit provides up to 3A at an adjustable output voltage of 0.6-1.5V from an intermediate bus voltage of 2.5V. Hardness by design techniques have been systematically used, and the prototype successfully passed TID irradiation up to more than 200Mrad and Single Event Effects tests with a...
The Fast Tracker (FTK) system, one of the ATLAS trigger upgrades, is presently being commissioned. The information from the 100 million channels of the tracking detectors is presently exploited at the HLT only for a subset of the events or for limited detector regions due to timing limitations. The FTK system is designed to deliver full event track reconstruction for all tracks with pT above 1...
- New devices (FinFETs) and fluid guardrings
- Double/ Multiple Patterning aka coloring
- Gridded/ track based placement and routing methodology
- In-design dynamic/ post-edit DRC checking to support new constraints including color and grid checks
Abstract
Continuous advancement in process technology following Moore’s law over the past few decades has greatly increased IC design...
Moore's Law has entered a new frontier as device scaling continues to excel in 10nm and beyond. As the physical dimension of devices and interconnect are being shrunk, the design rules and the design flow, for both design community and EDA community, face unprecedented complexity. Conventional design optimization techniques also need to take the novel process technologies, such as multi-gate...
- In-design extraction and analysis of parasitics, EM/ IR and LDE parameters
- Resimulation with parasitics and LDE parameters from a layout in-progress (prior to sign-off)
- Using electrical constraints to verify and meet design requirements
Abstract
Advanced nodes have introduced many new design challenges including significantly greater impact of parasitics and other electrical...
a. Why we need integrated simulation environment?
b. Environment for individual block
c. Environment for block integration.
d. Environment for verification and regression.
e. Summary
a. Implementation flow
b. Analysis flow
