2nd FPGA Developers' Forum (FDF) meeting

20 May 2025, 09:00 → 23 May 2025, 20:00 Europe/Zurich

500/1-001 - Main Auditorium (CERN)

Davide Cieri (Max Planck Society (DE)), Francesco Gonnella (University of Birmingham (GB))

The FPGA Developers’ Forum (FDF) is a platform to discuss and exchange information, experiences, implementation ideas, tips, and tricks as well as challenges faced with design tools, specific FPGA technologies.

The 2nd FDF meeting will take place at CERN from 20th to 23rd May 2025.
We will discuss several FPGA related topics, look at the scientific programme on the sidebar for details.

We are open to new ideas and the list will be adapted depending on your contributions. Have you got something to share with the community?

Submit an abstract now for your presentation through the button below.

There is no registration fee, you’re very welcome to participate in the FDF meeting even if you’re not giving a talk. And remember that FDF is open to anyone, not only CERN users.

The FDF aims to form a topical community of digital designers — especially on FPGAs —  working in physics and beyond, and to discuss details that very rarely see the light of day in typical workshops in our field. 

We will focus on the ‘how’ digital designs are implemented rather than their scientific end-goal, and novelty is not the only criterion. Sharing tips on how to avoid pitfalls, or other ideas and recommendations that could save your colleagues precious time, are considered equally important.  

A CERN account is needed for the submission and registration. If you do not have one, it can be created here.

See you at CERN!

We extend our sincere thanks to our sponsors for their generous support.

Gold Sponsors:

Silver Sponsors:

   

 

 

Tuesday 20 May

14:00 → 15:10 Introduction

14:00 Welcome to the 2nd FPGA Developers' Forum

14:20 Welcome to CERN

14:40 The future of FPGAs in HEP detectors for FCC and beyond

Speaker: Sophie Baron (CERN)

15:10 → 15:40 Tea Break

15:40 → 18:10 Sharable HDL cores

15:40 Open Logic – open-source FPGA Standard Library

Open Logic is the fastest-growing open-source HDL standard library on the market, as measured by GitHub stars. It simplifies FPGA development with reusable, modular, and vendor-independent components. Bridging the gap between hand-optimized HDL code and high-level abstractions like HLS and IP integration, it offers a balanced approach to effort and resource optimization. With a strong focus on code quality, verification, documentation, and ease of use, Open Logic ensures both reliability and accessibility.

This presentation will highlight the library's philosophy, its place in the FPGA design landscape, and the advantages it offers, including device independence and reduced maintenance effort. Attendees will explore key features such as FIFOs, AXI utilities, and CAMs, and discover how to integrate Open Logic effectively into their projects.

Speaker: Oliver Bründler (OpenLogic)

16:15 TBD

Speaker: Calliope-Louisa Sotiropoulou (CAST)

16:45 The PandABlocks framework for flexible run-time configuration of Zynq SoCs

The PandABlocks framework comprises FPGA gateware, linux kernel and root filesystem for the PS, a TCP server and web-UI. It was originally developed to support the Zynq-7000 based PandABox hardware platform used in beam line scanning applications at several synchrotron light sources for orchestration of motion systems and detectors. The PandA collaboration, consisting of Diamond Light Source, Soleil, MAX-IV, ALBA, and DESY, is currently working on the design of the successor to the PandABox based around a Zynq Ultrascale+ SoC. A key feature of PandABlocks is that the connections between functional blocks are re-wirable at run-time by the user, through the multiplexing and demultiplexing of buses distributed throughout the logic. This means that we do not need to maintain multiple versions of FPGA firmware for different beam lines or user applications. The framework includes a register interface, DMA capture of data, and precision synchronisation between hardware devices via MGTs.

Speaker: Glenn Christian (Diamond Light Source)

17:10 NDK: An open-source framework for high-speed network applications on FPGAs

CESNET (Czech Education and Scientific Network) has a long history of providing backbone connectivity and services to institutions such as universities and research centers. One of its subdivisions, tasked with monitoring network traffic, was already familiar with the FPGA technology when 100 GE networks emerged. Soon after, we developed our first FPGA-based network card and firmware to pre-process the monitored network traffic, marking the inception of the NDK (Network Development Kit) framework.
With Cesnet’s transition to 400G lines, network monitoring and the NDK framework also evolved. Aiming to quadruple the throughput, we opted to widen the datapaths instead of increasing the clock signal frequency. Wider datapaths led us to create a new concept of buses, enabling us to process multiple frames each clock cycle. With its software drivers, flexible build system, and the support of FPGAs from various vendors, the NDK is a suitable framework for a wide range of NIC applications.

Speakers: Daniel Kondys (CESNET), Radek Iša (CESNET)

17:40 Error-Redundant Implementation of Commercial IP Cores: A Practical Example

The reuse of predefined IP cores is a well-established practice in semiconductor design, offering cost and technical advantages. However, commercial providers must meet diverse implementation requirements, ensuring compliance with specifications while optimizing power, frequency, gate utilization, and feature scope. Additionally, IP cores must function reliably across FPGA and ASIC platforms, often under harsh conditions.
Fault tolerance demands techniques like triple-mode redundancy, error correction codes, and fail-safe state machines—but the greater challenge lies in verification and validation. These processes are time-intensive and costly, especially for third-party certification.
This paper presents a case study on implementing, verifying, and validating a PSI5 Controller IP core developed by SmartDV to meet ASIL-B certification under ISO 26262. It highlights key challenges and best practices for designing error-redundant IP cores.

Speaker: Mr Philipp Jacobsohn (SmartDV)

18:20 → 20:20 Welcome Reception

Wednesday 21 May

09:00 → 10:50 Algorithm Implementation: 1

09:00 Exploring Linearity and Temperature Stability in Time-to-Digital Converters

High-precision time measurements on the order of picoseconds ($10^{-12}$), as required in fluorescence lifetime microscopy and time-of-flight (ToF) applications, can be achieved using Time-to-Digital Converters (TDCs). Traditional timing methods rely on high-frequency clock counters, which become impractical for such small time intervals. A solution is to exploit the hardware of FPGAs to achieve sub-clock time resolutions. Although much of the existing literature on TDCs focuses on minimizing resolution while maintaining accuracy, the linearity and temperature dependence on performance is often overlooked. These factors are strongly tied to the underlying fabrication technology and hardware architecture. This presentation explores a Tapped-Delay-Line (TDL) TDC design implemented across different FPGA families (AMD, Efinix, Intel), with an emphasis on their linearity and temperature dependency, highlighting the performance differences and considerations for practical applications.

Speaker: Gian-Luca Brazerol (Ostschweizer Fachhochschule)

09:30 Implementation of Time to Digital Converter on FPGA for high-resolution-performance in Particle Therapy applications

Time-to-digital converters (TDCs) are essential for precise time measurements in several domains. FPGA-based TDCs are a flexible, low-cost, highly customizable alternative. We have implemented an FPGA-based TDC based on a tapped delay line architecture, targeting the latest device families of AMD, to measure single particle transit times in a silicon sensor with a <30ps resolution at Particle Therapy clinical rate (average rate of 1e7-1e9 pps). This is highly needed for new in-vivo online treatment verification techniques, e.g. Prompt Gamma Timing. The TDC design relies on carry-logic blocks to introduce a small delay, and latch-based observation points placed at regular intervals along the chain to sample the signal at discrete time steps. Manufacturing process variations are addressed by acting directly on placement and routing. A synchronous counter is enabled to extend the measurement range. Experimental validation confirmed an average of 5.8 ps with an uncertainty of 30 ps.

Speaker: Mr ARASH AMINI BARDPAREH (Politecnico di Torino)

09:50 A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine

Trying to modulate the RF cavity of a Synchrotron Light Source by leveraging Reinforcement Learning, resulted in a hardware implementation of the Gated Recurrent Unit (GRU) on the Versal AI Engine, by AMD Xilinx and extremely efficient in performing the main numerical operations needed by the model.

RNNs have been designed to handle time series, and they are the perfect candidates to handle this kind of task. Although RNNs don't parallelize well, their ability to distill input and pass information into the hidden state, could be beneficial for real time control tasks.
I will firstly introduce the AI Engine and its features. Second, I will introduce the GRU cell. Then I will show how numerical operations are being implemented in the AI Engine and its memory limitations. Finally, I will discuss how we tackled the lack of built-in activation functions, since the tanh and sigmoid function implementations are needed.

Speaker: Michail Sapkas (Universita e INFN, Padova (IT))

10:20 TBD

Trenz Electronic

10:50 → 11:20 Coffee break

11:20 → 12:50 Algorithm Implementation: 2

11:20 Distributed Arithmetic for Real-time Neural Networks on FPGAs

Neural networks with a latency requirement at the order of $\mu$s, like the ones used at the CERN Large Hadron Colliders, are typically deployed on FPGAs fully unrolled. A bottleneck for deployment of such neural networks is area utilization, which is directly related to the constant matrix-vector multiplications (CMVM) performed in the networks. In this work, we implement an algorithm that optimizes the area consumption for such neural networks on FPGAs by performing the CMVMs with distributed arithmetic (DA) and integrate with the hls4ml library, a FOSS library for running real-time neural network inference on FPGAs. The optimized resource usage and latency are compared with the ones from the original hls4ml implementation on different networks. The results show that the proposed optimization can achieve a reduction of on-chip resource by up to a half in realistic quantized neural networks, while reducing the latency by up to 40\%, all while maintaining bit-accurate output values.

Speaker: Chang Sun (California Institute of Technology (US))

11:50 Chisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators

Chisel4ml is a tool we developed for generating fast implementations of deeply quantized neural networks to FPGA devices. The tool is implemented in the Chisel Hardware Construction Language, and has a frontend in Python, to enable interfacing with neural network training libraries. We will present basics of the Chisel language and compare chisel4ml against hls4ml. In general, chisel4ml, is able to generate the hardware much faster then high-level synthesis solutions, because it uses structural descriptions of the circuits.

Speaker: Jure Vreča (Jožef Stefan Institute)

12:20 A Reconfigurable FPGA-Based ML Library for Kernel Methods

Kernel methods are fundamental in machine learning. They excel in regression, classification, and dimensionality reduction. They model nonlinear relationships and are widely used in many fields such as in face recognition, wind forecasting, and molecular energy estimation. However, their reliance on a kernel matrix leads to quadratic complexity in computation and storage, which makes large-scale datasets challenging.
We propose an FPGA-accelerated library with high parallelism and efficient data movement. The library is accessed from Python via PYNQ with a plug-and-play solution without requiring hardware expertise. It currently supports Kernel Ridge Regression and Gaussian Processes. Five kernel functions are supported, with Partial Reconfiguration to switch between them. We achieve 30x speedup compared to Python libraries on a Kria SOM.
Future work includes extending support to other kernel methods, and heterogeneous FPGA architectures like AMD Versal, with more advanced kernels.

Speaker: Yousef Alnaser (TU Chemnitz, Fraunhofer ENAS)

12:50 → 14:00 Lunch

14:00 → 14:40 Algorithm Implementation: 3

14:00 Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments

The ever-increasing data rates and ultra-low-latency requirements of particle physics experiments demand innovations for real-time decision-making. Transformer Neural Networks (TNNs) have demonstrated state-of-the-art performance in classification tasks, including jet tagging, but implementations on CPUs and GPUs fail to meet the constraints for real-time triggers. This work introduces two novel TNN architectures optimized for Field-Programmable Gate Arrays. The first one prioritizes latency, achieving a speedup of >1000× over GPU implementations while maintaining accuracy. The second one explores trade-offs between latency and accuracy through design-space exploration and a custom post-training quantization, which identifies optimal bit-widths, yielding significant reductions in hardware resource utilization with negligible accuracy degradation. Experiments demonstrate the effectiveness of these designs, setting new benchmarks for real-time machine learning in high-energy physics.

Speaker: Filip Wojcicki (Imperial College London)

14:20 FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems

Reservoir Computing (RC) is a new paradigm in Machine Learning, alternative to Neural Networks on predicting dynamical systems, offering advantages in efficiency and computational simplicity. These characteristics make RC particularly well-suited for implementation on resource-constrained hardware such as FPGAs, enabling low-power, real-time edge computing. Next-Generation Reservoir Computing (NG-RC) further enhances this approach by significantly reducing the number of required parameters compared to conventional RC, making FPGA implementations even more efficient. In this work, we present an FPGA-based implementation of NG-RC for predicting the Lorenz attractor, demonstrating its effectiveness in modeling chaotic systems with minimal computational overhead.

Speaker: João Folhadela (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))

14:40 → 16:00 Solutions to everyday digital design problems: 1

14:40 Abstract interface modelling for better genericity and code clarity

AXI4 (Memory-Mapped, Stream) is a well established set of flexible bus interfaces. They can support various address and/or data widths, have optional support for bursts, byte strobing, back-pressure, sideband signals, etc.

Writing generic yet easily maintainable AXI-compatible modules is hard: implementation must take care of abiding interoperability rules for optional signals at all times. Using generics and relying on default port values is root for a code maintenance nightmare, if even possible at all.

Using standard VHDL-93 constructs, We propose an approach for modelling interfaces and configuration in an abstract manner in a way it guarantees correct protocol encoding/decoding with enhanced code compactness, clarity and genericity, still producing optimal synthesis results.

Method, applied to AXI4, will be described in depth. Application of the method to other classes of modelling problems will be discussed.

Reusable library will be available under MIT license.

Speaker: Nicolas Pouillon (Ellisys)

15:10 Disruptive Efinix Quantum Architecture

In this session we will explain the new disruptive architecture from our new low power, high speed FPGA Families. This architecture is different to the standard FPGA architecture and has a lot of benefits compare to the old architecture.
We will go thru the different FPGA Families which are based on this Quantum architecture and we will work out the benefits for the user if they are using there FPGAs. At the end we will have a closer look into the free of charge Software and evaluation Boards which can be used to design the FPGAs

Speaker: Harald Werner (Efinix Inc.)

15:40 CERN ABT's lazy git workflow for equipment-specific designs

ABT has several mixed gateware/software projects, such as its fast interlocks (FIDS) and kicker timing routing (KiTR) systems, that require a specific top-level design for each equipment (e.g. PS KFA45 injection pulse generators) while at the same time also sharing a set of common HDL cores and AXI bus architecture. Git submodules answer the need of common cores well, however also the top-level design, project structure and submodules have many commonalities.

To cater for this, a branch-per-equipment approach is currently used to reduce HDL duplication and porting efforts. An automated GitLab CI/CD multi-project pipeline ensures up-to-date simulation, synthesis, compilation, packaging and delivery when triggered, wich can happen at several levels. This lazy approach, with its advantages and disadvantages, is presented here.

Speakers: Léa Strobino (CERN), Pieter Van Trappen (CERN)

16:00 → 16:30 Tea Break

16:30 → 18:10 Solutions to everyday digital design problems: 2

16:30 Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers

The Electron Ion Collider (EIC) Timing Data Link requires high precision clock recovery for accelerator master clock distribution. To meet the performance requirements a novel method for extracting a low jitter data frame clock from serial encoded data using Xilinx Ultrascale+ transceivers is presented. The frame clock frequency is at the word rate of the serial data link and its phase is deterministic. Dedicated FPGA output pins are used to eliminate phase drift from routing variations and minimize the effects of process, voltage, and temperature (PVT). This method enables timing endpoints to recover the accelerator master clock with minimal added phase noise.

Speaker: Paul Bachek (Brookhaven National Lab)

16:50 Standardizing SoC Development at CERN: A Build System for Xilinx Platforms

With the increasing adoption of SoC-based systems at CERN, new initiatives have been put in place to ensure that systems of similar form share as many components (hardware, gateware and software) as possible. As part of the DI/OT framework - now being integrated also into CERN's ATS SoC Common Framework Project - a new standardized build system has been developed to generate boot images for these platforms. This build system is modular, expandable and designed to streamline the HDL synthesis and compilation of Xilinx SoC-based projects, with strong emphasis on re-usability and standardization. It is also CI-friendly, aligning with CERN IT's new CI4FPGA developments for CI runners and Docker images. The use of this build system will be encouraged by the ATS sector, which constitutes Work Package Task 1.1 within the SoC Common Framework.

Speaker: André Pinho (CERN)

17:20 Reset Usages in FPGAs

I will talk about reset usages in FPGAs and some solutions to practical problems in asynchronous, synchronous and no reset scenarios on different FPGA families. I will point out that the optimum reset usage depends on not only coding styles but also built-in reset features and behavioral differences (e.g. RAM-based vs FLASH-based FPGAs) of the FPGA family in use. Moreover, I will explain how to integrate reset related linting checks into CDCI cycles so that potentially hazardous design and or verification issues are diagnosed at the early stages of projects. I will exemplify some problems I solved in the past. Planning to also mention tools like Questa Lint, RDC, CDC and their Open Source alternatives.

Speaker: Koray Karakurt

17:50 The new CI4FPGA service at CERN

The CI4FPGA service aims to provide CERN-based FPGA developers with suitable infrastructure and
pre-configured Docker images for all essential EDA tools, while maintaining high ease of adoption
for its users. This should eliminate the need for individual development teams to deploy and,
importantly, maintain their own solutions. Furthermore, by simplifying access to CI workflows, it
can help enhance confidence in the quality of shared code, thereby increasing collaboration and code
reuse across teams.

This presentation will introduce this new service, outline the types of runner nodes available for
running CI jobs, describe the pre-configured Docker images, demonstrate the comprehensive,
automatically-generated documentation that supports the service, and highlight convenience features,
such as pre-compiled simulation libraries.

Speaker: Christos Gentsos (CERN (IT-CA-GES))

20:00 → 23:20 Social Dinner

Thursday 22 May

09:00 → 10:30 HDL Development Tools: 1

09:00 Application-Specific Arithmetic Operators with the FloPoCo HDL core generator

Software programming languages have trained us to view computing in terms of a handful of operations over a handful of integer and floating-point formats: those supported by general-purpose processors and GPUs. In FPGAs, however, we have the opportunity to design the arithmetic for the application. This is both a qualitative challenge (what is the best way to compute an exponential or an FFT in an FPGA?) and a quantitative one (how many bits are necessary and sufficient on each bus of the hardware?).
Addressing these challenges has been the goal of the open-source FloPoCo project (www.flopoco.org) for 15 years. This talk will demonstrate some of its fancy operators, review some of the methodologies developed for optimizing and testing them, and discuss the challenges and opportunities of HLS in this context. It will also shamelessly advertise our recent book "Application-Specific Arithmetic: Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era".

Speaker: Florent de Dinechin (INSA-Lyon)

09:30 Customized eFPGAs with FABulous

FABulous is an eFPGA (embedded FPGA) framework comprising a full ecosystem for specifying, simulating, emulating and implementing FPGA ASIC macros as well as for providing the corresponding FPGA CAD suite for implementing user designs (the bitstreams) for the custom-defined eFPGAs.
[https://fabulous.readthedocs.io/en/]
This ecosystem integrates a range of open-source tools, including Yosys, nextpnr, Verilator and can use OpenLane and industry tools for the ASIC backend. FABulous FPGAs have been manufactured in Skywater 130, GF 180, TSMC 180, 130, 28nm nodes and the framework has users such as SLAC at Stanford University and New York University.
This talk will introduce the framework and demonstrate how a fabric with LUTs, DSP blocks, and BRAMs can be specified in just a minute. Moreover, it will also be shown how complex custom primitives can be added into FABulous fabrics and then instantiated in the FPGA bitstream generation flow. We will also reveal our FABulous chip gallery.

Speaker: Dirk Koch (Ruprecht-Karls-Universität Heidelberg)

10:00 Allo: A Python-Embedded Programming Model for Composable Accelerator Design

Special-purpose hardware accelerators are critical for performance gains amid slowing technology scaling, but designers lack effective tools to build complex accelerators. Existing high-level synthesis (HLS) tools require intrusive source-level changes to attain high performance while most accelerator design languages excel only with simple kernels. In this talk, we present Allo [PLDI’24], a Python-embedded programming model for composable accelerator design. Allo decouples hardware customizations (compute, memory, communication, data types) from algorithms, and encapsulates them as primitives. By preserving program hierarchy, Allo integrates customizations bottom-up, enabling holistic optimizations across functions. Evaluated on HLS benchmarks and real-world applications, Allo outperforms state-of-the-art tools. Allo-generated accelerators for machine learning models achieve superior latency and energy efficiency compared to GPUs, showing scalability for complex, large-scale designs.

Speaker: Hongzheng Chen (Cornell University)

10:30 → 11:00 Coffee break

11:00 → 12:50 HDL Development Tools: 2

11:00 Generating memory maps with Cheby and Reksio

Cheby is an HDL tool which transforms a YAML description of a memory map into HDL code, C header, python constants or HTML documentation. The tool was designed to be flexible: it supports many buses, many kinds of peripherals (registers, memories, wires, submodules) as well as structural features like repetition. The tool was also designed to be extensible: it can easily be extended to add new generators (like generations of constants for a different language or generation of drivers).

Using Reksio, you don't need to learn the syntax of the input file. This graphical user interface provides an interactive way to write or modify a memory map and to generate files within a click.

Speakers: Mr Bartosz Bielawski (CERN), Tristan Gingold (CERN)

11:20 HDLRegression: A reliable and efficient tool for FPGA regression testing

HDLRegression was developed to provide a reliable, efficient tool for regression testing of maintenance testbenches for UVVM and other FPGA project testbenches. It simplifies simulations with minimal changes—just a single comment in the testbench entity—making it easy to integrate into existing projects.

One big advantage is its independence from any specific verification framework, enabling use with UVVM, OSVVM, VUnit, or any other in-house tools for maximum flexibility.

As FPGA designs grow more complex, numerous tests are needed to verify functionality. HDLRegression addresses this with efficient, customisable test execution and a structured testing environment where results are easily accessible.

By offering reliable and efficient regression testing, HDLRegression improves testing processes, reduces complexity, and increases reliability in FPGA projects.

Speaker: Marius Elvegård (Inventas)

11:50 Common Exchange Format for HDL Build Systems

The diverse landscape of open-source HDL build systems, including VUnit, FuseSoC, HdlMake, HDLRegression and Bender, presents a challenge in terms of interoperability. While each tool offers unique advantages for managing HDL projects and their testbenches, their disparate methods for project description and dependency management impede the seamless integration of reusable libraries and IP cores. Incorporating widely adopted resources like OSVVM or UVVM or PoC-Library or Open Logic often requires significant adaptation across different build environments. To address this fragmentation, we propose the development of a common exchange format for build system information, drawing inspiration from the Language Server Protocol (LSP). This standardized format would enable build systems to exchange crucial project metadata, dependency specifications, and build configurations, fostering a more unified and efficient open-source ecosystem.

Adopting a universal exchange format would yield significant benefits for FPGA designers. It would enhance library and IP core reusability through standardized metadata, improve tool interoperability, and simplify project adoption/migration. Ultimately, this format would facilitate higher-level tooling and services across build system ecosystems, promoting collaboration and efficiency within the FPGA design community.

Speaker: Lieven Lemiengre (Sigasi)

12:20 nextpnr - customisable place and route for customisable silicon

nextpnr is an open source place and route toolchain for a range of FPGA devices. Through the himbächel and viaduct frameworks, it can easily be retargeted to new FPGAs, be it commercially available parts or eFPGAs for research purposes. This talk will cover some of the recent experiences in doing this, and some interesting insights into FPGA architecture variation and tradeoffs learnt in the process.

Speaker: Myrtle Shah (YosysHQ Gmbh)

12:50 → 14:10 Lunch

14:10 → 16:00 Verification

14:10 Enhancing FPGA Verification by Combining VUnit and UVVM

This talk explores the synergy between VUnit and UVVM, two leading open-source
verification frameworks for VHDL. UVVM provides a structured approach with powerful
testbench utilities and verification components, while VUnit enhances automation,
advanced test management, and continuous integration support. Additionally, VUnit
enables seamless use of multiple simulators within a single project setup.

The session includes practical examples and best practices to demonstrate how combining
these tools streamlines FPGA verification, improves productivity, and ensures maintainable
and expandable testbenches.

Speaker: Mr Markus Leiter (P2L2 GmbH)

14:40 TBD

Speaker: Mr Hardik Shah (Lattice Semiconductor)

15:10 Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage)

Requirements Tracking is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space and Avionics) applications.

Unfortunately, this is often handled manually, which is very time-consuming and error-prone. The open Source UVVM’s Specification Coverage allows a really efficient collection of predefined requirements, and it generates the reports you need for both mission-critical and safety projects, and in fact for any Project where quality is important.

This presentation gives a brief overview of Specification Coverage before going into more details of proper Requirements Tracking. It also shows what is provided with UVVM and how this could be applied.
UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage. UVVM has been the fastest growing FPGA verification methdology and Library over the last 4 and 8 years (cf Wilson Research)

Speaker: Espen Tallaksen (EmLogic)

16:00 → 18:00 CERN Campus Visits

Friday 23 May

09:00 → 10:25 Verification: 2

09:00 Python-based, flexible testbench for a spacecraft payload

Testing an FPGA design is complex and time consuming. Testing the main payload of an ESA mission spacecraft much more so. While modern HDL languages have powerful test capabilities, they can hardly match the unbounded facilities provided by Python. We have thus devised a flexible, cocotb-based framework for the task, in which JSON files are used both to allow a high degree of configurability, and to have easily-composable test sequences.
The whole testbench revolves around a set of invariants cast in a publisher-subscriber architecture, and is so flexible that performing hardware-in-the-loop tests just required a low-cost hardware interface and some glue logic.
We will share our experience with the different tools adopted and the issues we have encountered in our journey.

Speaker: Roberto Rigamonti (HES-SO/HEIG-VD)

09:25 Practical Methods for Functional Verification

Functional verification is a cornerstone of successful design, yet its complexity often poses significant challenges. In this presentation, we’ll explore some of the key verification methodologies, focusing on practical approaches that enhance efficiency and reliability. While the discussion will remain broad to resonate with a wide audience, specific topics such as testbench strategies, coverage metrics, and reuse will be examined in greater detail.

This session aims to spark conversation and share insights rather than providing all-encompassing solutions. Attendees will gain an understanding of fundamental practices, some actionable tips, and a platform to exchange ideas about overcoming common verification challenges.

Speaker: Simone Ponzio (ARM)

09:55 High Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing

Speaker: Mr Bernhard Gleissner (proDesign)

10:25 → 10:55 Coffee Break

10:55 → 11:35 Verification: 3

10:55 Why Your Team Should be using VHDL + OSVVM for Verification

Developing and deploying a verification methodology is costly and time consuming. Going without one is even more costly due to bugs escaping into production hardware systems.

Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM. Yet OSVVM is easier as it allows any VHDL engineer to write VHDL testbenches, test cases, and verification components for both simple unit/RTL level tests and complex, randomized full chip or system level tests.

With OSVVM you get transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co-simulation with software, test automation, scripts, and a comprehensive set of test reports.

This presentation examines the benefits of using OSVVM on your projects.

Speaker: Jim Lewis (SynthWorks)

11:35 → 13:05 Conclusions

11:35 Summary of FDF2025 and Awards

11:55 Closing Remarks