ACES 2018 - Sixth Common ATLAS CMS Electronics Workshop for LHC Upgrades
This workshop will be dedicated to electronic issues for upgrades, focusing on subjects where common features or developments are likely. Developments for upgrades for proton-proton and heavy ion running for Phase I and for high luminosity LHC (HL-LHC) will be included.
The following main areas will be covered:
- Front-end electronics developments for Phase I and HL-LHC
- Electronics systems for triggering at Phase I and HL-LHC, including level-1 tracking trigger and the use of modular electronics standards such as xTCA
- Electronics systems for DAQ and DCS at HL-LHC
- High precision timing measurement and clock distribution systems
- Optical and electrical links
- Power distribution and low power design techniques
- IC technologies and radiation hardness issues
- Progress on upgrades for HL-LHC
The oral presentations will be made by invitation. A poster session will be organised for which abstracts will have to be submitted on the indico page. More details can be obtained in contacting a member of the Programme Committee:
- Didier Contardo (LYON)
- Kevin Einsweiler (LBL)
- Philippe Farthouat (CERN)
- Cristina Fernandez (CIEMAT)
- Alex Grillo (UCSC)
- Magnus Hansen (CERN)
- Jeroen Hegeman (CERN)
- Oliver Kortner (MPI)
- Francesco Lanni (BNL)
- Alessandro Marchioro (CERN)
- Arno Straessner (DRESDEN)
- Francois Vasey (CERN)
- Administrative assistance provided by Evelyne Dho (CERN)
Registration is free (except for the conference dinner), but participants must register online before
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Posters (from Tuesday am to Thursday pm) 80/1-001 - Globe of Science and Innovation - 1st Floor
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1
First-Level Muon Track Trigger for Future Hadron Collider Experiments
Single muon triggers are crucial for the physics programmes at hadron collider experiments. The poster presents the concept for a novel muon trigger system, which exploits data from precision chambers like drift-tube chambers. Two example implementations are provided: the future muon trigger of the ATLAS experiment at the HL-LHC and the muon trigger of the baseline detector for the FCC-hh. A detailed description of fast-track reconstruction algorithms is also provided. The baseline system is based on the use of modern FPGA technology with an embedded microprocessor for floating point operations (System-on-Chip).
Speaker: Davide Cieri (Max-Planck-Institut fur Physik (DE)) -
2
Proposed Phase II ELMB for MDT Upgrade
A new ELMB (called ELMB2) is proposed for the Phase II MDT composed of new CAN bus circuitry and microprocessor replace the existing ELMB. Additionally, the current connection of the ELMB to the CSM for front-end voltage and temperature monitoring will be replaced with SCA connections to the DAQ system. The initialization of the CSM and mezzanines will also utilize the SCA connections to the front-end which will decouple the startup and recovery of the MDT from the DCS system.
Speaker: Jay Chapman (University of Michigan (US)) -
3
Optical transmitter (MTx+) and transceiver (MTRx+)
We present an optical transmitter (MTx+) and transceiver (MTRx+) based on LC TOSA and ROSA. The transmitter uses a VCSEL driver (LOCld65) of the 65 nm CMOS technology. LOCld65 is tested up to 14 Gbps. The receiver uses the ROSA/GBTIA for the moment. The electrical connector is the same as that of a SFP+. Both MTx+ and MTRx+ receive multimode fibers with the standard LC connector. The module is 6 mm in height and can be panel or board mounted. Measurement results will be present. MTx+ and MTRx+ with evaluation boards can be obtained for further development.
Speaker: Jingbo Ye (Southern Methodist University, Department of Physics) -
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The PiLup board: functionality, performances and potential application.
The PiLup board has been designed by INFN and University of Bologna for a possible use in the framework of the ATLAS TDAQ system. As an improved version of the ROD for the ATLAS Pixel Read-out, it hosts two Xilinx FPGAs: A Kintex-7 featuring high throughput and heavy data-processing capability, and a Zynq-7000 equipped with an embedded System-On-Chip. The functionality and the performances of the more up-to-date prototype will be described. As an example of potential application, tests to interface a RD53 pixel emulator and the ATLAS Felix board will be shown.
Speaker: Dr Riccardo Travaglini (INFN, Bologna (IT)) -
5
The ITk Strips Powerboard (v2) for The ATLAS Barrel
The upgrade of the ATLAS silicone strip detector (ITk Strips), for the HL-LHC will employ a parallel powering scheme for the bias high voltage and the low voltage electronics power. The power on a module will be managed using the Powerboard. The Poweboard uses the bPOL12V to step the external LV from 11V to 1.5V, monitor the LV and HV currents, disable power and monitor the temperature. The last three tasks are accomplished using the AMAC chip. This poster will present the design of Powerboard v2, initial test results and the plans for the production of the O(10,000) required Powerboards.
Speaker: Karol Krizka (Lawrence Berkeley National Lab. (US)) -
6
Serial powering testing with the 2.0A Shunt-LDO regulator of the RD53A pixel readout chip
The HL-LHC ATLAS and CMS pixel detectors will be powered using a serial powering scheme, where a constant current will be provided to a chain of pixel modules powered in series. This scheme is based on the design of a Shunt-LDO regulator that has been integrated on the new RD53A prototype pixel readout chip. Two Shunt-LDO regulators, one per power domain, are used to provide the required voltages while shunting any extra provided current. This poster presents results on the characterization of the 2.0A Shunt-LDO regulator and testing of the new RD53A pixel chips serially powered.
Speaker: Dominik Koukola (Vienna University of Technology (AT)) -
7
AREUS - a software framework for ATLAS Readout Electronics Upgrade Simulation
The ATLAS Readout Electronics Upgrade Simulation framework (AREUS) is a detailed simulation of the LAr calorimeter readout chain, used to find optimal solutions for the analog and digital processing of the detector signals.
Simulated pulse shapes take into account effects of electronics noise and of pile-up events. Analog-to-digital conversion, gain selection and digital signal processing are modeled at bit precision, including digitization noise and detailed electronics effects. Signal processing techniques can be optimized with respect to physics parameters like reconstructed energy and signal time in each channel. Trigger and object reconstruction algorithms can be integrated in the optimization process.Speaker: Philipp Horn (Technische Universitaet Dresden (DE)) -
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Redesign of the ATLAS hadronic Tile Calorimeter read out link and control board (Daughterboard) for the Phase-2 upgrade heading towards the High Luminosity Large Hadron Collider.
The Daughterboard (DB) interfaces the front-end and off-detector electronics. The newest revision migrated from two QSFPs to four SFP+ modules operating at: $4 \times 9.6$ $Gbps$ uplinks handled by two Kintex Ultrascale+ FPGAs and $2 \times 4.8$ $Gbps$ downlinks handled by two GBTxs. The DB provides continuous high-speed readout of digitized PMT samples through the uplink, and receives configuration, control and LHC synchronized timing through the downlink. TMR, FEC and CRC strategies, plus a double redundant design, aimed to virtually eliminate all possible single failure points and withstand damage from minimum ionizing and hadronic radiation, as well as single-event upsets.
Speaker: Mr Eduardo Valdes Santurio (Stockholm University (SE)) -
9
Silicon photonic wavelength division multiplexed high-speed links
We present our recent developments on an optical wavelength division multiplexed data transmission system. The nearly completed link demonstrator aims for a data rate of 4x10 Gb/s with the potential to scale the data rate up into the terabit-per-second range. Key component is a silicon-photonic chip with monolithically integrated, active and passive photonic components and circuits, whose characteristics will be shown.
Speaker: Dr Marc Schneider (Karlsruhe Institute of Technology) -
10
High Precision Online Luminosity Measurement using the CMS Phase 2 Upgrade of the Inner Tracker
The High-Luminosity LHC poses a challenge to the luminosity measurement accuracy, creating the need for the development of a new high precision online luminosity measurement system at CMS, using radiation hard detector technologies.
This work investigates the exploitation of the Tracker Endcap Pixel Extension (TEPX) for online luminosity measurement. In addition to the 750 kHz L1 physics trigger, an extra 75 kHz of trigger bandwidth from the TEPX will be allocated for luminosity. This accounts for about 110 Gb/s of acquired data that need processing in a dedicated back end system, using real-time implementations of algorithms for luminosity measurement.Speaker: Mr Alexander Ruede (CERN/KIT-IPE) -
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The Drift Tubes Test Stand for Phase-2 Upgrade
In view of the installation of a prototype of the Phase-2 on-detector electronics during the long shutdown of LHC in 2018, a demonstrator of the full trigger and readout chain was built in the CMS site.It consists of a DT (Drift Tubes) chamber equipped with a single FPGA hosting 138 TDCs with 1ns resolution that timestamp the hits collected from the frontend analog discriminators. The hits are then moved through high-speed links (10Gbps) towards the backend that is responsible for buffering the data and trigger generation.
Speaker: Andrea Triossi (Centro de Investigaciones Energéti cas Medioambientales y Tecno) -
12
AM07: Characterization of the Novel Associative Memory Chip Prototype Designed in 28 nm CMOS Technology for High Energy Physics and Interdisciplinary Applications
In the future years, luminosity, centre-of-mass energy of the proton-proton collisions at LHC will be strongly increased. Hence, next trigger system requires more challenging AM chips, with higher processing capability, lower power consumption, and higher memory density.
This work describes the characterization work on the first prototype (AM07) of these new generation 28 nm AMchips. Characterization results confirm the chip functionality up to 200 MHz as expected in simulation. With respect to the 65 nm AM06 chip, we achieved interesting results: we reduced the power consumption by a factor of 1.7 and the silicon area by a factor of 2.9.
Speaker: Giacomo Fedi (Universita & INFN Pisa (IT))
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Upgrades Overview 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Magnus Hansen (CERN)
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WelcomeSpeaker: Magnus Hansen (CERN)
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ATLAS Upgrades PlansSpeaker: Kevin Frank Einsweiler (University of California Berkeley (US))
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CMS Upgrades PlansSpeaker: Didier Claude Contardo (Centre National de la Recherche Scientifique (FR))
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LHCb Upgrades PlansSpeaker: Ken Wyllie (CERN)
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10:30
Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor
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IC Technology 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Francois Vasey (CERN)
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Total Ionizing Dose effects on 28nm CMOS TechnologySpeaker: Christian Enz (EPFL)
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Plans for the evaluation of the TID tolerance in 65nm and belowSpeaker: Federico Faccio (CERN)
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Difficulties in Designing in Advanced TechnologiesSpeaker: Bertrand Generret
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Serial Links Beyond 10 GbpsSpeaker: Paulo Rodrigues Simoes Moreira (CERN)
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12:35
Lunch
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High Speed Links 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Philippe Farthouat (CERN)
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23
Versatile Link and GBT Chipset Production: Status, Issues Encountered, and Lessons LearnedSpeaker: Lauri Juhani Olantera (CERN)
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A User View about the Usage of the GBT and VLSpeaker: Torsten Alt (Johann-Wolfgang-Goethe Univ. (DE))
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Versatile Plus Status and PlansSpeaker: Francois Vasey (CERN)
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High Speed Links on low Mass CablesSpeaker: Leyre Flores Sanz De Acedo (University of Glasgow (GB))
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16:00
Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor
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Timing 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Francesco Lanni (Brookhaven National Laboratory (US))
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28
Proposed Timing Detectors for ATLAS and CMSSpeaker: Lindsey Gray (Fermi National Accelerator Lab. (US))
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29
New Common Project on Precision TimingSpeaker: Sophie Baron (CERN)
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Current Experience with Precision Timing DistributionSpeaker: Jeroen Hegeman (CERN)
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31
Current TTC Systems and TTC-PON UpgradeSpeaker: Eduardo Brandao De Souza Mendes (CERN)
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TDAQ & DCS 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Jeroen Hegeman (CERN)
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Status and Plans for the Replacement of the ELMBSpeaker: Kamil Szymon Nicpon (CERN)
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PCIe40: A Common Readout Board for LHCb and ALICESpeaker: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
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34
Overview of the DAQ Architectures of ATLAS & CMSSpeaker: Giovanna Lehmann Miotto (CERN)
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Hardware Based Track Finding & Triggering at HL-LHCSpeaker: Mark Pesaresi (Imperial College (GB))
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10:30
Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor
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Detectors Upgrades 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Alessandro Marchioro (CERN)
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36
Status and Plans of RD53Speaker: Flavio Loddo (Universita e INFN, Bari (IT))
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37
Overview of the Pixel Detectors UpgradesSpeaker: Timon Heim (University of California Berkeley (US))
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Overview of the ASIC Developments for the Outer TrackersSpeaker: Davide Ceresa (CERN)
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Overview of the Hybrids Developments and Modules Assembly for Outer TrackersSpeaker: Craig Anthony Sawyer (Science and Technology Facilities Council STFC (GB))
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13:00
Lunch
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Detectors Upgrades 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Didier Claude Contardo (Centre National de la Recherche Scientifique (FR))
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Monolithic Pixel DevelopmentsSpeaker: Thanushan Kugathasan (CERN)
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Readout of the CMS High Granularity DetectorSpeaker: Paul Michael Rubinov (Fermi National Accelerator Lab. (US))
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Overview of the Calorimeters Readout UpgradesSpeaker: Arno Straessner (Technische Universitaet Dresden (DE))
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Preamplifier/Shapers & ADC for CalorimetersSpeaker: Philippe Schwemling (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
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16:00
Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor
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Detectors Upgrades & Reliability 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Cristina Fernandez Bedoya (Centro de Investigaciones Energéti cas Medioambientales y Tecno)
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Overview of the Muon Readout UpgradesSpeaker: Robert Richter (Max-Planck-Institut fur Physik (DE))
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ASICs Developments for the Muon DetectorsSpeaker: Paul Aspell (CERN)
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46
Experience with the FC7 Failures (and maybe others)Speaker: Jan Troska (CERN)
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FPGAs in Radiation EnvironmentSpeaker: Tullio Grassi (Univ. of Maryland (USA))
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19:30
Workshop Dinner
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Power 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Philippe Farthouat (CERN)
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Common Powering Requirements for CMS and Atlas Tracker Upgrades and First ProposalsSpeaker: Vincent Bobillier (CERN)
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Power Requirements and Developments for CalorimetersSpeaker: Sergei Lusin (University of Wisconsin Madison (US))
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51
Development for ATLAS New Small Wheel and Plans for Upgrade of Muon Power SuppliesSpeaker: Agostino Lanza (Universita and INFN (IT))
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Serial Powering for Pixel UpgradesSpeaker: Stella Orfanelli (CERN)
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11:00
Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor
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ATCA infrastructure 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Arno Straessner (Technische Universitaet Dresden (DE))
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Counting Rooms Constraints and Cooling StudiesSpeaker: Claudio Bortolin (CERN)
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Status of the xTCA Common Project, Procurement Framework for ATCA Shelves, Power Supplies and IPMCsSpeaker: Julian Maxime Mendez (CERN)
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12:30
Lunch
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ATCA infrastructure 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Arno Straessner (Technische Universitaet Dresden (DE))
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55
Overview of ATCA Boards Developments in ATLAS for phase-1Speaker: Stefano Veneziano (INFN e Università Roma Sapienza)
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Overview of ATCA Boards Developments in ATLAS and CMS for Phase-2Speaker: Eric Shearer Hazen (B)
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Using System-on-Chip to control ATCA BoardsSpeaker: Ralf Spiwoks (CERN)
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Wrap-up & Discussion
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16:00
Coffee break 80/1-001 - Globe of Science and Innovation - 1st Floor
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Close Out 80/1-001 - Globe of Science and Innovation - 1st FloorConvener: Magnus Hansen (CERN)
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