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Philippe Farthouat (CERN)26/09/2011, 14:00Oral
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Dr Markus Friedl (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)26/09/2011, 14:15Oral
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Jörg Schmiedmayer (Vienna University of Technology)26/09/2011, 14:30Oral
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Helmut Rauch (Austrian Academy of Sciences)26/09/2011, 14:45Oral
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Christian Fabjan (ÖAW-HEPHY & University of Technology, Vienna)26/09/2011, 15:00OralParticle Physics in Austria is diversifying. The accelerator-based experimental efforts are presently being carried out at LHC (ATLAS and CMS) and Belle/ Belle II at KEK. Hadron physics, with emphasis on perturbative QCD studies are being pursued at several research facilities. Recently a major astrophysics and astroparticle physics programme has been launched at Innsbruck. Exciting new...Go to contribution page
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Manfred Jeitler (Institut fuer Hochenergiephysik (HEPHY)-Oesterreichische Akadem)26/09/2011, 15:30There are a couple of institutes in Austria dealing with particle physics in various aspects, and most of them also have R&D programs for instrumentation. These institutes belong to universities or the Austrian Academy of Sciences, and the field of research ranges from astroparticle physics to nuclear physics. This presentation will give a brief overview of the institutes and their electronics...Go to contribution page
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Dr Christoph Posch (Austrian Institute of Technology GmbH)26/09/2011, 16:30Despite all the impressive progress made during the last decades in the fields of information technology, microelectronics and computer science, artificial sensory and information processing systems are still much less effective in dealing with real-world tasks than their biological counterparts. Even small insects still outperform the most powerful computers in routine functions involving...Go to contribution page
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Dr Rainer Minixhofer (Austriamicrosystems AG)26/09/2011, 17:15OralAustriamicrosystems as a globally acting, specialty semiconductor manufacturer with headquarters in Unterpremstätten, Austria, is a nucleation point for a lot of leading edge research in the semiconductor field. With its foundry services and “all-under-one-roof” offers, the company has a long history in providing open access to specialty analog semiconductor processes for the past 3 decades....Go to contribution page
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Satoko Friedl26/09/2011, 18:00The city of Vienna was essentially founded by the ancient Romans. In the late middle ages, it became the capital of the Habsburg Empire, and consequently grew in size and importance. Even though there are some Roman excavations, most of the architectural heritage originates from the monarchy. In particular, the turn of the 19th to 20th centuries was undoubtedly a peak in many aspects of arts...Go to contribution page
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Dr Peter Fischer (Physikalisches Institut)27/09/2011, 09:00The FAIR facility, which is being constructed at GSI, Darmstadt, Germany, will provide anti proton and ion beams with unprecedented intensity and quality. Several new or upgraded experiments will study the detailed structure of nuclei, nuclear matter, quark-gluon plasma, and much more. The very high track densities and the lack of fast triggers necessitates self triggered detector readout...Go to contribution page
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Giovanni Mazza (INFN sez. di Torino, Italy)27/09/2011, 09:50The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector. The ASIC will provide both the time and amplitude informations (via the Time over Threshold technique) of the incoming particle. ToPiX will consist of a matrix of 116x110 cells with a pixel size of 100x100 um2, the column readout logic and two 311 Mbit/s serializers. A reduced...Go to contribution page
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John Coughlan (STFC Rutherford Appleton Laboratory)27/09/2011, 09:50The Front End Module (FEM) is a custom on-detector FPGA based digital data acquisition card for the Large Pixel Detector (LPD) currently under construction for the European X-ray Free Electron Laser (XFEL) facility in Hamburg. In normal XFEL operation the LPD detector will generate 10 GBytes/sec of sparsified data for every one mega-pixel of sensor area. Data processed by the FEM is...Go to contribution page
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Mr Pablo Fernandez Carmona (CERN)27/09/2011, 10:15In order to achieve the required levels of luminosity in the CLIC linear collider, mechanical stabilization of quadrupoles to the nanometre level is required. The paper describes a design of hybrid electronics combining an analog controller and digital communication with the main machine controller. The choice of local analog control ensures the required low latency while still keeping...Go to contribution page
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Dr Vladimir Zivkovic (NIKHEF Institute)27/09/2011, 10:15The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the merits imposed by the LHC pixel detectors. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within Insertable B-Layer (IBL). As the IBL schedule was pushed significantly forward, a quick and efficient plan needed to be devised for...Go to contribution page
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Mark Raymond (Imperial College London)27/09/2011, 11:00A 130 nm CMOS chip has been designed for silicon microstrip readout at the SLHC. The CBC has 128 channels, and utilises a binary un-sparsified architecture for chip and system simplicity. It is designed to read out signals of either polarity from short strips (capacitances up to ~ 10 pF) and can sink or source sensor leakage currents up to 1 microamp. Details of the design and measured...Go to contribution page
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Mr Francis Anghinolfi (CERN)27/09/2011, 11:00The ATLAS Forward Detectors for Measurement of Elastic Scattering and Luminosity (ALFA) have been fully installed during the 2010-2011 winter LHC shutdown. ALFA consists of 8 mini tracking detectors made of 20 planes of scintillating fibers placed in Roman Pot units near the beam and 240m away on both sides of the interaction point. The front-end electronics sit directly on top of the PMTs and...Go to contribution page
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Dr Hubert Kroha (Max-Planck-Institut fuer Physik, Munich)27/09/2011, 11:25We discuss the development and performance of a new analogue and digital readout chip for the Monitored Drift-Tube (MDT) chambers of the ATLAS muon spectrometer using the IBM 130 nm CMOS 8RF-DM technology. The 4-channel Amplifier-Shaper-Discriminator (ASD) chip was designed to match the analogue performance of the presently used device in 0.5 micron Agilent technology which is now obsolete....Go to contribution page
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Mr Patrick Vogler (ETH Zurich)27/09/2011, 11:25Within the FACT project, we construct a new type of camera based on Geiger-mode avalanche photodiodes (G-APDs). Compared to photomultipliers, G-APDs are more robust, need lower operation voltage and have the potential of higher efficiency and lower cost, but were never tested in the harsh environments of Cherenkov telescopes. The FACT camera consists of 1440 G-APD pixels and readout channels,...Go to contribution page
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Dr Matteo Beretta (Istituto Nazionale Fisica Nucleare (INFN) - Laboratori Nazionali di Frascati)27/09/2011, 11:50We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. We have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic. The customized design maximizes the pattern density, minimizes the power consumption and...Go to contribution page
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Dr Matthew Noy (CERN)27/09/2011, 11:50The architecture and characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector (HPD) will be presented. This detector must perform time stamping to 200 ps (RMS) or better, provide 300 µm pitch position information and operate with a dead time of 1 % or less for 800 MHz−1 GHz beam rate. The demonstrator HPD Assembly comprises a readout chip with a test column...Go to contribution page
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Nicolas Dumont Dayot (LAPP-Laboratoire d'Annecy-le-Vieux de Physique des Particules ()27/09/2011, 12:15In the context of the LHC upgrades, a new Read-Out Driver (ROD) board for the ATLAS LAr calorimeter is being developed. xTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and is a serious candidate for future readout systems. We will present our current developments to master ATCA and to integrate a large number of very high speed links (96...Go to contribution page
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Mr Eduardo Picatoste Olloqui (Universidad de Barcelona)27/09/2011, 12:15An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. The circuit is based on a two fully differential interleaved channel with a first amplifier stage and a switched integrator. It offers an electronically cooled input termination at the input to achieve the stringent noise requirements. Compared to previous designs, its novelty relies in the use of...Go to contribution page
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Veljko Radeka (Brookhaven National Laboratory)27/09/2011, 14:00SystemsOralThe Liquid Argon Time Projection Chamber (LAr TPC) technology offers extraordinarily precise event reconstruction and particle identification, as well as scalability to very-large detectors. To go beyond the sensitivities of current experiments for neutrino physics and proton decay, the next generation of liquid argon TPCs are envisioned to be in the range of 20-100 kton. Detectors of this...Go to contribution page
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Mr Stefano Michelis (CERN)27/09/2011, 14:50In view of the upgrade of the LHC experiments, we are developing custom DC/DC converters for a more efficient power distribution scheme. Two new prototypes (AMIS3 and AMIS4) have been integrated in ASICs in the selected 0.35um commercial high voltage technology that has been successfully tested for all radiation effects: TID, displacement damage and Single Event Burnout. While AMIS3...Go to contribution page
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Mr Jakub Moron (AGH University of Science and Technology)27/09/2011, 14:50The design and measurements results of low power Phase-Locked Loop (PLL) prototype for applications in particle physics detectors readout systems are presented. The PLL is designed and fabricated in 0.35~$\mu$m CMOS technology. First measurements show that the ASIC is fully functional and generates clock in the frequency range 380MHz-1.1GHz. The PLL power consumption at 1~GHz is about 4.5...Go to contribution page
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Ms Nathalie SEGUIN-MOREAU (OMEGA / IN2P3 - CNRS)27/09/2011, 15:15SKIROC (Silikon pin Kalorimeter Integrated ReadOut Chip) is the very front end chip designed for the readout of the Silicon PIN diodes foreseen for the Electromagnetic CALorimeter (ECAL) of the future International Linear Collider. The very fine granularity of the ILC calorimeters implies a huge number of electronics channels (82 millions) which is a new feature of “imaging”...Go to contribution page
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Laura Gonella (University of Bonn)27/09/2011, 15:15The Shunt-LDO regulator is a new regulator concept which combines a shunt and a Low Drop-Out (LDO) regulator. Designed to match the needs of serially powered detector systems, it can also be used as a pure LDO regulator for general application in powering schemes requiring linear regulation. The flexibility of the design makes the Shunt-LDO a good candidate for use in the powering schemes...Go to contribution page
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Mr Peter Phillips (Particle Physics)27/09/2011, 15:40The engineering challenges related to the supply of electrical power to future large scale detector systems are well documented. Two options remain under active study in our community, namely serial powering and the use of DC-DC convertors. Whilst clearly different in detail, both have the potential to increase the efficiency of the powering system. The ATLAS Upgrade Strip Tracker...Go to contribution page
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Dr David Gascon (Universidad de Barcelona)27/09/2011, 15:40A wideband current mode preamplifier with 16 bits dynamic range (DR) is presented. It has been designed for the cameras of the Cherenkov Telescope Array (CTA). A novel current division scheme at the very front end part of circuit splits the input current in to two scaled currents which are connected to independent current mirrors. The mirror of the high gain path comprises a saturation control...Go to contribution page
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Kostas Kloukinas (CERN)27/09/2011, 16:30
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Markus Joos (CERN)27/09/2011, 16:30
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Bruno Soares Gonçalves (Instituto de Plasmas e Fusão Nuclear)27/09/2011, 16:35
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Wojciech Bialas (CERN)27/09/2011, 16:35
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Vladimir Zivkovic (NIKHEF Institute)27/09/2011, 16:45
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Magnus Hansen (CERN)27/09/2011, 16:55
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Massimo Manghisoni (Università degli Studi di Bergamo)27/09/2011, 17:00
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Eric Shearer Hazen (Department of Physics-Boston University)27/09/2011, 17:15
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Kostas Kloukinas (CERN)27/09/2011, 17:20
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Jorgen Christiansen (CERN)27/09/2011, 17:30
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Gregory Michiel Iles (Imperial College Sci., Tech. & Med. (GB))27/09/2011, 17:30
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Dr Sandro Bonacini (CERN)27/09/2011, 17:35
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Markus Joos (CERN)27/09/2011, 17:40
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Ken Wyllie (CERN)27/09/2011, 17:45
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Jean-Pierre Cachemiche (Centre de Physique de Particules de Marseille (CPPM)-Faculte de), Vincent Bobillier (CERN)27/09/2011, 17:50
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Denis Fougeron (Universite d'Aix - Marseille II (FR))27/09/2011, 17:55
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Philippe Farthouat (CERN)27/09/2011, 18:05
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Filipe Pereira Alves De Sousa (FEUP Faculdade de Engenharia (FEUP)-Universidade do Porto), Francis Anghinolfi (CERN)27/09/2011, 18:05
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Jano Gebelein (Kirchhoff-Institut fuer Physik (KIP)-Ruprecht-Karls-Universitae)27/09/2011, 18:15
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Markus Joos (CERN)27/09/2011, 18:25
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Dr Steve Trimberger (Xilinx Research Labs)28/09/2011, 09:00For more than twenty-five years, programmable logic has effectively leveraged Moore’s law to provide steadily increasing device performance, capacity and features, while lowering the cost dramatically. We know that microprocessor power consumption issues forced a radical change in those devices, shifting from faster clock rate to multi-core. Is the same happening to programmable logic? ...Go to contribution page
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Dr Jinyuan Wu (FERMILAB)28/09/2011, 09:50A low-power time-to-digital convertor (TDC) for an application inside vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to...Go to contribution page
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Dr Carolina Gabaldon Ruiz (CERN)28/09/2011, 09:50The ATLAS trigger system is responsible for reducing the event rate, from the design bunch-crossing rate of 40 MHz, to an average recording rate of 200 Hz, by selecting signal-like events out of the extremely large background. The ATLAS trigger is designed in three levels. The first-level (L1) is implemented in custom-built electronics, the two levels of the high level trigger (HLT) are...Go to contribution page
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Mr Cahit Ugur (GSI Helmholtzzentrum für Schwerionenforschung)28/09/2011, 10:15A 32-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine-time calculations are achieved by using the dedicated carry-chain lines. A low latency (30 ns) encoder handles the conversion of the fine time measurement. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and...Go to contribution page
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Marian Krivda (University of Birmingham, UK)28/09/2011, 10:15The ALICE trigger system in the experimental cavern processes information from triggering detectors at 3 hardware levels in p-p and Pb-Pb collisions. The performance of the system exceeds the specification and many automatic functions have been developed to facilitate work in the control room. The hardware is permanently monitored, and around 1200 counters, with considerable built-in...Go to contribution page
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Mr Hervé Le Provost (IRFU-CEA)28/09/2011, 11:00This contribution reports on the read-out system of the future KM3NeT undersea network of several thousands of synchronized optical detecting nodes. Each node embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and DAQ software designed within the ICE middleware framework resulting in a highly flexible,...Go to contribution page
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Dr Pamela Klabbers (University of Wisconsin)28/09/2011, 11:00We present a design for the Phase-1 upgrade of the CMS calorimeter trigger system composed of FPGAs and Multi-GBit/sec links that adhere to the micro-TCA crate Telecom standard. The upgrade calorimeter trigger will implement algorithms that create collections of isolated and non-isolated electromagnetic objects, isolated and non-isolated tau objects and jet objects. The algorithms are...Go to contribution page
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Mr Olivier Bourrion (Laboratoire de Physique Subatomique et de Cosmologie (LPSC)-Univ)28/09/2011, 11:25Directional detection of non-baryonic Dark Matter requires 3D reconstruction of low energy nuclear recoils tracks. A gaseous micro-TPC matrix, filled with either 3He, CF4 or C4H10 has been developed within the MIMAC project. A dedicated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic...Go to contribution page
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Dr Hubert Kroha (Max-Planck-Institut fuer Physik, Munich)28/09/2011, 11:25The upgrade of the LHC towards higher luminosity requires improved L1 trigger selectivity in order to keep the maximum total trigger rate at about 100 kHz. In the L1 muon trigger system this necessitates an increase of the pT threshold for single muons. Due to the limited spatial resolution of the trigger chambers, however, the selectivity for tracks above about 20 GeV/c is insufficient for an...Go to contribution page
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Dr Gregory Michiel Iles (Imperial College Sci., Tech. & Med.)28/09/2011, 11:50A novel approach to first-level hardware triggering has been studied and a prototype system built. Calorimeter trigger primitive data (~5 Tb/s) are reorganised and time-multiplexed so that a single processing node (FPGA) may access the data corresponding to the entire detector for a given bunch crossing. This provides maximal flexibility in the construction of new trigger algorithms, which...Go to contribution page
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Mr Harold Yepes Ramirez (IFIC-ANTARES)28/09/2011, 11:50ANTARES is the First full operational and the largest neutrino telescope in the Northern hemisphere. Located in the Mediterranean Sea, it consists of a 3D array of 885 photomultiplier tubes (PMTs) arranged in 12 detection lines (25 storeys each), able to detect the Cherenkov light induced by upgoing relativistic muons produced in the interaction of high energy cosmic neutrinos with the...Go to contribution page
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Mr Carlos David Llorens (Universidad Politécnica de Valencia representing the KM3NeT Consortium)28/09/2011, 12:15We describe the sound emission control board of an acoustic positioning system necessary to triangulate flexible optical detection lines in the KM3NeT future deep sea neutrino telescope. Such a positioning system must log the positions of optical sensors for Cherenkov radiation emitted in sea water to precisions of ~10cm, over a >1 km3 instrumented volume. This will be achieved by acoustic...Go to contribution page
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Janos Ero (Institut fuer Hochenergiephysik (HEPHY))28/09/2011, 12:15The present CMS Trigger Drift Tube Track Finder Unit was designed between 2003 and 2006. The long Shutdown planned for 2016-2017 gives an opportunity to perform a basic upgrade of this system. The rapid technology development allows us to redesign the electronic groups and structures in such a way that a smaller, more reliable facility with easier control and reduced maintenance can be built.Go to contribution page
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Sami Vaehaenen28/09/2011, 14:00Vertical (3D) integration using Through Silicon Vias (TSV) is gaining lot of attention within electronics industry. 3D integrated structures should enhance electrical performance of electronic devices, boost up device miniaturization, and enable new designs and stacks of device layers made with heterogeneous technologies. For pixel detectors, 3D integration using TSVs in combination with...Go to contribution page
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Mr Jan Sammet (RWTH Aachen University)28/09/2011, 14:50Around 2016, the pixel detector of the CMS experiment will be upgraded. The amount of current that has to be provided to the front-end electronics is expected to increase by a factor of two. Since the space available for cables is limited, this would imply unacceptable power losses in the available supply cables. Therefore it is foreseen to place DC-DC converters close to the front-end...Go to contribution page
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Dr Hung Pham (DRS-IPHC (IReS), University of Strasbourg, CNRS-IN2P3)28/09/2011, 14:50ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7µm pixel pitch, providing a sensitive area of ~3.8cm². Based on the sensor designed for the EUDET beam telescope, the device is a binary output sensor with integrated zero suppression circuitry featuring a 320...Go to contribution page
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Dr Sergei Lusin (CERN)28/09/2011, 15:15The electronic systems of modern high-energy physics detectors are often built with electromagnetic compatibilty issues as an important part of the requirements driving the design of the detector. The CMS experiment at CERN has an appreciable amount of electronic infrastructure not usually found in previous generations of high-energy physics detectors. Over more than a year of CMS...Go to contribution page
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Filipe Pereira Alves De Sousa (Univ. do Porto-Unknown-Unknown)28/09/2011, 15:15Electronic circuits submitted to high doses of radiation are prone to functional failures. Due to the high cost of currently available radiation hard technologies, alternative design approaches, resort to available, yet less costly and higher performance, commercial CMOS technologies. To improve radiation tolerance within these technologies specific design and layout methodologies are...Go to contribution page
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Wieslaw Iwanski (CERN/INP PAN Cracow)28/09/2011, 15:40The Atlas infrastructure, including also power distribution, has been built from scratch for the purpose of the LHC experiment. This provided more freedom and helped to deploy modern solutions. It this document will be presented examples of different approaches to implement electrical distribution. Ways to achieve the expected level of control will be demonstrated, statistics presenting usage...Go to contribution page
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Mr Guido Magazzu (UCSB/INFN)28/09/2011, 15:40A radiation tolerant integrated circuit for the distribution of clock, trigger and controls in the Front-End electronics of the CMS End-Cap Muon detector has been developed in the IBM CMOS 130nm technology. The circuit houses transmitter and receiver interfaces to serial links implementing the FF-LYNX protocol that allows the integrated transmission of triggers and data frames with different...Go to contribution page
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Magnus Hansen (CERN), Philippe Farthouat (CERN)28/09/2011, 16:30
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Tobias Flick (Bergische Universitaet Wuppertal (DE))28/09/2011, 16:30
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Maria Cristina Esteban Lallana (Instituto Tecnologico de Aragon)28/09/2011, 16:35
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Ken Wyllie (CERN)28/09/2011, 16:40
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192. CMS Tracker: Status of the optical system / optical system upgrades and associated developmentsDr Jan Troska (CERN)28/09/2011, 16:55
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Michal Bochenek (Conseil Europeen Recherche Nucl. (CERN))28/09/2011, 16:55
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Alexander Singovski (University of Minnesota (US))28/09/2011, 17:10
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Stefano Michelis (CERN)28/09/2011, 17:15
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Eric Shearer Hazen (Boston University (US))28/09/2011, 17:25
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Georges Blanchot (CERN), Stefano Michelis (CERN)28/09/2011, 17:35
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Stefan Simion (Universite de Paris-Sud 11 (FR))28/09/2011, 17:40
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Laura Gonella (Universitaet Bonn (DE))28/09/2011, 17:55
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Tobias Flick (Bergische Universitaet Wuppertal (DE))28/09/2011, 17:55
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Dr Jan Troska (CERN)28/09/2011, 18:00
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Philippe Farthouat (CERN)28/09/2011, 18:15
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Tiankuan Liu (Southern Methodist University (US))28/09/2011, 18:15
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28/09/2011, 18:30
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Dr Eric CASSAN (IEF - Univ. Paris Sud Orsay)29/09/2011, 09:00Silicon photonics has received a growing interest in the last years due to the possibility to realize strongly miniaturized photonic circuits using CMOS-compatible techniques and processes, and to the possible forthcoming integration of optical functions with electronics on the same chips. Passive and active devices have been demonstrated to distribute and manipulate light using a vast panel...Go to contribution page
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Paolo Petagna (CERN)29/09/2011, 09:50Micro-channel cooling is gaining considerable attention as an alternative technique for cooling of high energy physics detectors and front-end electronics. We are evaluating this technology for future tracking devices where material budget limitations are a major concern. Micro channel cooling is currently under investigation as an option for the cooling of the NA62 Gigatracker silicon pixel...Go to contribution page
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Mr Francois Vasey (CERN)29/09/2011, 09:50The Versatile Link is a bi-directional digital optical data link operating at rates up to 4.8 Gbit/s and featuring radiation resistant low power and low mass front-end components. The system is developed in multimode or singlemode versions operating at 850nm or 1310nm wavelength respectively. It has serial data interfaces and is protocol-agnostic, but is targeted to operate in tandem with...Go to contribution page
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Mr Spyridon Papadopoulos (CERN)29/09/2011, 10:15The forthcoming increase of rate of data production and radiation levels, associated with the transition to HL-LHC, necessitates a readout link upgrade. This upgrade is also an opportunity to move to a more efficient network infrastructure and to introduce new technologies and it is in light of this that we explore the possibility of using a unified architecture based on Reflective...Go to contribution page
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Mr Michael Woods (University of California Davis)29/09/2011, 10:15The SiD collaboration is developing a Si-W sampling electromagnetic calorimeter, with anticipated application for the International Linear Collider. Assembling the modules for such a detector will involve bonding technologies for the interconnects, especially silicon detector wafer to a flex-cable readout bus attachments. We review the interconnect technologies involved, including oxidation...Go to contribution page
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Dr Anna Macchiolo (Max-Planck-Institut fuer Physik)29/09/2011, 11:00We will report on the characterization of pixel modules composed of 75 microns thick n-in-p sensors and ATLAS FE-I3 chips, interconnected via the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is employed as an alternative to the bump-bonding process. These modules have been designed as a demonstration of a very compact detector to be employed...Go to contribution page
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Dr Anthony Weidberg (Nuclear Physics Laboratory)29/09/2011, 11:00Severe problems with VCSEL reliability have been observed in ATLAS operation. ATLAS has developed the use of Optical Spectrum Analysers as a sensitive indication of VCSEL damage. These studies and detailed microscopic investigations have shown that the observed VCSEL reliability issues have been caused by moderate levels of humidity combined with the use of non-hermetic packages. Long term...Go to contribution page
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Dr Sandro Bonacini (CERN)29/09/2011, 11:25The radiation characteristics with respect to Total Ionizing Dose (TID) of a 65 nm CMOS technology has been investigated. Single transistor structures of a variety of dimensions and several basic circuits were designed and fabricated. The circuits include a 64-kbit shift-register, a 9-kbit SRAM, a ring-oscillator, a low noise preamplifier, a low-power discriminator and two 6-bit DACs with...Go to contribution page
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Mr David Hall (University of Oxford)29/09/2011, 11:25The Versatile Link (VL) project is developing a high-speed optical link for the HL-LHC. 850 nm VCSELs are more radiation-hard than 1310 nm EELs. Previous tests on multimode fibres at -25°C at 27 kGy/hr showed unacceptable radiation induced absorption. We have developed a CO2 cooling system which will be used in late June to irradiate cold fibres at low dose rates (1 kGy/hr) to the full HL-LHC...Go to contribution page
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Dr Paschalis Vichoudis (CERN)29/09/2011, 11:50We have designed and built an FPGA-based platform for users of high speed optical links in high energy physics experiments. The Gigabit Link Interface Board (GLIB) serves both as a platform for the evaluation of optical links in the laboratory as well as a triggering and/or data acquisition system in beam or irradiation tests of detector modules. The GLIB is a double width Advanced Mezzanine...Go to contribution page
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Dr Takeo Higuchi (KEK)29/09/2011, 11:50Readout and digitization electronics of upgraded B-factory detector Belle II will be located at the detector side to reduce number of analog cables. The digitized signals are transmitted out over optical serial links. The on-detector electronics is expected to suffer about 10¹² neutrons per year with kinetic energy peaking around 5 MeV. In our studies bombarding a prototype on-detector...Go to contribution page
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Ms Evangelia GOUSIOU (CERN)29/09/2011, 12:15WorldFIP is a deterministic fieldbus used in the LHC for the communication with a variety of systems. There are more than 10.000 WorldFIP agents installed all around the LHC tunnel and exposed to a complex radiation field. A new customized version of WorldFIP agents, the nanoFIP, housed in an Actel ProASIC3 FPGA, has been developed at CERN in cooperation with the industry. The paper describes...Go to contribution page
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Csaba Soos (CERN)29/09/2011, 12:15The Versatile Link common project is developing optical link architectures and components to be used for readout and control in future HL-LHC experiments. The on-detector opto-electronic module, the Versatile Transceiver (VTRx), is derived from an industry standard module type and is adapted through minimal customization to the requirements dictated by the HL-LHC-specific front-end...Go to contribution page
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165. Organic and Printed Large-area Electronics: Disruptive Technologies for Innovative ApplicationsDr Eugenio Cantatore (Eindhoven University of Technology)29/09/2011, 14:00Organic electronics is manufactured with carbon-based semiconductors that are processed at low temperature, and thus can be deployed on thin, flexible substrates like plastic foils and paper. Organic semiconductors are often available as ink-like solutions, thus high throughput fabrication of electronics using processes normally designed for graphical printing is feasible and has been the...Go to contribution page
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Dr Markus Brugger (CERN)29/09/2011, 14:45A large spectrum of equipment and electronics is exposed to radiation around the various underground areas of the CERN ‘Large Hadron Collider’ (LHC). In the current configuration, LHC alcoves equipped with commercial or not specifically designed electronics are mostly affected by the risk of ‘Single Event Effects’ (SEE), whereas electronics installed in the LHC tunnel will in the long-term...Go to contribution page
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Mr Lukas Perktold (CERN)29/09/2011, 16:00The NA62 experiment needs to provide time stamping of individual particles to 200ps-rms or better per station. Bump-bonded to the pixel sensor each ASIC serves an array of 40 columns x 45 pixels. Discriminated signals from each pixel are sent to the lower edge of the ASIC to an array of time-to-digital converters (TDCs). The outputs of 5 pixels are multiplexed together yielding a total of 9...Go to contribution page
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Mr Claudio Gotti (INFN Milano Bicocca and Università di Firenze)29/09/2011, 16:00An integrated charge sensitive preamplifier was designed in 90 nm CMOS technology. The chip is part of the R&D effort towards the upgrade of the pixel sensors of the CMS detector. It was submitted in april 2010, and was received and tested in autumn 2010. In the design of the amplifier block, a single ended structure was preferred over a differential one, in order to achieve a lower noise....Go to contribution page
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Dr Hervé Chanal (Laboratoire de Physique Corpusculaire de Clermont-Ferrand), Mr Yannick Denis Zoccarato (Institut de Physique Nucleaire de Lyon (IPNL)-Universite Claude)29/09/2011, 16:00FEAFS chip has been designed for a future sCMS Silicon Strip Tracker. Its primary function is to provide a 40 MHz selective readout of particle hits useful to establish the 100kHz hardware trigger of the experiment. To achieve this goal, the chip identifies clusters of limited number of activated strips and correlated in position in two closely superimposed sensors connected to the same chip....Go to contribution page
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Mr Maximilian Buechele (Physikalisches Institut der Albert-Ludwigs-Universitaet Freiburg)29/09/2011, 16:00The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted-clock-sampling method. A particular challenge of this algorithm is the predictable placement of the logic components and the uniform routing inside the...Go to contribution page
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Dr Riccardo Travaglini (INFN-Bologna)29/09/2011, 16:00he ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL).A new front-end ASIC has been foreseen (named FE-I4) and it will be readout with improved off-detector electronics. In particular, the new Read-Out Driver module (ROD) is a VME-based board designed to process a four-fold data throughput....Go to contribution page
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Mr Daniel Paer Erik Eriksson (Department of Physics-Stockholm University-Unknown)29/09/2011, 16:00Upgrade plans for ATLAS hadronic calorimeter (TileCal) include full readout of all data to the counting room. We are developing a possible implementation of the future readout and trigger electronics aiming at a full functional demonstrator during Phase 0, starting from an existing functional test slice assembled using a combination of prototypes and emulators. Presently the first version of...Go to contribution page
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Giovanni Mazza (INFN sez. di Torino, Italy)29/09/2011, 16:00The GigaBit Transceiver (GBT) project aims at the design of a radiation tolerant chip set for high speed optical data transmission. The chipset includes the GigaBit Laser Driver (GBLD), a radiation tolerant ASIC designed in a standard CMOS 130 nm technology. The GBLD is a laser driver designed to work to up to 5 Gb/s and capable to drive both VCSELs and some types of edge emitting lasers. The...Go to contribution page
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Jan Scheirich (Czech Technical University in Prague, Faculty of Electrical Engineering)29/09/2011, 16:00The DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor will be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. The DEPFET sensor requires switching and...Go to contribution page
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Mr Frédéric Druillole (CEA Saclay)29/09/2011, 16:00To prepare future experiment, we need to qualify new solid state detectors and gaseous TPC. From T2K experiment and GET project, we develop a small board constituted of two 64 AGET asic, a 4-channel pipeline adc and a smart commercial board called “AVNET minimodule” to sequence the acquisition and send data in TCP/IP mode through the Ethernet network. The size of the board is 15 cm x 8 cm....Go to contribution page
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Dr Yifan Yang (Université Libre de Bruxelles)29/09/2011, 16:00This talk describes a high speed ethernet-based data and clock network for applications which require an array of multiple sensor nodes distributed over distances of up to 250 m from a central hub. Speeds of up to 100 Mbit/sec and clock skew at the level of 50 ps are acheivable using commercially available network-grade twisted pair cables and low-power ethernet transceiver circuits. No...Go to contribution page
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Mr Andreas Ebling (J.G.U. Mainz)29/09/2011, 16:00The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based.\\ The LHC machine plans to bring the beam energy to the nominal value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged.\\ To cope with the...Go to contribution page
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Mr Tuomas Sakari Poikela (University of Turku / CERN)29/09/2011, 16:00We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most...Go to contribution page
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Jerôme Pibernat (CENBG/CNRS/IN2P3)29/09/2011, 16:00In experiments with radioactive beams from heavy ions facilities it is shown that active targets and TPCs experimental methods are effective means to study nuclear spectroscopy. The principle advantages are good resolution, versatility and high luminosity. To address the needs of the nuclear Physics community we are in the process of developing a Generic Electronic system for TPCs (GET) to...Go to contribution page
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Mr David Pierre Martin (Lab. Phys. Nucl. Hautes Energies (LPNHE)-Univ. P. et Marie Curi)29/09/2011, 16:00The ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%. The architecture, chosen by LSST, is based on a “Correlated Double Sampling” with a “Dual Slope Integrator” method. Many modular tests benches have been developed to qualify this chip and...Go to contribution page
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Dr Sandro Bonacini (CERN)29/09/2011, 16:00As triple well technologies became available in recent years as an option for several submicron technologies, the question of their robustness against SEU with respect to single well versions has been asked, but a systematic comparison has been missing from the literature. This work present the first systematic comparison of the sensitivity to Single Event Upsets of latch cells designed in a...Go to contribution page
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Mr FU Yunan (Institut Pluridisciplinaire Hubert Curien)29/09/2011, 16:00The paper presents a design of CMOS Pixel Sensor (CPS) using the vertical integration technology (3DIT), expected to alleviate the most essential limitations of 2D-CPS. Our objective is to develop an intelligent architecture in order to meet the requirements of the innermost layer of the International Linear Collider (ILC) vertex detector, which are particularly demanding in spatial resolution...Go to contribution page
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Mr Jens Verbeeck (K.U.Leuven), Prof. Paul Leroux (K.U. Leuven)29/09/2011, 16:00The design of a radiation tolerant configurable discrete time signal conditioning circuit in 130nm CMOS technology for use with resistive sensors like strain gauge pressure sensors is presented. The circuit is intended to be used for remote handling in harsh environments in the International Experimental Thermonuclear fusion Reactor (ITER). The design features a 1.5V differential preamplifier...Go to contribution page
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Dr Tiankuan Liu (Southern Methodist University (US))29/09/2011, 16:00In this paper we present the R&D towards cryogenic digital data links for a Liquid Argon Time Projection Chamber (LArTPC). An electrical data link with a commercial LVDS driver and a 20-meter CAT5E twisted pair can work up to 1 Gbps at liquid nitrogen temperature or 77 K. Components of a cryogenic optical data link, including a serializer ASIC, laser diodes, optical fibers, and optical...Go to contribution page
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Dr Remi Jean Noel Cornat (Laboratoire Leprince-Ringuet (LLR)-Ecole Polytechnique-Unknown)29/09/2011, 16:00Calorimeters for a future International Linear Collider developed within the CALICE collaboration will feature about 10^8 channels. A scalable control and data acquisition system was developed. Is is based on GigaEthernet and a specific serial link packing slow control, fast control and read out data. Most of the hardware and firmware components are shared among the various detectors. The...Go to contribution page
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Georges Blanchot (CERN)29/09/2011, 16:00The development at CERN of low noise DC-DC converters for the powering of front-end systems enables the implementation of efficient powering schemes for the physics experiments at the HL-LHC. Recent tests made on the ATLAS short strip tracker modules confirm the full electromagnetic compatibility of the DC-DC converter prototypes with front-end detectors. The integration of the converters in...Go to contribution page
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Dr Erdem Motuk (University College London)29/09/2011, 16:00The development of the Clock and Control (CC) hardware and firmware for the EuXFEL DAQ system is presented. The system exploits the data handling advances provided by the new telecommunication architecture standard for physics. The CC is responsible for synchronising the DAQ system to overall system timing. The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear...Go to contribution page
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Mr Martin Postranecky (Department of Physics and Astronomy, University College London)29/09/2011, 16:00ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ("DAVE"). The unit was designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP functionality, with random trigger, simple and complex deadtime, ECR, BCR etc. being generated to give exactly...Go to contribution page
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John Coughlan (STFC Rutherford Appleton Laboratory)29/09/2011, 16:00The Train Builder is an Advanced Telecom ATCA based custom data acquisition system designed to provide a common readout system for the large 2D Mega-pixel detectors presently under construction for the European-XFEL facility in Hamburg. Each detector outputs 10 GBytes/sec of raw data over multiple 10 Gbps SFP+ optical links. The Train Builder DAQ system will merge detector link image fragments...Go to contribution page
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Olivier Raymond Bourrion (Laboratoire de Physique Subatomique et de Cosmologie (LPSC)-Univ)29/09/2011, 16:00A front end ASIC has been designed to equip the µTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the “Time Over Threshold” information for each of those. This 64 digital information, sampled at a rate of...Go to contribution page
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Ivo Polak (Institute of Physics)29/09/2011, 16:00We will present some new ideas on the design of different parts of DC/DC converter which operates on Very High Frequency. I show different topologies, and its power efficiency influence, which is being achieved during design stage of 2 years project called Brahms. There are recent interesting results, but not final solution yet. The presentation is focused to the perspective of power...Go to contribution page
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Mr Dominik Przyborowski (AGH University of Science and Technology)29/09/2011, 16:00The design and measurements of 8--bits DACs based on L--2L ladder architecture are presented. The main design goals were low power consumption and low area. Such features allow using the DAC for channel parameter trimming in multichannel readout system. The PMOS and NMOS based DACs are studied in wide range of biasing conditions and for two operation modes -- as current generator and current...Go to contribution page
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Christian Neher (University of California at Davis)29/09/2011, 16:00As silicon detectors in HEP require increasingly complex assembly procedures, the availability of a wide variety of interconnect technologies provides more options for overcoming obstacles in generic R&D. I present recent progress and challenges faced in various interconnect technologies: gold stud and double gold stud bonding, deposition and bonding of indium bumps, solder ball bonding and...Go to contribution page
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Sergio Gonzalez Sevilla (DPNC, University of Geneva)29/09/2011, 16:00The Large Hadron Collider (LHC) will extend its current physics programme by increasing the peak luminosity by one order of magnitude. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker. The super-module programme is an integration concept for the barrel short-strip region of the future ATLAS tracker in which double-sided silicon micro-strip modules are...Go to contribution page
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Mr Christian Irmler (HEPHY Vienna)29/09/2011, 16:00In the Belle II SVD readout chain the analog singnals will be transmitted over long lines. This leads to signal distortion, caused by the frequency dependent transfer function of the cable and also by reflections, which occour whenever the line impedance changes. One possibility to compensate these effects is a dedicated filter at the receiver end. This presentation describes the approach to...Go to contribution page
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Mr Alan Prosser (Fermilab)29/09/2011, 16:00Modern particle detectors utilize optical fiber links to deliver event data to upstream trigger and data processing systems. Future detector systems can benefit from the development of dense arrangements of high speed optical links emerging from industry advancements in transceiver technology. Supporting data transfers of up to 120 Gbps in each direction, optical engines permit assembly of the...Go to contribution page
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Dr Nicolas Pillet (Lab. de Physique Corpusculaire (LPC))29/09/2011, 16:00The ATLAS upgrade will require more efficient electronics to fulfil the new performances expected by the experiment. Concerning the readout electronics of the Tile Calorimeter, the replacement of the 3in1 board by an integrated circuit is under study. The proposed circuit is composed of a multi-gain current conveyor, followed by shapers, an integrator for the calibration and an...Go to contribution page
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Dr Ketil Røed (CERN)29/09/2011, 16:00In the main tracking detector of ALICE, the Time Projection Chamber (TPC), an SRAM based FPGA from Xilinx is implemented in the Readout Control Unit (RCU)of the front-end electronics and controls the read out of data from the detector. This paper will present the first measurements of single event upsets in this FPGA. The results will be compared to previous simulations and discussed in light...Go to contribution page
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Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)29/09/2011, 16:00This poster describes the implementation of a flexible system for the electromagnetic calorimeter (ECAL) Off Detector (OD) electronics firmware update and the corresponding software tools designed to manage the update operation. The idea is to equip each ECAL VME64x crate with the new JTAG Distribution Board (JDB) that access XILINX and ALTERA FPGAs JTAG chains for trigger (TCC68/48) and data...Go to contribution page
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Dr Huaishen LI (IHEP, C.A.S.)29/09/2011, 16:00The upgrade of Beijing Synchrotron Radiation Facility(BSRF) need two-dimensional position-sensitive detection equipment to improve the experimental performance. New structures and new technology GEM detector, in particular, pixel-based(Pad) GEM detector, has good prospects in the domain of synchrotron radiation and high energy physics experiments for its simple structure, superior performance...Go to contribution page
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Mr Francesco Zappon (Nikhef)29/09/2011, 16:00GOSSIPO-4 is a prototype chip featuring an array of high resolution Time to Digital Converters (TDC) with a PLL control that will be taped out on the 9th of August 2011. This prototype is the successor of GOSSIPO-3 test chip and the precursor of the 65k pixel TimePix3 chip. The prototype is being developed to test a set of new features that will be used in TimePix3, including a 8 pixel...Go to contribution page
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Dr David Cussans (University of Bristol)29/09/2011, 16:00Initial tests the CBC binary readout chip connected to a sensor are presented.Go to contribution page
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Dr Pablo Vazquez Regueiro (University of Santiago de Compostela, IGFAE)29/09/2011, 16:00The Pixel Detector (PXD) of the Belle II experiment at superKEKB accelerator in Japan is based in the DEPFET technology. Two layers of 8+12 modules at a radius of 13 and 22 mm will give a spatial resolution below 10 µm. The radiation level expected in the first layer in ten years of operation is about 10 MRad of total ionizing dose. In order to study the tolerance of the DEPFET technology...Go to contribution page
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Mr Tobias Harion (Kirchhoff Institute for Physics)29/09/2011, 16:00KLauS is an ASIC in AMS 350nm Bicmos Technology with 12 Silicion Photomultiplier (SiPM) readout channels. It is designed to be used in the plastic sintillator based Analog Hadron Calorimeter (AHCal) at a future Linear Collider. Its dynamic range reaches 200pC and SNR is better than 10 for single photon signal of very low gain SiPMs. The chip provides 2V bias tuning to compensate SiPM...Go to contribution page
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Paolo De Remigis (INFN)29/09/2011, 16:00The Micro Vertex Detector is the innermost part of the Panda experiment and is constituted of pixels and strips. The design foresees a triggerless data acquisition, and Topix is the current Asic solution for the pixel readout featuring more than 10k cells with a serial data output exploiting the GigaBit Transceiver project, at present under development at CERN, that will manage the data...Go to contribution page
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Dr Peter Wieczorek (GSI Darmstadt, Germany)29/09/2011, 16:00For the electromagnetic calorimeter of the PANDA - Experiment the ASIC – Design – Group of the GSI – Experiment – Electronics department developed an integrated preamplifier and shaper ASIC. The chip developed for spectroscopy using is optimized for the readout of large area avalanche photo diodes (LAAPD) with a capacitance of 280 pF and an event rate of 350 kHz. Each ASIC has two equivalent...Go to contribution page
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Mrs Nathalie Seguin-Moreau (LAL)29/09/2011, 16:00MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active part of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital...Go to contribution page
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Dr Babak Rahbaran (HEPHY Vienna--Institute of High Energy Physics Vienna)29/09/2011, 16:00At LHC 40 million collisions of proton bunches occur every second, resulting in about 800 million proton collisions. The Level-1 trigger, a custom designed electronics system based on FPGA technology and the VMEbus system, performs a quick on-line analysis of each collision every 25 ns and decides whether to reject or to accept it for further analysis. As part of the Global Trigger Upgrade,...Go to contribution page
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Mr Pavel Stejskal (CERN)29/09/2011, 16:00Optical link components used in future particle physics experiments will typically be exposed to intense radiation fields during the lifetime of the experiment and the qualification of these components in terms of radiation tolerance is thus required. We have created a model that describes the degradation of the L-I characteristic of a semiconductor LASER undergoing irradiation with the...Go to contribution page
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Timo Tick (CERN)29/09/2011, 16:00The next generation hybrid pixel detectors in particle physics experiments require reduced mass budget, increased interconnection density and they need to be tileable to seamlessly cover large areas. These criteria cannot be fulfilled with present day interconnection techniques. As a result the particle physics community has recently put in a lot of effort to investigate and evaluate variety...Go to contribution page
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Mr Erik van der Bij (CERN)29/09/2011, 16:00The accelerator control systems at CERN will be renovated and many electronics modules like analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on VITA and PCI-SIG standards such as FMC, PCI Express and VME64x. The Wishbone specification is used as SOC bus. To attract partners, the projects are...Go to contribution page
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M. Citterio (INFN Milano)29/09/2011, 16:00The paper describes power switching converters suitable for possible power supply distribution networks for the upgraded detectors at the High Luminosity LHC collider. The proposed topologies have been selected by considering their tolerance to the highly hostile environment where the converters will operate as well as their limited electromagnetic noise emission. The analysis focuses on the...Go to contribution page
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Maria Cristina Esteban Lallana (Instituto Tecnologico de Aragon)29/09/2011, 16:00The characterization of electromagnetic noise of DC-DC converters is a critical issue that has been analyzed during the design phase of CMS tracker upgrade. Previous simulation studies showed important variations of conducted emission of DC-DC converters among impedances and power network topologies. Several tests have been performed on real DC-DC converters to validate the Pspice model and...Go to contribution page
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Andrea Brogna (Karlsruher Institut für Technologie, Institut für Prozessdatenverarbeitung und Elektronik)29/09/2011, 16:00We discuss the power supply and distribution for new linear accelerators in particular with respect to the innovative architecture of the pulsing mode. The possibility to exploit the small duty-cycle becomes a critical factor to optimize the peak and mean power over the connections and cabling to reduce the loss, undesidered heating generation and interference and other sources of noise. We...Go to contribution page
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Dr Jan Troska (CERN PH/ESE)29/09/2011, 16:00The CMS Pixel detector phase 1 upgrade calls for an optical readout system operating digitally at or above 320 Mb/s. Since the re-use of the existing link components as installed is excluded, we have designed a new Pixel Optohybrid (POH) for use within this system. We report on the design and choice of components as well as their measured performance. In particular, we have studied the...Go to contribution page
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Gianluca Traversi (University of Bergamo and INFN Pavia)29/09/2011, 16:00In a DNW MAPS a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. Various solutions complying with different sensor layout and pixel pitch have been fabricated in a planar (2D) 130nm CMOS technology. This work will discuss the design and characterization of deep N-well (DNW) monolithic active pixel sensors (MAPS)...Go to contribution page
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Mr Nicolai Schroer (ZITI, LS Informatik V, Heidelberg University, Mannheim)29/09/2011, 16:00The pixel detector of the ATLAS experiment at CERN will be upgraded with an additional layer (IBL) in 2013. To handle the data readout the currently used VME card pairs consisting of a back of crate card (BOC) and a read out driver (ROD) are being redesigned. We present details of the hardware design of the new BOC prototype. It takes advantage from modern FPGA technology and commercial...Go to contribution page
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Ms Eva Vilella (University of Barcelona)29/09/2011, 16:00The gated operation is proposed as an effective method to reduce and uniformize noise figures in particle tracking pixel detectors based on Geiger mode avalanche photodiodes for future linear colliders. A protoype based on a 3x3 array with the sensor and the front-end electronics monolithically integrated has been fabricated with the conventional HV-AMS 0.35µm technology. Experimental results...Go to contribution page
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Mikhail Matveev (Rice University)29/09/2011, 16:00We present the status of hardware and software tools for remote access to Xilinx programmable devices in the Cathode Strip Chamber Endcap Muon Electronic System at the CMS experiment at CERN.Go to contribution page
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Dr Jan Troska (CERN PH/ESE)29/09/2011, 16:00The Versatile Transceiver will be deployed on detectors that will be operated at the upgraded HL-LHC where the instantaneous luminosity will be increased by a factor of 5-10 with respect to the nominal LHC. All components housed at the front-ends must thus be immune to single-event upsets to a level compatible with the correct operation of the detector systems. We will carry out an...Go to contribution page
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Gisele Martin-Chassard (Unknown)29/09/2011, 16:00The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10^19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which...Go to contribution page
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Mr Lukas Püllen (Bergische Universitaet Wuppertal)29/09/2011, 16:00In the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be an new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network...Go to contribution page
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Dr Elena Pedreschi (Sezione di Pisa (INFN)), Dr Franco Spinella (Sezione di Pisa (INFN))29/09/2011, 16:00The main goal of the NA62 experiment at the CERN SPS is to measure the branching ratio of the K+ → π+νν decay, collecting about 100 events in two years of data taking. The nature of the experiment puts stringent requirements on the trigger and data acquisition system: the efficient online selection of interesting events and loss-less readout at high rate will be key issues. Readout uniformity...Go to contribution page
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Dr Alexander Grillo (UCSC)29/09/2011, 16:00The Semi-Conductor Tracker in the ATLAS experiment at the Large Hadron Collider is potentially subject to various beam loss scenarios. It is important to understand what the effect of such an event would be on the operation of the SCT detector. Previous tests have shown the ABCD ASIC to be the weak point of the SCT modules when exposed to the intense radiation of a beam loss incident....Go to contribution page
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Mr Mikhail Lemarenko (Physikalisches Institut-Universitaet Bonn)29/09/2011, 16:00A major upgrade of the current Japanese B-Factory (KEK-B) is planned by the fall of 2013. Together with this new machine (SuperKEK-B), also a new detector, BelleII, will be operated to fully exploit the higher luminosity (40 times larger than the previous experiment). One of the major changes in the new experiment will be the introduction of a new sub-detector, close to the interaction point,...Go to contribution page
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Dr Hans Muller (CERN), Dr José Francisco Toledo Alarcón (Valencia Polytechnic University)29/09/2011, 16:00The Scalable Readout System (SRS) was developed within RD51 collaboration as a multi-channel readout system, allowing ASICs, hybrids or discrete frontends with analog, binary or digital readout over a customizable link interface. User-specific frontends are linked to adapter cards which are straddle-mounted to Front-end Concentrator cards (FEC). The ensemble (Adapter + FEC card) forms a 6Ux220...Go to contribution page
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Mr Damien Thienpont (IN2P3/LAL)29/09/2011, 16:00A low-power and low-area circular memory has been designed in a 130 nm technology. This prototype aims to be integrated into a plannar pixel sensors readout 3D integrated circuit for the future ATLAS high luminosity upgrade. Three types of memory cell have been designed: one with Typical transistors, an other with low-Vt transistors and the last one with custom enclosed transistors. The...Go to contribution page
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Vladimir Ryjov (CERN)29/09/2011, 16:00The NA62 experiment will be focused on precision tests of the Standard Model via studies of ultra-rare decays of the charged kaons. The high resolution Liquid Krypton (LKr) calorimeter of the NA48 experiment will provide a photon-veto with hermetic coverage from zero out to large angles from the decay region. The study of an upgraded readout system began in 2008. This paper presents the...Go to contribution page
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Dr David Gascon (Universidad de Barcelona)29/09/2011, 16:00The future international high energy gamma ray observatory, the Cherenkov telescope Array (CTA), will consist in an array of 50-100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photodetectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000...Go to contribution page
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Mr Jan Michel (Goethe University Frankfurt)29/09/2011, 16:00The data transport and trigger system of the HADES di-electron spectrometer operating at GSI, Germany was upgraded recently. The main goal was to substantially increase the event rate capabilities to reach trigger rates of up to 100 kHz and data rates of 400 MByte/s. The whole data communication system is based on FPGA-equipped platforms connected by optical links. Here, a custom network...Go to contribution page
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Mr Andrej Seljak (IJS Institute Ljubljana)29/09/2011, 16:00We are developing the readout electronics for the proximity focusing hybrid avalanche photon detector (HAPD), the baseline photon sensor of the Belle II aerogel RICH. The detector, positioned in the spectrometer forward direction inside the 1.5 T magnetic field, has to efficiently detect the single photons. The readout electronics has to digitize small analog signals and transfer them to the...Go to contribution page
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Dr Mauro Raggi (Laboratori Nazionali di Frascati (LNF)-Istituto Nazionale Fisic)29/09/2011, 16:00The branching ratio for the decay K+ -> pi+ nu anti-nu is sensitive to new physics; the NA62 experiment will measure it to within about 10%. To reject the dominant background from channels with final state photons, the large-angle vetoes (LAVs) must detect particles with 1-ns time resolution and 10% energy resolution over a very large energy range. Our custom readout board uses a...Go to contribution page
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Dr Giuseppe Giraudo (INFN-Torino)29/09/2011, 16:00The Micro Vertex Detector (the MVD) for the Panda experiment is optimized for the detection of the secondary vertices and for maximum acceptance close to the interaction point. The experimental set-up requires sophisticated solutions for the detector integration in order to maintain a stringent material budget. The thermal power produced by the “on board” read-out electronics is fast removed...Go to contribution page
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Mikihiko Nakao (KEK)29/09/2011, 16:00At Belle II, most of the digitization is made inside or near the detector, and the digitized data are collected via high-speed optical serial links. Each of the frontend electronics boards equips at least one FPGA for a unified data link implementation, and at the same time to receive a system clock, the level-1 trigger and other fast timing signals and provide fast status signals. These...Go to contribution page
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Mr Peter Lemmens (KVI, University of Groningen)29/09/2011, 16:00The PANDA collaboration at the future FAIR facility at Darmstadt, Germany, will employ antiproton annihilations to investigate yet undiscovered charm-mesons and glueballs. The rich physics program requires various sophisticated event-selection criteria based e.g. on invariant mass, secondary vertices, and time correlations. Therefore, the readout electronics is designed such that all detectors...Go to contribution page
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Dr Vasilii Kushpil (Academy of Sciences of the Czech Republic (ASCR))29/09/2011, 16:00New electronic single board tester described here allows us to test and compare basic characteristics of new types of the APD (SiPMD, MCAPD, GAPD). The tester was realized in a portable form with graphics LCD and three controls buttons. It can measure statical and dynamical characteristics of the APD. We applied virtual periphery concept for very fast and simple way to measure the S/N...Go to contribution page
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111. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgradeTiankuan Liu (Southern Methodist University (US))29/09/2011, 16:00The upgrade of ATLAS Liquid Argon (LAr) calorimeter readout calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. We are addressing the problem by iterative design previously reported at TWEPP with a commercial 0.25 μm silicon-on-sapphire CMOS technology we have evaluated to be...Go to contribution page
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Dr Roberto Ammendola (INFN Roma Tor Vergata)29/09/2011, 16:00We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level 0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on-board on DDR2 latency memories and readout upon reception of a Level...Go to contribution page
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Mr Peter Lemmens (KVI, University of Groningen)29/09/2011, 16:00Charm-meson resonances and yet undiscovered glueballs might reveal the origin of the hadronic mass spectrum. The PANDA collaboration at the future FAIR synchrotron facility at Darmstadt, Germany, will employ antiproton annihilations to investigate resonances in the charmonium mass region. In order to gain high flexibility for physics event selection, a trigger-less data-acquisition system is...Go to contribution page
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Elliot Lipeles (University of Pennsylvania)30/09/2011, 09:00The HL-LHC, the planned high luminosity upgrade for the LHC, will increase the collision rate in the ATLAS detector approximately a factor of 5 beyond the luminosity for which the detectors were designed, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult...Go to contribution page
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Dr Duccio Abbaneo (CERN)30/09/2011, 09:45The planned upgrades of the the LHC and its injector chain are expected to allow operation at luminosities around or above 5x10^34 cm-2 s-1 sometimes after 2020, to eventually reach an integrated luminosity of 3000 fb-1 at the end of that decade. In order to fully exploit such operating conditions and the delivered luminosity, CMS needs to upgrade its tracking detectors and substantially...Go to contribution page
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Markus Joos (CERN)30/09/2011, 11:00
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Magnus Hansen (CERN)30/09/2011, 11:15
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Francois Vasey (CERN)30/09/2011, 11:30
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Jorgen Christiansen (CERN), Kostas Kloukinas (CERN)30/09/2011, 11:45
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Philippe Farthouat (CERN)30/09/2011, 12:00Oral
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Mr VAL30/09/2011, 16:10• Requirements to and technologies for IC packaging. • Overview of different packaging technologies and their specific applications. • Packaging for high reliability applications. • Pitfalls and challenges in IC Packaging. • Advanced 3D packaging (chip on chip / die on die / etc.).Go to contribution page
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Oral
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