TWEPP 2014 - Topical Workshop on Electronics for Particle Physics

22 Sept 2014, 10:00 → 26 Sept 2014, 18:00 Europe/Zurich

Centre des Congrès - Aix en Provence, France

Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR)), Jorgen Christiansen (CERN)

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

 

TWEPP-14 is organized with support from:

 

Monday 22 September

12:00 Registration

Welcome

Convener: Jorgen Christiansen (CERN)

1 TWEPP-14 Opening

Speaker: Jorgen Christiansen (CERN)

Slides TWEPP14-Opening.pdf TWEPP14-Opening.pptx

2 Welcome from the Local Organising Committee

Speaker: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

Slides Welcome_in_Aix_en_Provence_No2.pdf

Opening 1

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

3 HEP Electronics in France

IN2P3 promotes and unifies research activities in subatomic physics. It coordinates programs on behalf of the CNRS and Universities and has a partnership with CEA. For its experiments and international collaborations, IN2P3 has strong and long standing capabilities in developing, deploying and supporting a wide variety of instruments, from detectors up to the associated electronics. In order to improve exchanges among its engineers and focus its R&D, a network on instrumentation has been set up, subdivided according to detector types. The talk will first summarize the missions of IN2P3, then review past achievements and current R&D activities in electronics dedicated to each detector type.

Speaker: Claude Pierre Colledani (Institut Pluridisciplinaire Hubert Curien (FR))

Slides Electronics_Developments_at_IN2P3.pdf Electronics_Developments_at_IN2P3.pptx

4 From Deep Sea to Deep Space with the ANTARES and KM3NeT Undersea Neutrino telescopes

The ANTARES Collaboration is operating a large undersea detector installed by 2500m depth off the Mediterranean coast of France. Completed in 2008, ANTARES is the largest neutrino telescope of the Northern hemisphere and the first one ever built in the sea. It aims at opening a new observational window over the Universe by looking for high energy cosmic neutrino events. The ANTARES cabled observatory also constitutes a unique deep sea infrastructure for multidisciplinary Earth and Sea Sciences. In parallel, the second generation detector KM3NeT aiming at instrumenting a multi-km scale neutrino telescopes in the deep sea is being developed.

Speaker: Vincent Bertin (Centre National de la Recherche Scientifique (FR))

Slides ANTARES-TWEPP14.pdf ANTARES-TWEPP14.pptx

16:00 Coffee break

Opening 2

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

5 ITER, DEMO: On the Road to Sustainable Fusion Energy

In 2006, in Paris, China, the European Union, India, Japan, Korea, Russia and the United States committed to building ITER in Cadarache. ITER should demonstrate the feasibility of nuclear fusion, but significant amount of energy will only be produced in the next step reactors dubbed “DEMO”. What are the physical and technical challenges to be faced to produce fusion energy? Will fusion reactors open the path to a proliferation resistant and safe energy? What would be the impact of the extraction of the almost inexhaustible fuel resources from the oceans? How much nuclear waste and greenhouse gas would be produced? Will fusion energy be available soon enough to contribute to the mitigation of climate change?

Speaker: Jean-Marc ANE (CEA)

Slides ITER_DEMO_No5.pdf ITER_DEMO_No5.pptx

17:30 City Tour

19:30 Welcome Reception

Tuesday 23 September

Plenary 1

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

6 Deep Insight into Fly-inspired Optical Sensors and their Robotic Applications

The demand for innovative visual sensors increases constantly in the challenging field of autonomous aerial robotics and especially in the very new field of soft and micro-scale robotics. The compound eyes of insects and crustaceans, which show an extraordinarily wide range of designs, a remarkable optical layout, high sensitivity in dim light and even at night, and polarized light sensitivity, provide an endless source of inspiration for designing curved, flexible visual sensors of the future. After an overview of the implementation of several bio-inspired optical sensors, an innovative insect-inspired Curved Artificial Compound Eye chip reusing skills acquired in pixel design for the LHC will be described.

Speaker: Stephane Viollet (CNRS)

ASICs: A1a

Convener: Christophe De La Taille (OMEGA (FR))

7 TDCPix: Tracking for the NA62 GigaTracker

The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detector. The asynchronously operating pixel array consists of 1800 pixels, each 300x300$\mu m^2$. The requirements are a single-hit timing resolution better than 200ps RMS and read-out efficiency of 99% or better. The time-walk effect is compensated by in-pixel time-over-threshold discriminators connected to an array of 720 TDC channels. The TDCpix processes up to 80 Mhits/cm$^2$ and provides the hit data without need of a trigger in a continuous data stream via four 3.2Gb/s serialisers.

Speaker: Matthew Noy (CERN)

Slides mnoy.23.09.2014.pdf

8 The ToPiX v4 Prototype for the Triggerless Readout of the PANDA Silicon Pixel Detector

ToPiX v4 is the prototype for the readout of the silicon pixel sensors of the Micro Vertex Detector for the PANDA experiment. ToPiX provides position, time and energy measurement of the incoming particles and is designed for the trigger-less environment foreseen in PANDA. The prototype includes 640 pixels with a size of 100x100 um2, a 160 MHz time stamp distribution circuit to measure both particle arrival time and released energy (via ToT technique) and the full control logic. The ASIC is designed in a 0.13 um CMOS technology with SEU protection techniques for the digital parts.

Speaker: Giovanni Mazza (INFN sez. di Torino)

Paper

Slides GMazza_TWEPP2014.pdf

Systems, Planning, Installation, Commissioning and Running Experience: B1a

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

9 The CMS Central Hadron Calorimeter DAQ System Upgrade

The VME-based data acquisition electronics of the CMS hadron calorimeters will be replaced with a μTCA-based system starting in 2014 and continuing through 2018. The primary new components are the μHTR and AMC13 modules. The μHTR buffers data from the detector and creates trigger primitives. The AMC13 accepts the clock and trigger from the global DAQ system, distributes the clock to the μHTR and the on-detector electronics, and concentrates data for shipping back to the DAQ system. We report on the design, development status, and schedule for the new DAQ system.

Speaker: Andrew James Whitbeck (Fermi National Accelerator Lab. (US))

Paper

Slides CMS_HCal_DAQ_upgrades_TWEPP14.pdf

10 ATLAS Tile Calorimeter Electronics and Future Upgrade

The Tile Calorimeter (TileCal) of the ATLAS experiment is the hadronic calorimeter designed for energy reconstruction of hadrons, jets, tau-particles and missing transverse energy. An overview of the on-detector and off-detector TileCal electronics used for ATLAS data taking is given. Upgrade plans for TileCal electronics for the High Luminosity LHC programme in 2024 are discussed, together with R&D activities at different laboratories that target different parts of the TileCal electronics. In particular, a demonstrator prototype for TileCal electronics to be installed during the long shutdown in 2014 is described.

Speaker: Dr Giulio Usai (University of Texas at Arlington (US))

Paper

Slides twepp14_giulio_usai_v4.pdf

10:40 Coffee break

ASICs: A1b

Convener: Christophe De La Taille (OMEGA (FR))

11 FSBB-M and FSBB-A: Two Large Scale CMOS Pixel Sensors Building Blocks Developed for the Upgrade of the Inner Tracking System of the ALICE Experiment

Two CMOS Pixel Sensors (CPS) flavours: MISTRAL and ASTRAL, dedicated to the upgrade of the Inner Tracking System (ITS) of the ALICE experiment are being designed at IPHC in Strasbourg. Each of two sensors is composed of three identical units called FSBB (Full Scale Building Block), multiplexed towards the external word. This paper will show the design and the laboratory test results of FSBB-M (for MISTRAL) and FSBB-A (for ASTRAL).

Speaker: Dr Frederic MOREL (IPHC-IN2P3, UDS)

Slides TWEPP_2014_MOREL.pdf TWEPP_2014_MOREL.pptx

12 Front End Electronics for SOI Monolithic Pixel Sensor

SOI monolithic pixel sensor has been developed using 0.2 um SOI pixel process technology. Pixel diodes are formed on SOI substrate and then pixel front end electronics are formed in 40nm thin SOI layer. Tungsten vias are used to connect the diode and electronics. A simple source follower circuit, charge sensitive preamplifier, comparator, and counter are designed in a pixel area. The minimum pixel area is 8 um square with typical 3 transistor cell and a diode. In the presentation, performance test results, problems and solutions are described.

Speaker: Toshinobu Miyoshi (KEK)

Slides 20140923_twepp_soi_miyoshi_v3.pdf 20140923_twepp_soi_miyoshi_v3.pptx

Systems, Planning, Installation, Commissioning and Running Experience: B1b

Convener: Geoff Hall (Imperial College Sci., Tech. & Med. (GB))

13 Technological Prototype of a Silicon-tungsten Imaging Electromagnetic Calorimeter.

Particle Flow Algorithm (PFA) and highly granular calorimeters can achieve the best jet energy resolution aiming at precise physics measurements. As shown by years of R&D within the CALICE collaboration the silicon-tungsten imaging electromagnetic calorimeter provides the best granularity, stability and jet resolution. Our concept has been selected to compete for the upgrade of the CMS ECAL. The latest version of our detector concept, featuring 1024 channels on 4 dm2 pcb will be presented including technological choices for an application on an ILC. First thougths for the CMS ECAL upgrade will be discussed.

Speaker: Remi Jean Noel Cornat (Ecole Polytechnique (FR))

Paper

Slides TWEPP14_RC_-_V3.pdf

14 Development and Testing of the Upgrade to the CMS Level-1 Calorimeter Trigger

In 2015 the LHC will resume operations with a center-of-mass energy at 13 TeV and significantly higher Pile Up than previous runs at the LHC. In order to operate under these challenging conditions, CMS is upgrading its calorimeter trigger in two stages: the Stage 1 upgrade will be used in 2015 and integrated with the legacy system. Scheduled for 2016, Stage 2 will have an improved position and energy resolution at the Level 1 trigger.

Speaker: Isabel Ojalvo (University of Wisconsin (US))

Slides ojalvoTWEPP2014-Finalp.pdf

12:00 Lunch

Plenary 2

Convener: Jorgen Christiansen (CERN)

15 Electronics for HL-LHC: Challenges and Outlook

To further extend the ultimate physics reach of the experiments at the Large Hadron Collider (LHC), a series of accelerator and experimental upgrades are planned in 2014 (phase 0), 2018 (phase 1) and 2023 (phase 2). The phase 2 machine upgrade, called the High Luminosity-LHC (HL-LHC), is foreseen to increase the instantaneous luminosity by a factor five with a total integrated luminosity of 3000 fb−1. ATLAS and CMS plan an upgrade involving the replacement of some of their detectors (e.g. new trackers) and the replacement of almost all the trigger and readout electronics. The predicted high particle rates will lead to a higher number of readout channels (higher granularity detectors), higher trigger and data rates and intense radiation doses imposed on the front-end electronics. This presentation summarizes the challenges which the readout electronics will face, as well as the on-going and future developments.

Speaker: Philippe Farthouat (CERN)

Slides TWEPP14-Plenary-PhF.pdf

ASICs: A2

Convener: Mr Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

16 Characterization of Depleted Monolithic Active Pixel Sensor (DMAPS) Prototypes

New monolithic pixel detector concepts, which integrate the front-end circuitry and the sensor on the same silicon substrate, are being explored for track reconstruction in future particle physics experiments. The innovative concept of Depleted Monolithic Active Pixel Sensors (DMAPS) is based on a high resistive silicon bulk material enabling full substrate depletion with creation of an electrical drift field for charge collection, while keeping full CMOS capability for the electronics. Due to the availability of deep p- and n-type implantations in the used technology (ESPROS), the pixel electronics can be implemented using independently isolated N- and PMOS transistors.

Speaker: Theresa Obermann (Universitaet Bonn (DE))

Paper

Slides 07_OBERMANN.pdf

17 The ABC130 ASIC Design for the ATLAS Silicon Strip Upgrade

The ABC130 Front End ASIC for the ATLAS Silicon Strip upgrade has been designed and fabricated in IBM 130nm CMOS technology. It uses a binary architecture with fixed trigger latency, similar to that used in the current experiment, but the functionality is extended to support two readout mechanisms: one with low latency to support region of interest track trigger construction, and the other for full event readout. Key results will be shown, including first cross checks of the electronic gain and noise measured with silicon strips and first results from a fully populated detector hybrid

Speaker: Francis Anghinolfi (CERN)

Slides ABC130_Version2.pdf ABC130_Version3.pdf

18 A Dedicated Front-end for Readout of Strip Detectors in the LHCb Upgrade Experiment

Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout ASIC. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. The ASIC front-end comprises a charge preamplifier and a shaper. Fast shaping is required ($T_{peak}=25ns$, fast recovery) to distinguish between the LHC bunch crossings. A prototype of an 8-channel front-end was designed in CMOS 130 nm, fabricated and tested. The measurements showed very good performance. In particular, symmetrical output pulses with fast recovery times were observed.

Speaker: Marek Idzik (AGH University of Science and Technology (PL))

Slides idzik_TWEPP_SALT_2014.pdf

Systems, Planning, Installation, Commissioning and Running Experience: B2

Convener: Prof. Lutz Feld (Rheinisch-Westfaelische Tech. Hoch. (DE))

19 Front-End Trigger Electronics for Cathode Strip Chambers in the CMS Endcap Muon System

We have built and installed new front-end trigger electronics for the Cathode Strip Chambers in the CMS Endcap Muon system that will efficiently handle the increased data rate in the forthcoming High Luminosity LHC accelerator upgrade. Maintaining trigger efficiency in the forward region requires deployment of higher performance electronics and an improved trigger algorithm. We report on the design and recent performance tests of the newly installed trigger system, as well as the development of the new trigger algorithm.

Speaker: Jason Gilmore (Texas A & M University (US))

Slides JGslides-CSCfrontendTriggerUpgrades_Twepp2014.pdf

20 Development of the Readout System for LCTPC for the Future ILC

We will present the readout system being designed for the LCTPC (Large Prototype TPC) for the future ILC. A CPLD resident on a MCM(Multi-chip Module) board will be used to concentrate data from 8 SALTRO chips on the same board and transfer them to a SRU(Scalable Readout Unit) via a serial DTC(data, trigger, control) link, in the final system there will be 75 MCM boards sit on 3 pad module make 9600 analog channels in total. We will report the status of the first MCM prototype board as well as the full readout chain.

Speaker: yifan yang (Universite Libre de Bruxelles)

Paper

21 First Irradiation Tests Results of the ALICE TPC RCU2

This paper will present the first results from irradiation tests performed on the ALICE TPC Readout Control Unit 2 (RCU2). The RCU2 is developed in order to double the readout speed with respect to the present RCU1, which then will fulfill the requirements for LHC RUN2. While the present RCU1 is based on an SRAM based FPGA, which configuration memory has shown to be sensitive to single event upsets, the newly released Flash based Smartfusion2 FPGA from Microsemi has been chosen for the RCU2.

Speaker: Chengxin Zhao (University of Oslo (NO))

Paper

Slides TWEPP_2014_CZHAO_V3.pdf TWEPP_2014_CZHAO_V3.pptx

16:05 Coffee break

First Poster Session

Convener: Ken Wyllie (CERN)

22 ABC130 Test System and Wafer Probe Results

The first batch of wafers of ABC130, a Front End ASIC for the ATLAS Silicon Strip Upgrade in IBM 8RF 130nm CMOS technology, were received in November 2013. A design error with the bidirectional SLVS transceiver blocks was identified and corrected, then the design was resubmitted. The corrected wafers are expected to be delivered in June 2014. The poster will describe the custom driver board, probe card, firmware and software used to test ABC130. In addition wafer probe results will be summarised.

Speaker: Peter Phillips (STFC - Rutherford Appleton Lab. (GB))

Poster ABC130Poster_v2.pdf ABC130Poster_v2.ppt

23 Dream: a 64-channel Front-end Chip with Analogue Trigger Latency Buffer for the Micromégas Tracker of the CLAS12 Experiment.

The new 64-channel DREAM (Dead-timeless Readout Electronics ASIC for Micromégas) chip has been designed to read the Micromégas tracker of the CLAS12 experiment. Each channel associates a low noise very frontend part, optimized for large detector capacitances (150pF range), together with a 512-cell analogue memory, ensuring both a trigger latency and derandomization bufferization, allowing a negligible deadtime in operation, in the conditions foreseen for the experiment (20 MHz sampling and readout frequencies, 20 kHz trigger rate, and up to 16µs trigger latency). The paper describes the chip architecture and reports its main measured performances.

Speaker: Dr Christophe Flouzat (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))

Poster dream_twepp2014.pdf

24 The Front-end Electronics for the 1.8-kchannel SiPM Tracking Plane in the NEW Detector

NEW is the second phase of NEXT, an experiment aiming at searching neutrinoless double-beta decay. Neutrinoless events can only be told from very close energy background events by using to a topological signature produced at the SiPM tracking plane, making this one of the strongest features in NEXT: a high background rejection. The present work describes in detail the front-end electronics in the NEW detector as well as the new cabling solutions that have been developed. The tracking plane consists of close to 1800 sensors with a 1-cm pitch arranged in twenty-eight 64-SiPM boards.

Speaker: Mr Javier Rodriguez Samaniego (IFIC)

Paper

Poster TWEPP_2014_Poster_b.pdf

25 A Muon Trigger Upgrade with High Transverse Momentum Resolution for the ATLAS Detector at the High-Luminosity LHC

The Level-1 trigger for muons in ATLAS is based on trigger chambers (RPCs, TGCs) with excellent time resolution which are able to identify muons coming from a particular beam crossing. It is proposed to use precision tracking chambers (MDTs) for improving the transverse momentum resolution at the Level-1 trigger for the phase II of the LHC, the so-called High-Luminosity LHC. We present the new trigger algorithm and the architecture of the electronics as well as a prototype test. We demonstrate the performance for a transverse momentum threshold of 20 GeV using experimental data.

Speaker: Yasuyuki Horii (Nagoya University (JP))

Paper

Slides ATL-MUON-SLIDE-2014-642.pdf

26 Development of a Multi-points Wireless Temperature Monitoring System for Optohybrid for CMS GEM Project

We will present a multi-points wireless temperature monitoring system being designed for the optohybrid for the CMS forward moun detector upgrade project. Optohybrid is a readout board which will be installed inside CMS to control 24 front-end electronics chips and transfer the concentrated data to off-detector electronics through high speed optical fiber. An efficient cooling system is extremely important for reliable operation. We therefore designed such a system which can precisely measure the temperature of different components continuously without affecting normal run. We will report on the system design and the performance of the prototype board.

Speaker: yifan yang (Universite Libre de Bruxelles)

Poster Yifan_Yang_ID6.pdf

27 The ATLAS FTK Auxiliary Card: A Highly Functional VME Rear Transition Module for a Hardware Track Finding Processing Unit

The ATLAS Fast TracKer is a hardware-based track finder for the ATLAS High Level Trigger. Pattern recognition and preliminary track fitting are performed by VME Processing Units consisting of an Associative Memory Board (AMB) containing custom associative memory chips for pattern recognition, and the Auxiliary Card (AUX), a powerful rear transition module which formats the data for the AMB and performs linearized fits on AMB track candidates. We report on the design and testing of the AUX, which utilizes six FPGAs to process up to 32 Gbps of hit data and fit one track candidate per nanosecond

Speaker: Karol Krizka (University of Chicago (US))

28 6 bit, Low Power SAR ADC for CBM-MUCH with Maximum Sampling Rate 50 MS/s

The design considerations on ADCs as a building block for mixed-signal read-out ASICs in high energy physics are presented. The choice of successive approximation architecture is justified as optimal in terms of a power-speed trade-off, arising in multi-channel data acquisition systems for up-to-date physical experiments. As an example, the development of an area-efficient SAR ADC in 180nm CMOS process with variable sampling rate in the read-out ASIC for CBM-MUCH electronics is presented. The ADC power consumption, confirmed by start-to-finish design: 1.2 $mW$ (at sampling rate 50MS/s).

Speaker: Dmitry Osipov (NRNU MEPHI)

29 A Simulation Framework for the Track Trigger System for the CMS Upgrade

A simulation framework has been developed to test and characterize algorithms, architectures and hardware implementations of the vastly complex track trigger processor foreseen for the high luminosity upgrade of the CMS experiment at LHC. High-level SystemC models of all system components and input data from physics simulations have been used to evaluate figures of merit, like delays or bandwidths, under realistic conditions. The use of SystemC for high-level modeling allows co-simulation with models developed in Hardware Description Languages. Therefore, the simulation framework can be used as a test bench for digital modules developed for the final system.

Speaker: Christian Amstutz (KIT - Karlsruhe Institute of Technology (DE))

Poster amstutz_magazzu-A_simulation_framework_for_the_CMS_track_trigger.pdf

30 NUCLEON ASIC and Ladder Electronics for Cosmic Ray Experiment

The goal of the NUCLEON satellite mission is the measurements of the elemental energy spectra of high-energy (10**11 -10**15 eV) cosmic rays. It requires a high dynamic range of the readout electronics. The silicon strip detectors were used, the readout ASIC developed and both placed on the ladder. The ADC, data control interface, detector loads, high voltage distributer and service electronics were installed on the ladder as well. Dynamic range of the readout electronics, tested at the SPS beem is 1 – 40 000 mip. Such ladder can be used for future HEP and space cosmic ray experiments.

Speaker: Eduard Atkin (NRNU MEPHI)

Paper

31 The eCDR-PLL IC, a Radiation-Tolerant ASIC for Clock and Data Recovery and Deterministic Phase Clock Synthesis

A radiation-tolerant ASIC is being designed for LHC clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR) with determinist phase and low jitter. It operates in two FM modes: either generating 40, 120 and 240MHz outputs (for GBT-FPGA applications) or providing 40, 80, 160 and 320 MHz (for TTC and eLinks applications). The CDR operates with 40, 80, 160 or 320Mbit/s data generating in-phase clocks at 40, 80, 160 and 320MHz, regardless of the data rate. All the outputs are phase programmable with a resolution of 195 or 260ps depending on the FM mode.

Speaker: Pedro Miguel Vicente Leitao (FCT Fundacao para a Ciencia e a Tecnologia (PT))

Paper

Slides TWEPP14_eCDRPLL_Poster.pdf

32 High Reliability DC/DC Converter Module for Electronic Boards Equipped with FPGAs

A high reliability Buck DC/DC converter, ready to be used on several CERN electronic boards equipped with FPGAs, has been designed and verified. Long lifetime design, according to CERN requirements, has been implemented by minimising component stress with 50% derating. It is a compact power supply module of 16 x 19 mm, which can deliver up to 6A with 95% efficiency. Its main features include an input range from 3.0V to 5.5V, output range from 0.6V to 3.3V, shielded inductor, output ripple below ±50mVpp, soft-start and thermal shutdown.

Speaker: Jose Luis Sirvent Blasco (University of Barcelona (ES))

Paper

33 A CMOS Pixel Sensor Prototype for the Outer Layers of Linear Collider Vertex Detector

The first CMOS pixel sensor prototype integrated with 4-bit column-level ADC for the outer layers of the ILC vertex detector has been fabricated and tested. The design is adapted to an original concept of minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. Inside each pixel an amplification stage with a correlated double sampling is used. At the bottom of the pixel array, each column is terminated with a self-triggered ADC, which employs a threshold voltage to trigger the conversion. The test results of the prototype will be presented.

Speaker: Dr Liang Zhang (Shandong University)

Paper

34 Development of the Readout System for Triple-GEM Detectors for the CMS Forward Muon Upgrade

We will present the readout system being designed for triple-GEM detectors that should be installed in the CMS muon endcap system for the LHC high luminosity phase. The system takes full advantage of current generic developments introduced for the LHC upgrades: micro-TCA, MP7 and AMC13 boards, Versatile Link, GBT, etc. Some hardware components have to be specifically designed: the VFAT3 chip, the GEM Electronic Board and the Opto-Hybrid board. We will report on the readout system design, the performance of the first prototypes of the GEB, and Opto-hybrid and our experience with the micro-TCA system.

Speaker: Gilles De Lentdecker (Universite Libre de Bruxelles (BE))

35 Clock and Timing Distribution in the LHCb Upgraded Detector and Readout System

The LHCb experiment is upgrading part of its detector and the entire readout system towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity and increase its trigger efficiency. In this paper, the new timing, trigger and control distribution system for such an upgrade is reviewed with particular attention given to the distribution of the clock and timing information across the entire readout system, up to the FE and the on-detector electronics. Different solutions are compared in terms of reliability, jitter, complexity and implementation.

Speaker: Federico Alessio (CERN)

Paper

36 The CMS Hadron Calorimeter Detector Control System Upgrade

The CMS hadron calorimeter detector control system provides 40.08 MHz LHC clock to the front end electronics as well as supplying synchronization signals and I2C communication. Pedestals and diagnostic bits are controlled, and temperatures and voltages are read out. SIPM temperatures are actively stabilized by temperature readback and generation of correction voltages to drive the Peltier regulation system. Overall control and interfacing to databases and experimental DAQ software is provided by the software CCM Server. We report on design and development status, and implementation schedule of this system.

Speaker: Mehmet Ozgur Sahin (Deutsches Elektronen-Synchrotron (DE))

Paper

Slides ngFEC_TWEPP.pdf

37 A New Generation of Charge Integrating ADC (QIE) for the CMS HCAL Upgrade

The CMS experiment will upgrade the photodetection and readout systems of its hadron calorimeter through 2018. A central feature of this upgrade is the development of two new versions of the QIE, a custom ASIC for measurement of charge from detectors in high-rate environments. With 3 fC sensitivity, 17-bits of dynamic range, a time-to-digital converter with sub-nanosecond resolution, and dead-timeless operation at 40 MHz, the QIE is ideal for calorimetry at the LHC. We present performance characterization, radiation tolerance measurements, and plans for deployment in the upgraded CMS detector.

Speaker: Jim Hirschauer (Fermi National Accelerator Lab. (US))

Paper

38 A Software Package for the full GBT Chipset Lifecycle

This work presents the software environment surrounding the GBT chipset, addressing the requirements of GBTX, GBLD and GBT-SCA. The GBTX is a high speed bidirectional ASIC, implementing radiation hard optical links for high-energy physics experiments. Having more than 300 8-bit configuration registers, it poses challenges addressed by a wide variety of software components. This software keeps track of each GBT device by storing data from the testing and characterisation phase. This paper focuses on tools available to the designers and users, enabling them to create and test configurations and ensure a good quality tracking of their devices.

Speaker: Sebastian Stefan Feger (CERN)

Paper

Demonstration video SEU_test_run_demo.mov

Poster Twepp_2014_-_A_Software_Package_for_the_full_GBT_Chipset_Lifecycle.pdf

39 Low power Analog Digital Converter for a Silicon Photomultiplier Readout ASIC

We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end "KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block reduces the sampling rate. Design details and simulation results will be presented.

Speaker: Konrad BRIGGL (Heidelberg University)

Paper

40 Flexible Front-End Hybrids for the CMS Outer Tracker Upgrade

The upgrade of the CMS tracker for the HL-LHC is based on a binary readout scheme based on the CMS Binary Chip. The connectivity requirements of this flip-chip ASIC requires the use of high density interconnecting hybrids. Module integration studies indicated that a foldable flexible hybrid circuit results in an optimal module arrangement. A full module size HDI flexible hybrid was designed, integrating eight CBC2 ASICs. The hybrid is fitted with carbon fiber stiffeners and a sharp folding allows connecting the two strip sensors wirebond arrays. The mechanical properties of the assembly and its electrical performance are presented.

Speaker: Mark Istvan Kovacs (CERN)

Paper

Slides TWEPP-14_Poster_CMS_Flexible_FE_Hybrids_final_17_09_2014.pdf

41 A Low-latency and Low Overhead Encoder ASIC for the Serial Data Transmission in ATLAS LAr Calorimeter Readout Upgrade

We present the design and test results of a digital encoder ASIC, LOCic, for high-speed serial data transmission in ATLAS LAr calorimeter readout upgrade. This chip implements a low latency and low overhead line code. The user data is scrambled and encoded into a 128-bit data frame including CRC for error detection. The encoder overhead is 12.5%. A 12-bit BCID information is embedded in the frame header. The ASIC is manufactured with a commercial 0.25 µm Silicon-on-Sapphire process and tested to operate at 640 MHz with 7 ns latency.

Speaker: Datao Gong (Southern Methodist Univeristy)

Slides Poster_LOCic_TWEPP14.pdf

42 Versatile ASIC for L0 Triggering in Cherenkov Telescopes

A versatile and reconfigurable ASIC implementing multiple concepts of low level trigger (L0) for Cherenkov telescopes is presented. Two different Level-0 approaches have been included in the L0 ASIC: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analog clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger concepts. Each differential pair output of the discriminator is also available as a LVDS output. Differential circuitry using local feedback allows high speed (500 MHz) to be achieved while maintaining good linearity in a 1 Vpp range.

Speaker: David Gascon (University of Barcelona (ES))

Slides TWEPP_2014_TL0_Poster.pdf

43 FlashCam: A Novel Cherenkov Telescope Camera with Continuous Signal Digitization

The Cherenkov Telescope Array (CTA) is the next generation ground-based observatory for cosmic gamma rays. The FlashCam camera for its mid-size telescope introduces a new concept, with a modest sampling rate of 250 MS/s, that enables a continuous digitization as well as event buffering and trigger processing using the same front-end FPGAs. The high performance Ethernet-based readout provides a dead-time free operation for event rates up to 36 kHz corresponding to a data rate of 2.4 GB/s sent to the camera server. We present the camera design and the current project status.

Speaker: Dr Arno Gadola (Physik-Institut, Universität Zürich)

Paper

Poster TWEPP_2014_FlashCam_Poster_Arno_Gadola_V1.0.pdf

44 Proposed FPGA Based Tracking for a Level-1 Track Trigger at CMS for the HL-LHC

The High Luminosity LHC (HL-LHC) is expected to deliver a luminosity in excess of 5x10^34 cm^{-2}/s. The high eventrate places stringent requirements on the trigger. A key component of the CMS upgrade for the HL-LHC is a track trigger to identify tracks with transverse momentum above 2 GeV already at the first-level trigger within 5 us. This presentation will discuss a proposed track finding and fitting based on the "tracklet based approach" implemented on FPGAs. Tracklets are formed from pairs of hits in nearby layers in the detector and used in a road search.

Speaker: Nicola Pozzobon (Universita e INFN (IT))

Slides 20140922_twepp2014__pozzobon__proposed_fpga_track_finding_L1_HLLHC.pdf

45 Design of Low-Power, Low-Voltage, Differential I/O Links for High Energy Physics Applications

This work presents the design of a low-power, differential signaling, input/output data link in a 65 nm CMOS process for high-energy physics (HEP) experiments. The proposed driver is able to operate at 320 Mbps or 640 Mbps achieving a normalized power dissipation of 1.875 mW/Gbps. A pre-emphasis technique has been adopted to reduce the impedance mismatch between the driver output and the transmission line. This paper will discuss in detail the solutions implemented in the design and will describe the simulation results.

Speaker: Gianluca Traversi (Universita e INFN (IT))

Paper

Poster Poster_TWEPP_2014.pdf

46 The GBT-SCA, a Radiation Tolerant ASIC for Detector Control and Monitoring Applications in HEP Experiments

This work describes a radiation tolerant, monitoring and control ASIC for applications in HEP experiments. The GBT-SCA is part of the GBT optical link chip-set. Its purpose is to distribute control and monitoring signals to the on-detector front-end electronics for the upgrades of the LHC experiments. It is designed employing radiation hardening techniques and is fabricated in a commercial 130 nm CMOS technology. This contribution will present the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link.

Speaker: Alessandro Caratelli (Sezione di Pisa (IT))

Paper

47 Building Blocks X-fab SOI 0.18µm

Building blocks in the Silicon On Insulator 0.18 μm X-fab technology have been designed to study the future generation of SKIROC2 ASIC. These blocks are designed to characterize this technology as a possible candidate for the design of the final read-out ASIC of the Silicon Tungsten (SiW) Electromagnetic Calorimeter (ECAL) foreseen at the International Linear Collider. The performance of these building blocks will be compared to those of SKIROC2. The main parameters studied are noise, linearity, cross-talk, Power Supply Rejection Ratio, Single Event effects (SEU, SEL) and power consumption.

Speaker: Mr Jean-Baptiste Cizel (LLR/Weeroc)

Paper

Poster Building_blocks_XFAB_SOI_018.pdf

48 First Results of the Belle II Silicon Vertex Detector Readout System

At the heart of the Belle II experiment at KEK, there is a Vertex Detector composed of 2 layers of DEPFET pixels (PXD) and 4 layers of double-sided silicon strip detectors (SVD). The latter use APV25 front-end chips, originally developed for CMS, which are run in the so-called *multi-peak mode* that delivers several samples along the shaped waveform. Those are processed in the backend firmware to obtain precise amplitude and timing. The whole system (including the full DAQ chain) was successfully tested in a beam at DESY in January 2014 and first results are presented here.

Speaker: Dr Markus Friedl (Austrian Academy of Sciences (AT))

Paper

Poster friedl_twepp14_poster_a0.pdf

49 100Gbps PCI-express Readout for the LHCb Upgrade

We present a new data acquisition system under development for the next upgrade of the LHCb experiment at CERN. We focus in particular on the design of a new generation of readout boards, the PCIe40, and on the viability of PCI-express as an interconnect technology for high speed readout. We show throughput measurements across the PCI-express bus in both directions, on Altera Stratix 5 devices, using a DMA mechanism and different synchronization schemes between the FPGA and the readout-unit. Finally we discuss hardware and software design considerations necessary to achieve a throughput of 100Gbps per readout board.

Speaker: Paolo Durante (CERN)

Paper

50 Failure Analysis Results and Lessons Learned on LHC Experiments Crate and Power Supply Equipment

The LHC accelerator’s first long shutdown period (LS1), in 2013-2014, has given the experiments the opportunity to perform planned upgrade and maintenance activities on systems and equipment. It has also been the right to conduct a preventive maintenance campaign on crate and power supply equipment which is foreseen to operate smoothly for another 4 to 8 years. This paper will present the lessons learned during the LS1 power supply preventive maintenance activities as well as a in-depth analysis of the most common failure modes and weaknesses observed in LHC power supplies experiment over the past operation years.

Speaker: Sylvain Mico (CERN)

Paper

Poster Poster_TWEPP-2014.pdf

51 A Generic Firmware Core to Drive the Front-End GBT-SCAs for the LHCb Ugprade

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

Speaker: Cairo Caplan (CBPF - Brazilian Center for Physics Research (BR))

Paper

52 The development of a general purpose ARM-based Processing Unit for the ATLAS TileCal sROD

The Large Hadron Collider at CERN generates enormous amounts of raw data which present a serious computing challenge. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design difficulty for the end-user. An overview of the PU is given and the results for performance and throughput testing of Freescale i.MX6 quad-core ARM Cortex-A9 processors are presented.

Speaker: Mitchell A. Cox (University of the Witwatersrand)

Paper

53 CLIC-ACM: Generic Modular Rad-Hard Data Acquisition System Based on CERN GBT Versatile Link

CLIC is a world-wide collaboration to study the next “terascale” lepton collider, relying upon a very innovative concept of two-beam-acceleration. This accelerator, currently under study, will be composed of the subsequence of 21000 two-beam-modules. Each module requires more than 300 analogue and digital channels which need to be acquired and controlled in a synchronous way. CLIC-ACM is the custom control acquisition and control module which is being developed to concentrate all this signals in a single control point. This paper describes the system architecture with respect to its radiation-tolerance, power consumption and scalability.

Speaker: Stefano Magnoni (Universidad de Oviedo (ES))

Paper

Poster twepp2014_clic_poster.png

54 The MuPix Monolithic Active Pixel Sensor for the Mu3e Experiment

Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay mu->eee. In order to reject both combinatorial and physics background, decay vertex position, decay time and particle momenta have to be precisely measured. A pixel tracker based on 50 um thin high voltage monolithic active pixel sensors (HV-MAPS) in a magnetic field will deliver precise vertex and momentum information. Test beam results obtained with the MuPix HV-MAPS chip developed for the Mu3e pixel tracker will be presented.

Speaker: Dr Dirk Wiedner (Ruprecht-Karls-Universitaet Heidelberg (DE))

Paper

Poster TWEPP2014_Wiedner.pdf

55 Applications of Cascaded Phase Lock Loop (PLL) Blocks inside Field Programmable Gate Array (FPGA)

Signals with various timing relations can be generated inside FPGA conveniently with internal phase lock loop (PLL) blocks. When multiple PLL blocks are cascaded together. In this paper, clocks generated by cascaded PLL with slightly difference in frequencies are studied. They are used to produce pulse pairs with precise timing delay control at 0.98 ps/step. They are also used to generate calibration signals inside FPGA based TDC with evenly spread timing spectrum. The cascaded PLL can also be used for relative phase measurement of several input clocks. The firmware of the FPGA and the measurement results are presented.

Speaker: Dr Jinyuan Wu (Fermilab)

56 Extensions for the Rear Side of MicroTCA.4 Systems

For special needs at the European XFEL invented an RF-Backplane. It is an optional extension for the 9U crates in the MicroTCA.4 standard. The passive RTM backplane is suited for interconnection of high-precision RF and CLK signals for μRTM and the new extended RTMs. It improves cable management and system reliability and offers more space for electronics. Furthermore with this backplane come also new RTM Power Modules, which deliver managed low-noise bipolar analog voltages. To manage this backplane a new MCH-RTM Backplane Management was developed, which has a direct connection to the front MCH.

Speaker: Annika Rosner (DESY)

57 Radiation Testing Techniques and Results For the ATLAS TileCal Upgrade

We present results from recent radiation tolerance tests that we have performed on prototype boards and components for the front-end electronics intended for the upgrade of the hadronic calorimeter (TileCal) for the ATLAS experiment at the LHC. The tests include Total Ionizing Dose (TID) tolerance, Non-Ionizing Energy Loss (NIEL) tolerance, and Single Event Effects (SEE) tolerance. We describe the test setups used, the methodology, the different boards tested and their radiation tolerance requirements, and test results

Speaker: Gary Drake (Argonne National Laboratory (US))

58 DDL, the ALICE Data Transmission Protocol and its Evolution from 2 to 6 Gb/s.

ALICE (A Large Ion Collider Experiment) is the detector system at the LHC (Large Hadron Collider) that studies the quark-gluon plasma. The information sent by the sub-detectors composing ALICE are read out by DATE (Data Acquisition and Test Environment), the ALICE data acquisition software, using hundreds of multi-mode optical links called DDLs (Detector Data Links). To cope with the higher luminosity of the LHC, the bandwidth of the DDL links will be upgraded in 2015. This paper will describe the evolution of the DDL protocol from 2 to 6 Gbit/s.

Speaker: Filippo Costa (CERN)

Paper

59 The Synchronization of CMS ECAL Trigger Primitives via Optical Links

The calorimeter trigger of the CMS experiment at the LHC uses Synchronization and Link Boards (SLB) to perform the synchronization of trigger primitives (TP) from the electromagnetic and hadronic calorimeters and transmit these TPs to the Regional Calorimeter Trigger (RCT). During the first long shutdown, the SLBs will be replaced by optical SLBs (oSLBs) and the receiver mezzanines (RM) in the RCT will be replaced by optical RMs (oRMs). With this upgrade, we can send a copy of the ECAL TPs to the future calorimeter trigger, while being transparent to the current system.

Speaker: Jose Carlos Rasteiro Da Silva (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

60 Progress Towards the First Prototype of a Silicon Tracker Using an 'Artificial Retina' for Fast Track Finding

Our research aims to develop a specialized track processor capable of precisely reconstructing events with hundreds of charged-particle tracks in pixel and silicon strip detectors at 40 MHz. For this purpose we design and test a massively parallel, neurobiology-inspired, pattern-recognition algorithm. Here we present the R&D for a first prototype of silicon tracker with trigger capabilities based on this novel approach for fast track finding. We report on the design and the construction of a practical device that consists of a telescope based on silicon strip detectors. The track finding algorithm has been implemented using commercial FPGA of TEL62 boards. Tracking performance and trigger capabilities of the device are presented along with perspective for future applications.

Speaker: Andrea Abba (Università degli Studi e INFN Milano (IT))

61 Global Trigger Upgrade Firmware Architecture for the Level-1 Trigger of the CMS Experiment

The Global Trigger (GT) is the final step of the CMS Level-1 Trigger and implements the “menu'' of triggers, which is a set of selection requirements applied to the final list of objects (such as muons, electrons or jets) to trigger the readout of the detector and serve as basis for further calculations by the High Level Trigger. Operational experience in developing trigger menus from the first LHC run has shown that the requirements increased as the luminosity and pile-up increased. The new GT is designed based on Xilinx Virtex-7 FPGAs, which combine unsurpassed flexibility with regard to scalability and high robustness.

Speaker: Dr Babak Rahbaran (Austrian Academy of Sciences (AT))

Paper

62 MMC Implementation for the MTCA Devices Used in X-FEL

The MTCA electronics standard, except the high performance fast serial links on the backplane, provides also extensive management of the devices in crate. Each AMC board must have MMC implemented to get power in the MTCA crate, which in many cases is barrier for new users to switch to MTCA. This presentation/poster will show details and aspects of the MMC implementation developed at DESY for the X-FEL project, in which MTCA.4 will be used as the main standard for the electronic systems.

Speaker: Dr Jaroslaw Szewinski (NCBJ Swierk)

Poster TWEPP_poster.pdf

63 Development of a Five Channel, 12 bit, 800 MSPS µTCA-Based Digitizer For the Muon g-2 Experiment at Fermilab

We present the design of a 5 channel 800 MSPS uTCA based digitizer that will be deployed in the the Muon g-2 Experiment at Fermilab. The digitizer features 12-bit 800 MSPS digitizers with dedicated 1Gbit memory buffers. Multiple Xilinx Kintex-7 FPGAs provide the control and coordination within the digitizer. Provisions for a modular front end allow for application specific analog signal conditioning prior to digitization. The design conforms to the AMC standard for a full size, dual module. We will also discuss initial test results.

Speaker: Nate Rider (Cornell University)

64 The CMS Level-1 Calorimeter Trigger Electronics System for the LHC Run II

The CMS experiment implements a two-level online selection system. The first level is based on coarse information coming from the calorimeters and the muon detectors while the High Level Trigger combines fine-grain information from all sub-detectors. During Run II, the goal is to maintain the current thresholds (e.g., for electrons and photons) and improve the performance for the selection of taus. The plan to upgrade the CMS trigger system will be presented as well as recent hardware and firmware developments. Algorithms selecting electrons, photons, taus and jets will also be presented along with the expected performance.

Speaker: Thierry Romanteau (Ecole Polytechnique (FR))

Paper Upd_proceeding_twepp2014_romanteau.pdf

Poster Twepp2014_Romanteau_A0_rv1.pdf

Wednesday 24 September

Plenary 3

Convener: Alessandro Marchioro (CERN)

65 Exploiting Physics at the Nanoscale: Innovative Microsystems Process and Device Technologies at Sandia National Laboratories

Sandia’s MESA complex includes both silicon and compound semiconductor fabs and over 100 laboratories, staffed by 500 scientists, engineers, and technologists. In addition to radiation-hardened silicon and III-V process technologies, Sandia conducts R&D through product delivery in a wide array of nanoscale and microscale technologies, including many relevant to the particle physics community. This talk will describe several technologies including radiation-hardened semiconductors, atomic physics-based devices, optoelectronics/photonics, MEMS, sensors, and others. The goal of the presentation is to foster partnerships with the global particle physics community to develop new sensors and electronics based upon MESA process and device technologies.

Speaker: Gilbert Herrera (Sandia National Laboratories)

Slides TWEPP_2014_Herrera_final.pdf TWEPP_2014_Herrera_final.pptx

ASICs: A3a

Convener: Alessandro Marchioro (CERN)

66 PACIFIC: A 128 Ch ASIC for Scintillating Fiber Tracking in LHCb Upgrade

The design of a 128 channel ASIC (PACIFIC) for the upgrade of LHCb tracker system is presented. The detector will be made of scintillating fibers and read out by 128 channel SiPM arrays. PACIFIC chip will be connected to a SiPM without any external component. It includes analog signal processing and digitization. The first stage is a current conveyor followed by a tunable fast shaper (~10ns) and a gated integrator. The digitization is done using a 3-bit non-linear flash ADC operating at 40MHz. The power consumption is below 8mW/Ch. The chip will use an 130nm CMOS technology.

Speaker: David Gascon (ICC-UB)

Slides PACIFIC_TWEPP14p.pdf

67 CLARO-CMOS: a Fast, Low Power and Radiation-hard Front-end ASIC for Single-photon Counting in 0.35 Micron CMOS Technology

The CLARO-CMOS is a prototype ASIC for fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of about 1 mW per channel. The chip was designed in 0.35 micron CMOS technology, and was tested for radiation tolerance with neutrons up to 10$^{14}$ 1 MeV neq/cm$^2$ and protons and X-rays up to 8 Mrad. Its capability to readout single photons at high rate from a Hamamatsu R11265 Ma-PMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated.

Speaker: Paolo Carniti (Universita & INFN, Milano-Bicocca (IT))

Paper

Slides Slides_TWEPP2014_CLARO.pdf

Systems, Planning, Installation, Commissioning and Running Experience: B3a

Convener: Magnus Hansen (CERN)

68 A TTC Upgrade Proposal Using Bidirectional 10G-PON FTTH Technology

A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being proposed to replace the existing off-detector TTC system used by the LHC experiments. High split ratio, dynamic software partitioning, low and deterministic latency, as well as low jitter are required. Exploiting the latest available technologies allows delivering higher capacity together with bidirectionality, a feature absent from the legacy TTC system. This article focuses on the features and capabilities of the latest TTC-PON prototype based on 10G-PON FTTH components along with the metrics characterizing its performance.

Speaker: Dimitrios Marios Kolotouros (University of Ioannina (GR))

Paper

Slides TWEPP2014_Kolotouros.pdf

69 The FC7 AMC for Generic DAQ/Control Applications in CMS

The FC7 is a flexible, μTCA compatible Advanced Mezzanine Card (AMC) for generic data acquisition/control applications. Built around the Xilinx Kintex 7 FPGA, the FC7 provides developers with a platform which has access to a large array of configurable I/O, primarily delivered from onboard FPGA Mezzanine Card (FMC) headers. Targeting users of high speed optical links in high energy physics experiments, the board is capable of driving and receiving links up to 10Gb/s. This paper presents test results from the first set of pre-production prototypes and reports on FC7 uses and applications towards upgrades in CMS.

Speaker: Mark Pesaresi (Imperial College Sci., Tech. & Med. (GB))

Paper

Slides FC7.pdf

10:40 Coffee break

ASICs: A3b

Convener: Alessandro Marchioro (CERN)

70 SPIROC and TRIROC, Design and Performance of Dedicated Very Front-End for SiPM

The SPIROC and TRIROC chips are complete dedicated very front-end electronics for the readout of SiPM. Designed with AMS 0.35 µm SiGe technology, they enable to digitize and process signal over such a large dynamic range ADC. SPIROC has been extensively used for calorimeters by different groups for ILC (International Linear Collider) HCAL and ECAL prototypes. With its 64-channel readout, TRIROC targets Time-of-Flight Positron Emission Tomography (TOF-PET) application. TRIROC had been designed for TRIMAGE European project and includes compatibility with positive and negative SiPM signals and benefits from a TDC fine time binning of 40 ps. Designs and measurements of both chips will be presented.

Speaker: Ludovic Raux (OMEGA Ecole Polytechnique -CNT)

Slides SiPM_ROC_TWEPP14_ter.pdf SiPM_ROC_TWEPP14_ter.pptx

71 Low Noise 4-channel Front End ASIC with On-Chip DLL for the Upgrade of the LHCb Calorimeter

An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and includes dedicated solutions to achieve low noise, linearity and spill-over specifications. The included DLL is capable of shifting the phase of the LHC clock (25 ns) in steps of 1ns. The selected technology is AMS SiGe BiCMOS 0.35um.

Speaker: Eduardo Picatoste Olloqui (University of Barcelona (ES))

Paper

Slides TWEPP2014_ICECALv3.pdf

Systems, Planning, Installation, Commissioning and Running Experience: B3b

Convener: Magnus Hansen (CERN)

72 Development of Scalable Electronics for the TORCH Time-of-Flight Detector

The TORCH detector is proposed for the low-momentum particle identification upgrade of the LHCb experiment. It combines Time-Of-Flight and Cherenkov techniques to achieve particle separation up to 10GeV/c. This requires a timing resolution of 70ps for single photons. Existing electronics has already demonstrated a 26ps intrinsic timing resolution, however the channel density needs improvements for future Micro Channel Plate (MCP) devices. This paper will report on a scalable design using custom ASICs (NINO-32 and HPTDC). The system provides up to 8x64 channels for a signal MCP device.

Speaker: Rui Gao (University of Oxford (GB))

Paper

Slides TWEPP_2014_GAO.pdf TWEPP_2014_GAO.pptx

73 The Central Logic Board and its Auxiliary Boards for the Optical Module of the KM3NeT Detector

The KM3NeT neutrino telescope will be composed of many optical modules, each of them containing 31 (3") photomultipliers, connected to a Central Logic Board. The Central Logic Board integrates Time to Digital Converters that measure Time Over Threshold of the photomultipliers signals while White Rabbit is used for the optical modules time synchronization. Auxiliary boards have also been designed and built in order to test and extend the performance of the Central Logic Board. The Central Logic Board, as well as the auxiliary boards, will be presented by focusing on the design consideration, prototyping issues and tests.

Speaker: Antonio Orzelli (INFN Genova)

Paper

Slides twepp_clb.pdf

12:00 Lunch

ASICs: A4

Convener: Christophe De La Taille (OMEGA (FR))

74 Development of Front-end Electronics for LumiCal Detector in CMOS 130 nm Technology

The design and preliminary measurement results of a multichannel, variable gain front-end electronics for LumiCal detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier and CR-RC shaper with pole-zero cancellation circuit. Measurement results confirm full functionality of the prototype and compliance with all requirements imposed by the detector specification. Power consumption of the front-end is around 1.5 mW per channel with 50 ns peaking time and noise ENC below 900 e$^{-}$.

Speaker: Jakub Moron (AGH University of Science and Technology (PL))

Paper

Slides moron_Twepp_LumiCal_2014.pdf

75 High-speed, High-resolution, Radiation-tolerant SAR ADC for Particle Physics Experiments

We present the design of a 12-bit, 160-MSPS two-step SAR ADC in 40-nm CMOS with calibration and radiation test results. The ADC measured 67.5-dB SNDR and ≥85-dB SFDR that displayed minimal degradation after being exposed to a total ionizing dose of up to 1 Mrad. The power consumption is 4.5 and 6.1 mW at 80 and 160 MSPS, respectively. The small die size also opens up good potential for single event error treatment using redundancy techniques. The experimental results reveal great potential of SAR ADC for high-energy particle physics experiments.

Speaker: Prof. Yun Chiu (The University of Texas at Dallas)

Paper

Slides 07_CHIU.pdf 07_CHIU.pptx

76 VMM2 - An ASIC for the New Small Wheel

We present VMM2, an ASIC for charge-interpolating trackers designed for use with Micromegas and sTGC in the ATLAS Muon upgrade. It integrates 64 channels, each providing charge amplification, discrimination, neighbor logic, amplitude and timing measurements, analog-to-digital conversions, and either direct or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. Designed and fabricated in a commercial 130 nm technology, has a layout size of 13.5×8.4 mm² and it is packaged in a custom 400-pin Ball Grid Array (BGA).

Speaker: Gianluigi De Geronimo (Brookhaven National Laboratory (US))

Slides TWEPP_2014_VMM2_fin.pptx

77 A Radiation Hardened TDC with < 10 ps Resolution and Improved Recovery Time from Single Events in 40 nm CMOS

A radiation hardened Time-to-Digital Converter (TDC) has been designed with < 10 ps single-shot resolution using resistive interpolation. The TDC uses a DLL based control loop to calibrate gate delays to a reference clock. The control loop uses a novel low bandwidth Bang-Bang phase detector in combination with a high bandwidth dead-zone PFD for fast recovery after single-event strikes. The Bang-Bang phase detector has internal self-calibration for total dose radiation hardening. Finally an adapted flip-flop is used in the time capture registers that has no data dependent delay to improve overall resolution.

Speaker: Mr Jeffrey Prinzie (KU Leuven)

Paper

Slides A_Radiation_Hardened_TDC_JeffreyPrinzie.pdf

78 Design of Bandgap Reference Circuits in a 65 nm CMOS Technology for HL-LHC Applications

This work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65nm CMOS technology. Together with a conventional structure which exploits bipolar devices, a smaller solution based on diodes and a version with MOS transistors biased in weak inversion region are included. This paper intends to describe and compare the features of the different approaches by means of simulation and experimental results.

Speaker: Gianluca Traversi (Universita e INFN (IT))

Paper

Slides TWEPP_2014_v2.pdf

Systems, Planning, Installation, Commissioning and Running Experience: B4a

Convener: Wesley Smith (University of Wisconsin (US))

79 The High Throughput Readout Chain of the DSSC 1M Pixel Detector Operating in Pulsed Mode

The readout chain of the DSSC 1Megapixel detector currently built at DESY, Hamburg for the European X-Ray Free Electron Laser XFEL.EU is described. The system operates in a pulsed mode comparable to the new ILC. 800 images of 1Megapixels (9 bit per pixel) are produced at a rate of 10 Hz leading to a total throughput requirement of 144 GBit/s. In order to deal with the high data rates, the latest Kintex7 FPGAs are used to implement fast DDR3-1600 image buffers and high speed Aurora- and 40 GBit/s QSFP+ links.

Speaker: Mr Manfred Kirchgessner (University Heidelberg)

Paper

Slides DSSC_FastReadoutChain.pptx

80 IPbus: A Flexible Ethernet-based Control System for xTCA Hardware

The xTCA standards define pathways for control communication, but no specific hardware control protocol is defined. The IPbus suite of software and firmware implements a reliable high-performance control link for particle physics electronics, and has succesfully replaced VME control in several large projects. In this talk, we outline the IPbus system architecture, and describe recent developments in the reliability, scalability and performance of IPbus systems, carried out in preparation for deployment of CMS upgrades before the LHC 2015 run. We also discuss lessons learnt in the integration of a complex distributed firmware and software system, and future directions.

Speaker: Tom Williams (University of Bristol (GB))

Paper

Slides IPbus_TWEPP_20140924_v1.pdf

Trigger: B4b

Convener: Wesley Smith (University of Wisconsin (US))

81 Upgrade of the ATLAS Central Trigger for LHC Run 2

This talk focuses on the upgrades of the ATLAS central trigger processor (CTP) during the past year. The increased energy and luminosity of the LHC in the next run period requires a more selective trigger menu in order to satisfy the physics goals of ATLAS. Therefore the electronics of the CTP is upgraded and the commissioning status will be presented. In addition, the CTP software has been extended to allow the CTP to be partitioned into three freely configurable and separately operating sets of sub detectors. This new approach and its operational advantages are discussed as well.

Speaker: Kristof Schmieden (CERN)

Paper

Slides 2014_twepp_L1CT.pdf

82 ATCA-based ATLAS FTK Input Interface System

The first stage of the ATLAS Fast TracKer (FTK) is an ATCA-based input interface system, where hits from the entire silicon tracker must be clustered and organized into overlapping eta-phi trigger towers before being sent to the tracking processors. First, FTK Input Mezzanine cards receive hit data and perform clustering to reduce data volume. Then, the ATCA-based Data Formatter system will organize the trigger tower data, sharing data among boards over a full-mesh backplane. The board and system level performance studies and implementation details, as well as the operation experiences from the FTK full-chain testing, will be presented.

Speaker: Yasuyuki Okumura (University of Chicago (US))

Paper

Slides twepp.yasuyuki.okumura.v3.pdf

83 First Operation of the Level-0 Trigger of the NA62 Liquid Krypton Electromagnetic Calorimeter

The setup of the experiment NA62, studying ultra-rare decays of charged kaons at the CERN SPS, is going to be completed for the first physics data taking in the autumn of 2014. We present the final design, implementation and the first on-field performance tests of the Level-0 trigger system of the Liquid Krypton calorimeter, photon veto in the 1-10 mrad region. The system is composed of 36 readout boards (TEL62), 108 mezzanines and 215 FPGAs. It identifies electromagnetic clusters, with an instantaneous hit rate up to 30 MHz, providing information on time, position and energy.

Speaker: Nicola De Simone (Universita e INFN Roma Tor Vergata (IT))

Paper

Slides twepp214_na62lkrl0.pdf

16:05 Coffee break

Second Poster Session

Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))

84 Adaptive power supply for the gain stabilization of SiPM

The gain of SiPMs depends both on bias voltage and on temperature. We can compensate the temperature variation by regulating the bias voltage. We have developed and built an adaptive bias voltage regulator and performed tests in a climate chamber at CERN. Over a temperature range 1 – 40 degrees C we have tested the performance of the bias voltage regulator with five SiPMs / MPPCs from three different manufacturers. We demonstrate that we achieve a gain stability of less than 1% for temperatures between 20-30 degrees C as anticipated.

Speaker: Ivo Polak (Acad. of Sciences of the Czech Rep. (CZ))

Slides TWEPP2014_ivo_gainStab.pdf

85 Architectural Improvements and Technological Enhancements for the APEnet+ Interconnect System

In this paper we describe the latest generation of APEnet+ network interface card. This new APEnet+ generation delivers a point-to-point, low-latency, 3D-torus NIC integrated in a PCIe Gen3 board based on a state-of-the-art, 28nm Altera Stratix V FPGA. The NIC features a network architecture designed following the Remote DMA paradigm and tailored to tightly bind the computing power of modern GPUs to the communication fabric. For the new APEnet+ card we show characterizing figures as achieved bandwidths, eye diagrams and BER obtained by exploiting new high performance ALTERA transceivers and PCIe Gen3 compliancy.

Speaker: Andrea Biagioni (INFN Rome Section)

Paper

86 New Approach to Preamplifier-Shaper Design

A new approach to design of amplification blocks (such as preamps, shapers) is described. The generalized block diagram and analytic expressions for its transfer function are presented. The particular cases of this structure are classical schemes, using either the voltage or current feedback, but not limited by them. The discussed formulas can be useful for the design of a whole range of amplifier blocks, built according to both a traditional and a non-traditional structures. As a result of expression analysis the features of various particular cases are given. For example, those were confirmed by simulations and experimental data.

Speaker: Eduard Atkin (NRNU MEPHI)

Paper

87 Optimisation of the Front-End Electronics of Drift Tube Chambers for High-Rate Operation

We report on the high-rate optimisation of a new Amplifier/Shaper/Discriminator (ASD) chip for the ATLAS Monitored Drift Tube (MDT) chambers, which have to sustain an unprecedented radiation background during LHC operation. The design of a new ASD chip is inevitable to provide enough chips for future upgrades of the MDT chamber front-end electronics and desirable to optimise the shaping properties. This is necessary to fully exploit the improvements of new small diameter drift tube chambers (sMDT), which have been developed for high rate operation.

Speaker: Philipp Schwegler (Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)

Poster Poster_TWEPP_2014_Schwegler.pdf

88 Zero Suppression Logic of the ALICE Muon Forward Tracker Pixel Chip Prototype PIXAM and Readout Electronics Development

In the framework of the ALICE experiment upgrade at HL-LHC, a new tracking detector, the Muon Forward Tracker, is foreseen. To fulfill detector requirements, CMOS Monolithic Active Pixel Sensor (MAPS) technology was chosen thanks to interesting performances and properties in terms of readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This paper presents the large size prototype PIXAM, designed in a 0.18 µm process, and will focus specially on the zero suppression logic of the chip which does the data compression. Finally, the readout electronics principle of the compressed data flow is also presented.

Speaker: Dr Christophe FLOUZAT (CEA Centre de Saclay)

Paper

Poster poster_15.pdf

89 MicroTCA and AdvancedTCA Equipment Evaluation and Customization for LHC Experiments

The MicroTCA and AdvancedTCA industry standards are candidate modular electronics platforms for the upgrade of the current generation of high energy physics experiments at CERN. The PH-ESE group at CERN launched an xTCA evaluation project with the aim of performing technical evaluations and providing support for commercially available components. Over the past years, different equipment from different vendors has been evaluated. This paper summarizes our evaluation results of commercial MTCA and ATCA equipment. Special emphasis is put on the component requirements defined in view of future equipment procurement. Customized prototypes developed according to these generic specifications are presented.

Speaker: Matteo Di Cosmo (Ministere des affaires etrangeres et europeennes (FR))

Paper

Slides MicroTCA_and_AdvancedTCA_equipment_evaluation_and_customization_for_LHC_Experiments.pdf

90 Readout Electronics Upgrade on ALICE/PHOS Detector for Run 2 of LHC

The ALICE PHOS collaboration is carrying out a major upgrade of its readout electronics for the RUN 2 of LHC (2015-2017). The upgrade mainly includes three aspects: 1) The increase of the event readout rate; 2) The improvement of the communication stability of the interface between Front-end electronic boards and readout concentrators; 3)The compatibility to the upgraded ALICE Trigger system and DATE software. We will present the latest status of the upgrade activities, with particular focus on the technical implementation strategies and the test results.

Speaker: Dr Dong Wang (Central China Normal University)

Paper

Poster poster_big092002.pdf

91 The Readout Chain for the PANDA MVD Strip Detector

The PANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons on stationary targets. The Micro-Vertex-Detector (MVD) as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors.
Developments for the readout of the strip detectors, ranging from a customized self-triggering readout ASIC and a Module Data Concentrator ASIC at the stave level over the GigaBit Transceiver (GBT) link to the FPGA-based off-detector electronics, will be presented.
Supported by BMBF, HIC4FAIR and JCHP.

Speaker: Mr Robert Schnell (Justus-Liebig-Universitaet Giessen (DE))

Paper

Poster PANDA_MVD_Strip_DAQ.pdf

92 Low-Power Clock Distribution Circuits for the Macro Pixel ASIC

Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed, based on standard supply voltage and on auxiliary, reduced supply. Circuit performance, in terms of power consumption and speed, is evaluated for each of the proposed solutions and compared with that relevant to standard CMOS drivers.

Speaker: Luigi Gaioni (Universita e INFN (IT))

Paper

Poster poster_twepp2014_gaioni.pdf

93 High-Resolution Time To Digital Converters for the KM3NeT Neutrino Telescope

Thirty-one high-resolution time-interval measuring channels have been implemented in Field-Programmable Gate Arrays for the KM3NeT high energy neutrino telescope. Time to digital Architectures with low resources occupancy are desirable allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The required resolution to measure both, time of flight and timestamp must be 1 ns. A 4-Oversampling technique with two high frequency clocks and an asymmetric FIFO memory is used to achieve this resolution. The proposed TDC firmware is developed in Xilinx Kintex-7

Speaker: David Calvo (IFIC)

Paper

94 Development of GEM Electronics Board (GEB) for Triple-GEM Detectors

Developed for use with triple GEM detectors; the GEM Electronics Board (GEB) forms a crucial part of the electronics readout system being developed as part of the CMS muon upgrade. The objective of the GEB is three-fold; to provide stable powering and ground for VFAT3 front ends, to enable high speed communication between 24 VFAT3 front ends and an Optohybrid, and to shield the GEM detector from electromagnetic interference. The paper will describe the concept and design of a large-size GEB in detail, highlighting the challenges in terms of design and feasibility of this deceptively difficult system component.

Speaker: Joonas Petteri Talvitie (Lappeenranta Univ. of Technology (FI))

Paper

Slides TWEPP2014_posterA0.pdf

95 Development of a FEI4 Wafer Level Stress Compensation Layer for Improvement of Thin Pixel Modules 3D Assembly

Low mass pixel modules are developed for reducing radiation length in CERN LHC atlas system upgrade consisting of a silicon sensor flip-chipped with micro-bumps to a FEI4 read-out integrated chip. Thinning the FEI4 chips to 100 µm results in increasing chip bow leading to co-planarity issues during flip-chip reflow process. We demonstrate that chip deformation can be dynamically compensated adding an appropriate layer onto the wafer back-side. Working with thermo-mechanical models and experimental trials of deposited stacks we are able reducing the bow magnitude by a factor of 3 over the temperature range.

Speaker: Gabriel Pares (C)

96 MicroTCA.4 for Industry and Research – Experiences with the Introduction of a New Crate Standard

MicroTCA.4 is a novel electronic standard derived from the Telecommunication Computing Architecture (TCA) and rapidly evolved to become a viable standard for demanding applications in large-scale research facilities of the high-energy physics and photon science community. DESY has taken on a coordinating role in the further development of MicroTCA.4 components as well as the further advancement of the standard.

Speaker: Katharina Fein (DESY)

97 Test Bench Development for the Radiation Hard GBTX ASIC

This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements bidirectional 4.8 Gb/s links between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional tests of the GBTX and to evaluate its performance. Total Ionizing Dose and Single-Event Upsets tests were also performed and the results will be presented in this paper.

Speaker: Pedro Vicente Leitao (CERN)

Paper

Slides TWEPP14_GBTX_TestBench_Poster.pdf

98 Secondary Particle Acquisition System for the CERN Beam Wire Scanners upgrade

A secondary particle shower acquisition system is under design for the new CERN wire scanner-based beam profile monitors. In these systems a thin wire passes through a circulating beam and the resulting secondary particles are detected to reconstruct the beam profile. It is proposed that the new acquisition system be based on a polycrystalline diamond detector (pCVD). The accompanying electronics should exploit the high dynamic of such detector, with digitization in the tunnel and optical transmission to the signal processing electronics on the surface. In addition the signal chain must be capable of 40 MHz bunch by bunch measurements.

Speaker: Jose Luis Sirvent Blasco (University of Barcelona (ES))

Paper

Slides TWEPP14_Poster_Sirvent.pdf TWEPP14_Poster_Sirvent.pptx

99 The Clock and Control System for the EuXFEL 2D Detectors: Firmware and System Integration

The firmware structure and system integration of the final Clock and Control (CC) hardware for the EuXFEL 2D mega-pixel detectors are presented. The hardware was developed as a combination of an AMC board and a custom RTM that would work in a MTCA.4 crate. The firmware consists of a number of modules interconnected around a bus/register system that communicates to the control system over PCIe. The firmware also communicates with the front end electronics, veto unit and the timing system. The control of the system operation is through a device implemented on the EuXFEL DAQ software framework.

Speaker: Erdem Motuk (University College London)

TWEPP_2014_poster [Compatibility Mode].pdf

100 SET Detection and Compensation and Its Application in PLL Design

We present a new charge-compensation (CC) scheme to mitigate single-event-transient effect in designing a phase-locked loop. The CC method significantly reduces SET-induced voltage perturbation at the oscillator control node as well as a faster recovery. It is triggered only when SET strikes occurs and thus does not affect normal PLL dynamics. The PLL achieves a 12.5MHz to 500MHz tuning range with an RMS jitter of 4.9pS. It consumes 21.5mW of power under 1.5V supply. The CC circuit consumes 4.5mW of power and occupies 5.3% of the PLL area.

Speaker: Prof. Jinghong Chen (University of Houston, Texas)

Paper

Slides TWEPP_SET_Detection_and_Compensation_and_Its_Application_in_PLL_Design.pdf TWEPP_SET_Detection_and_Compensation_and_Its_Application_in_PLL_Design.pptx

101 A Digital Readout System for the CMS Phase I Pixel Upgrade

The Phase I Upgrade to the CMS Pixel Detector at the LHC features a new 400 Mb/s digital readout system. This new system utilizes upgraded custom ASICs, PSI46dig Read Out Chips (ROC) and Token Bit Manager (TBM08/09) for data packaging, new optical links, and changes to the Front End Drivers (FEDs). We will be presenting the new architecture of the full readout chain, the new schema for data encoding/transmission, and the results of preliminary testing of the new components.

Speaker: Robert Stringer (University of Kansas (US))

Paper

Slides TWEPP2014-final.pdf

102 Analogue Sum ASIC for L1 Trigger Decision in Cherenkov Telescopes Cameras

An application specific integrated circuit (ASIC) has been developed for level 1 trigger decisions in Cherenkov Telescope cameras. The ASIC comprises 7 input differential analogue channels and 2 output digital differential channels. Analogue inputs are provided by the previous trigger stage implemented in the so-called L0 ASIC. The L1 ASIC computes the analogue sum of three configurable sets of inputs, and provides digital output signals when any of the sums is above configurable voltage thresholds. The analogue signal processing stage has been specifically developed for this application by means of a low noise differential architecture that provides 500MHz bandwith.

Speaker: Lluís Freixas Coromina (C)

Paper

Poster Poster PDF describing the analog ASIC for trigger level 1 for CTA LST camara telescopes.

103 Architecture of the Upgraded BCM1F Backend Electronics for Beam Conditions and Luminosity Measurement - Hardware and Firmware

The Beam Radiation Instrumentation and Luminosity Project of the CMS experiment, consists of several beam monitoring systems. One system, the upgraded Fast Beams Condition Monitor, is based on 24 single crystal CVD diamonds with a double-pad sensor metallization and a custom designed readout. Signals for real time monitoring are transmitted to the counting room, where they are received and processed by new back-end electronics designed to extract information on LHC collision, beam induced background and activation products. Data in the form of histograms is transmitted to the DAQ. The system architecture and signal processing algorithms will be presented.

Speaker: Agnieszka Anna Zagozdzinska (Warsaw University of Technology (PL))

Paper

Slides Agnieszka_Twepp14.pdf

104 The CMS HCAL FEE Control Module

In the CMS Hadron Calorimeter, the Clock Control Module distributes the system clock to the readout modules and supports control and monitoring of the front-end electronics. This year an upgrade prototype, called ngCCM, has been built and used for a beam-test of the upgraded Forward HCAL. The ngCCM uses a 4.8 Gbps GBT-like optical link to the counting room along with a redundant mechanism in case the primary link fails. Notably, it is possible to reprogram FPGAs in the front-end via the GBT link. We describe the ngCCM and its integration within the Forward HCAL.

Speaker: Stephen Goadhouse (University of Virginia (US))

Poster The CMS HCAL FEE Control Module

105 Thermal Analysis of the Proto-VIPRAM2D Chip

Thermal analysis has been essential in designing reliable IC. This becomes even more critical when multiple thin dies are stacked together to form a 3D integration. This paper presents our latest work on thermal modeling, analysis, and simulations on the prototype Vertical Integrated PRAM (proto-VIPRAM2D) chip. We proposed a sub-circuit-block level thermal simulation approach using Fourier heat flow model, where one CAM cell is used as a unit heat source. This approach significantly reduces the simulation time and computing resources while providing efficient and accurate thermal/temperature simulations in both 2D and 3D IC scenarios.

Speaker: Tao Zhang (SMU)

Paper

Poster PosterThermal_TWEPP14[1].pdf

106 A 12GHz Low-Jitter LC-VCO PLL in 130nm CMOS

This paper presents a LC-VCO PLL designed in 0.13μm CMOS technology for multi-data rate serial link applications. The PLL covers a 5.6GHz to 13.4GHz tuning range by using two LC-VCO cores while remaining locked from -40°C to 85°C. At 25°C, the PLL has a RMS random jitter (RJrms) of 0.37pS at 11.44GHz. The integrated jitter is less than 0.7pS. The PLL consumes 50.88mW of power from a 1.2V supply at 12GHz.

Speaker: Prof. Jinghong Chen (University Of Houston, Texas)

Paper

Slides TWEPP_A_12GHz_Low-Jitter_LC-VCO_PLL_in_130nm_CMOS_.pdf TWEPP_A_12GHz_Low-Jitter_LC-VCO_PLL_in_130nm_CMOS_.pptx

107 FBCT Fast Intensity Measurement Using TRIC Cards

At the CERN PS complex, precise fast intensity measurements are very important in order to optimize the transfer efficiencies between the different accelerators. Over the last two years a complete renovation has been ongoing, where the old electronics, based on analogue integrators, have been replaced by a fully digital system enclosed in a single VME based card.This new system called TRIC (Transformer Integration Card) is based on a 12bit, 212MS/s ADC and an FPGA for the signal processing. Also located on the same board one finds a 250V/1.5W DCDC converter used to generate precise calibration pulses.

Speaker: Mr Juan Carlos Allica (CERN)

Paper

Poster TWEPP2014_c.pdf

108 JTAG-based Remote Configuration of an FPGA Over Optical Fibers

We present a remote FPGA-configuration method based on JTAG extension over optical fibers. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or software development. The method combines the advantages of the slow remote JTAG configuration and the fast local flash memory configuration. We have verified that we can successfully configure an FPGA 100-meter far away. The method will be used in the ATLAS liquid argon calorimeter upgrade Demonstrator. All components on the FPGA side are verified to meet the radiation tolerance requirements.

Speaker: Tiankuan Liu (Southern Methodist University)

Paper

Slides Poster_JTAG_TWEPP14.pdf

109 The Clock Distribution System for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade Demonstrator

A prototype Liquid-argon Trigger Digitizer Board (LTDB), called LTDB Demonstrator, has been proposed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog/Digital converters and four FPGAs with embedded multi-gigabit-transceivers on each Demonstrator need high quality clocks. A clock distribution system based on commercial components is being developed for the Demonstrator. The design of the clock distribution system is presented. The performance of the clock distribution system has been evaluated. The components used in the clock distribution system have been qualified to meet radiation tolerance requirements of the Demonstrator.

Speaker: Tiankuan Liu (Southern Methodist University)

Paper

Poster Poster_ClockDemo_TWEPP14.pdf

110 Development of the Read-out ASIC for Muon Chambers of the CBM Experiment

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power budget of 10mW per channel, area efficient 1.2 mW at 50 Msps 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and SAR ADC. The chip also includes the threshold DAC and the digital part.

Speaker: Evgeny Malankin (NRNU MEPhI)

Paper

111 Clock and Data Recovery Implementation and Testing for the Readout Control Unit 2 in ALICE TPC.

A new readout control unit for the ALICE TPC in Run-2 - the RCU2 - has been designed in order to increase data throughput and radiation tolerance. Since the TTCrx ASIC project is disbanded, new ways to recover clock and data was implemented and tested. Two methods have been applied, one using the internal fabric resources of the SmartFusion2 FPGA and the other using a commercial component, the ADN2814. Clock jitter from the SmartFusion2 recovery method has shown comparable results as the TTCrx jitter performance. However, neither of the solutions performed well enough under radiation to be applicable for the RCU2 without major modification.

Speaker: Christian Torgersen (University of Bergen (NO))

Paper

Poster poster.pdf

112 The Upgrade Plans and Challenges of the ATLAS First-level Trigger Towards the HL-LHC

The LHC plans to increase the design instantaneous luminosity by a factor of five. The ATLAS experiment will upgrade its trigger and DAQ systems to preserve the acceptance for electro-weak processes without increasing thresholds on the transverse momenta of physics objects. The new scheme includes additional hardware to decouple a short latency system from a longer latency one using the tracking information from a high-granularity tracker. The longer-latency system could also run calorimeter-based more pile-up resilient clustering trigger algorithms and the muon trigger system to increase momentum resolution using the precision tracking detectors.

Speaker: Per Olov Joakim Gradin (Uppsala University (SE))

Poster The_upgrade_plans_and_challenges_of_the_ATLAS_first-level_trigger_towards_the_HL-LHC(POSTER).pdf

113 PEALL4: A 4-channel, 12-bit, 40-MSPS, Power Efficient and Low Latency SAR ADC

The PEALL chip is a Power Efficient And Low Latency successive approximation register (SAR) ADC candidate designed for the upgrade of the ATLAS experiment at the CERN LHC. The full functionality of the converter is especially achieved by an embedded high-speed clock frequency conversion generated by the ADC itself. The design and test results of the PEALL chip implemented in a commercial 130nm CMOS process will be presented. The size of this four-channel ADC, with embedded voltage references and sLVDS output serializer, is 2.8x3.4 mm2, while the total power dissipation is less than 27mW per channel.

Speaker: Fatah Rarbi (IN2P3 / LPSC Grenoble)

Paper

114 The GBT-FPGA Core: Features and Challenges

Initiated in 2009 to emulate the GBTx serial link and test the first GBTx prototypes, the GBT-FPGA project is now a full library, targeting FPGAs from ALTERA and XILINX, allowing the implementation of one or several GBT links of 2 different types: “Standard” or “Latency-Optimized”. The first major version of this IP Core was released in April 2014. This paper presents the various flavours of the GBT-FPGA kit, and focuses on the challenge of providing a fixed and deterministic latency system both for clock and data recovery for all FPGA families.

Speaker: Manoel Barros Marin (CERN)

Paper

Poster gbt_fpga_twepp14_poster.pdf

115 The ATLAS Level-1 Muon Topological Trigger Information for Run 2 of the LHC

For run 2 of the LHC, the ATLAS Level-1 trigger system will include topological information on trigger objects in order to cope with the increased trigger rates. The existing Muon-to-Central-Trigger-Processor interface (MUCTPI) has been modified in order to provide coarse-grained topological information on muon candidates. A MUCTPI-to-Level-1-Topological-Processor interface (MuCTPiToTopo) has been developed to receive the electrical information and to send it optically to the Level-1 Topological Processor (L1TOPO). This poster will describe the different modules mentioned above and present results of functionality and connection tests performed.

Speaker: Marcos Vinicius Silva Oliveira (Juiz de Fora Federal University (BR))

Paper

Poster ATL-DAQ-SLIDE-2014-657.pdf

116 A Pattern Recognition Mezzanine Based on Associative Memory and FPGA Technology for L1 Track Triggering at HL-LHC

The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We propose a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

Speaker: Daniel Magalotti (Universita e INFN (IT))

Poster twepp_2014_v4.pdf

117 The VFAT3-Comm-Port : A Complete Communication Port for Front-end ASICs Intended for Use within the High Luminosity Radiation Environments of the LHC.

Intended for implementation within the VFAT3 ASIC; the VFAT3-Comm-Port offers a single port for clock, synchronization, fast and slow control commands as well as data and slow control readout. The paper initially describes the core design which could be offered for use as an IP block in other projects. It also discusses an encoding technique which provides unique comma characters and increases robustness to errors associated with Single-Event-Effects (SEEs) and Single-Event-Upsets (SEUs) during transmission. The second part describes the specific implementation of the Comm-Port within the VFAT3 chip.

Speaker: Mieczyslaw Maria Dabrowski (Warsaw University of Technology (PL))

Paper

Poster Poster_v2.0.pdf

118 Depleted Monolithic Active Pixel Sensors with LF 150 nm CMOS

We present the recent development of the depleted Monolithic Active Pixel Sensors, implemented with an L-Foundary 150 nm process. Unlike in the case of standard MAPS technologies, this process provides a high-resistive substrate that enables large signal and fast charge collection by drift in a 50 um – 100 um thick depleted layer, and the use of PMOS and NMOS transistors in the pixel cell without limitation. In order to evaluate the basic CMOS parameters and sensor characteristics, different pixel layouts and readout architectures were implemented. In this presentation, we will also report on the latest measurement results.

Speaker: Tetsuichi Kishishita (University of Bonn)

Paper

Poster TWEPP_v1.pdf

119 CMS ECAL Electronics Developments for HL-LHC

The High Luminosity LHC (HL-LHC) will provide unprecedented instantaneous and integrated luminosity. The CMS electromagnetic calorimeter (ECAL) will face a challenging environment at the HL-LHC: higher event pileup, higher radiation levels for the crystals and photodetectors, and a higher rate of anomalous signals from the APDs. To mitigate these challenges and maintain the excellent physics performance of the detector, a redesign of the ECAL electronics is planned, including an increase in trigger rate and latency.

Speaker: Magnus Hansen (CERN)

Paper

Poster ECAL_electronics_upgrade_poster_TWEPP14.pdf

120 Research and Design of the Electronics System for the Underground Dark Matter Detection Experiment in IHEP

The underground dark matter experiment in IHEP is direct detection of dark matter that using CsI(Na) as detector material, and rare nuclear recoil events of dark matter particles scattering on target material will be detected by photo-multiplier tubes (PMTs). This paper describes the electronics system structure we chosen for this detector; emphatically focus on the design of main modules that are high-speed ADC module and 2-level data acquisition module. Some performance results also are presented at the end.

Speaker: Dr Jun Hu (Institute of High Energy Physics, Chinese Academy of Sciences(IHEP,CAS))

Paper

Slides Hujun'poster_for_TWEPP14.pdf

121 Design and Testing of Combined GEM+CSC Trigger Algorithm Firmware for the CMS Muon Endcap System

With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require more complex trigger algorithms to handle the increased data rate while maintaining high data collection efficiency. Higher performance trigger electronics have already been deployed in the front-end, and advanced trigger logic is under development to take advantage of the capabilities in the new system. We report on the progress in development and simulation of the new CSC trigger algorithm, as well as plans for a combined GEM+CSC trigger proposed for phase 2 LHC operations.

Speaker: Aysen Tatarinov (Texas A & M University (US))

122 3D Simulation and Dopping Profile Measurements of Planar Pixel Sensors

Innovative edgeless planar pixel sensors for the High Luminosity LHC upgrade are under production. Through 3D TCAD simulation of the production process and electric field at the inside of the detector, combined with SiMS measurements, a calibration and complete insight of the new structures is achieved. Comparison between simulated data and experimental measurements allow a calibration of the process and a better understanding of the production. In addition, innovative bias grid geometries in classical planar pixel structures are studied a 3D approach while the question of efficiency drop in the region of the bias grid is addressed.

Speaker: Vagelis Gkougkousis (Universite de Paris-Sud 11 (FR))

Slides 3D_Simulation_and_Dopping_Profile_Measurements_of_Planar_Pixel_Sensors.pdf

123 Development of a Custom On-line Ultrasonic Vapour Analyzer and Flowmeter for the ATLAS Inner Detector, with Application to Cherenkov and Gaseous Charged Particle Detectors.

Sound velocity measurements can simultaneously determine gas composition and flow. We have developed ultrasonic analyzers with custom microcontroller-based electronics, currently used in the ATLAS detector control system, with numerous applications. Three instruments monitor C3F8 and CO2 coolant leak rates into the nitrogen envelopes of the ATLAS silicon microstrip and pixel detectors. Two instruments aid operation of the new thermosiphon coolant recirculator. One monitors air leaks into the low-pressure condenser. The other measures return vapour flow, and can measure C3F8/C2F6 blend composition, should this be needed to protect the silicon under increasing LHC luminosity. We describe these developments.

Speaker: Mr Sergey Katunin (PNPI St Petersberg)

Paper

124 ProtoVIPRAM2D: Realization and Testing

The challenge of the Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project is to increase pattern density through aggressive Vertical Integration. Our first step is to implement in conventional VLSI building blocks that can be used in 3D stacking. We are reporting on the first successful implementation of a conventional 2D demonstrator of the VIPRAM chip (protoVIPRAM2D). Detailed measurements achieved with a dedicated test card benchmark the design in terms of yield, speed and power consumption. Measurements are promising for Level 1 Tracking Trigger applications in LHC experiments. The results show that these building blocks are ready for 3D stacking.

Speaker: Tiehui Ted Liu (Fermi National Accelerator Lab. (US))

Paper

Slides TWEPP_2014_POSTER_VIPRAM.V2.pdf TWEPP_2014_POSTER_VIPRAM.V2.pptx

125 Demonstrator System for the Phase-I Upgrade of the Trigger Readout Electronics of the ATLAS Liquid-Argon Calorimeters

The trigger readout electronics of the ATLAS LAr Calorimeters will be improved for the Phase-I luminosity upgrade of the LHC to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being set up which is planned to be installed on the ATLAS detector during the upcoming LHC run. Results from system tests of the analog signal treatment, the trigger digitizer, the optical signal transmission and the FPGA-based back-end are reported.

Speaker: Jasmin Fragnaud (Centre National de la Recherche Scientifique (FR))

Poster ATL-COM-LARG-LAr_Demonstrator.pdf

126 NaNet: a Configurable NIC Bridging the Gap Between HPC and Real-time HEP GPU Computing

NaNet is a FPGA-BASED PCIe Network Interface Card with GPUDirect capability featuring a configurable set of channels: standard 1/10GbE and custom 34Gbps APElink and 2.5Gbps optical with deterministic latency KM3link. GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing. We will describe NaNet architecture and its performances, and present two use cases for it: the GPU-based low-level trigger for the RICH detector in NA62 experiment and the on-/off-shore data link for KM3 underwater neutrino telescope.

Speaker: Alessandro Lonardo (Universita e INFN, Roma I (IT))

Paper

18:45 Group Photo and Conference Dinner

Thursday 25 September

Plenary 5

Convener: Alessandro Marchioro (CERN)

127 A Hybrid CMOS Pixel Detector for High-Speed X-Ray Imaging of Inertial Confinement Fusion Experiments

A hybrid pixel detector with 25µm pitch has been developed to record multiple x-ray images with integration times as short as 1ns to measure the implosion dynamics of inertial confinement fusion experiments. The 1024x448 pixel detector is fabricated with Sandia’s 0.35µm technology and consists of a silicon diode array directly bonded to a CMOS ASIC. The ASIC incorporates a global shutter with adjustable integration and interframe timing and 2-frame in-pixel analog storage with a maximum of more than 1 million electrons per frame. Next-generation cameras are being designed and fabricated that will provide 4 and 8 frames per pixel.

Speaker: John Porter (Sandia National Laboratories)

ASICs: A5a

Convener: Mr Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

128 FEAST2: a Production Grade 10W Radiation Tolerant DC/DC Converter

A 10W converter ASIC, called FEAST2, has been developed for LHC experiment upgrades. It has been proved to be tolerant up to more than 500Mrad(Si) TID and an integrated particle fluence of 5x1014n/cm2. FEAST2 has been also tested for SEE up to a LET=64MeVcm2mg-1 without output power interruptions. FEAST2 is embedded in two modules called FEASTMP and FEASTMN (with positive and negative output voltage respectively). FEASTMP is today in production and a first lot of 1000 samples will be available soon. FEAST2 functional and radiation tests will be shown and FEASTMP production peculiarities will be discussed.

Speaker: Federico Faccio (CERN)

Slides PresentationTWEPP14_.pdf

129 Development of a Lower Power 5.12 Gbps Data Serializer and Wireline Transmitter Circuit for VeloPix Chip

We report on a prototype of a 5.12 Gbps Data Serializer and Wireline Transmitter circuit in 130 nm CMOS technology. A shift-register-free topology has been used in the serializer block. A 16-to-1 multiplexer selects one bit of data at a time from either a posedge triggered section or a negedge triggered section of a 16-bit input register clocked at 320 MHz. The serializer consumes only 15 mW of power and the wireline transmitter with pre-emphasis consumes 45 mW. The authors will explain the circuit design aspects and present experimental results.

Speaker: Mr Vladimir Gromov (Nikhef)

Paper

Slides TWEPP2014_Gromov_25_09_14.pdf TWEPP2014_Gromov_25_09_14.ppt

Trigger: B5a

Convener: Stefano Veneziano (Universita e INFN, Roma I (IT))

130 VIPRAM Architecture and Its Implementation: from 2D to 3D

The VIPRAM approach has, from the beginning, attempted to increase pattern density and decrease power density through Vertical Integration. To mitigate issues implicit in adopting an emerging technology, a flexible architecture has been developed that can be implemented in either conventional or Vertically Integrated VLSI. This allows us to bring the system interface to maturity at an early stage while, at the same time, making steady progress towards the final VIPRAM solution. This is particularly important for Level 1 Tracking Trigger applications. The talk will cover the architecture, system interface and implementation that takes the design from 2D to 3D.

Speaker: Jim Hoff (Fermilab)

Slides VIPRAM_2D-3D.V6.pptx

131 Pulsar II: An FPGA-based Full Mesh ATCA Processor Board

The Pulsar II is an FPGA-based full mesh ATCA processor board capable of creating a scalable architecture abundant in flexible, high bandwidth interconnections. The resulting full mesh interconnection among FPGAs is a natural fit for spatial and time multiplexed data processing. The design has been motivated by silicon-based tracking trigger needs for the LHC experiments. Near term applications are the ATLAS FTK Data Formatter, which requires spatial data multiplexing, and the CMS Level-1 tracking trigger vertical slice demonstration, which also demands extensive time multiplexing. In this talk we present the board design and performance study results.

Speaker: Jamieson Olsen (Fermilab)

Slides twepp_pulsar2.pptx

10:40 Coffee break

Logic & Packaging: B5b

Convener: Ken Wyllie (CERN)

132 The C-RORC PCIe Card and its Application in the ALICE and ATLAS Experiments

The ALICE and ATLAS DAQ systems read out detector data via point-to-point serial links into custom hardware modules, the ALICE RORC and ATLAS ROBIN. To meet the increase in operational requirements both experiments are replacing their respective modules with a new common module, the C-RORC. This card, developed by ALICE, implements a PCIe Gen 2 x8 interface and supports twelve optical links via three QSFP transceivers. This paper presents the design of the C-RORC, its performance and its applications in the ALICE and ATLAS experiments.

Speaker: Heiko Engel (Johann-Wolfgang-Goethe Univ. (DE))

Paper

Slides TWEPP_Presentation_20140925.pdf

133 New Production Methods for Silicon Bare Modules for the CMS Pixel Detector, Upgrade Phase I

This paper describes the production process and results for the fourth barrel layer for the CMS silicon pixel detector, upgrade phase I. The fourth layer will be produced in distributed detector production lab (DDTL) at KIT and DESY. Both research centers have commonly developed and investigated new production processes, including SAC solder bump jetting, gold stud bumping and precoat by powder processes (PPS) to bump the sensor tiles and prepare them for the flip-chip process. First production samples with the new digital ROCs have been produced and tested with a 90Sr source, indicating a yield of 100%.

Speaker: Thomas Blank (KIT)

Paper

ASICs: A5b

Convener: Mr Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

134 8-Gbps-per-channel Radiation-tolerant VCSEL Drivers for the LHC Detector Upgrade

We present the designs and testing results of a single-channel and a two-channel VCSEL driver and a four-channel array VCSEL driver ASICs for the LHC detector upgrade. All ASICs are fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 are designed to drive differentially VCSEL TOSAs, whereas LOCld4 is designed to drive a VCSEL array die. LOCld1/LOCld2 and LOCld4 pass the 10-Gbps and 8-Gbps eye masks, respectively. The radiation tolerance of LOCld1 has been qualified with x-ray and neutron beam test.

Speaker: Ms Xiaoting Li (Central China Normal University, Southern Methodist University)

Paper

Slides talk_VCSEL_driver_.pdf

135 A 10 Gb/s Laser Driver in 130 nm CMOS Technology for High-energy Physics Applications

The GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system on the transmitter side. As part of design efforts towards the upgrade of electrical components for the future LHC experiments, a 10 Gb/s GBLD (GBLD10) was developed in 130 nm CMOS technology. The GBLD10 is based on the distributed-amplifier architecture with pre-emphasis to achieve data rates up to 10 Gb/s and is capable of driving VCSELs with modulation currents up to 12 mA. The pre-emphasis function, to compensate for capacitive loads, is designed with the capacitive degeneration technique.

Speaker: Ping Gui (SMU)

Paper

Slides 05_GUI.pdf

12:00 Lunch

Plenary 6

Convener: Francois Vasey (CERN)

136 CMOS Pixel Sensors for Particle Tracking and Vertexing : Achievements and Perspectives

CMOS Pixel Sensors (CPS) exploit the features of CMOS industry to achieve highly granular and thin sensors with integrated front-end electronics. The concept is being developed since the late nineties and benefits from the steady evolution of industrial ASIC and imager industry. The talk will overview intrinsic features of CPS, highlighting the technology potential. It will next discuss pros and cons of various charge collection system and readout designs. The talk will then summarise achieved detection performances of existing devices manufactured in different imaging processes. Its last part will provide an outlook mentioning requirements of future devices using CPS.

Speaker: Marc Winter (Institut Pluridisciplinaire Hubert Curien (FR))

Slides mwinter-review-cmos_1.pdf

Optoelectronics and Links: A6

Convener: Francois Vasey (CERN)

137 Versatile Transceiver and Transmitter Production for Phase I Upgrades of LHC Experiments

Production of the Versatile transceiver and twin transmitter modules for use in the readout and control systems of upgrading LHC detector systems is starting. We review the VTRx and VTTx flavours and their customer base as well as commercial actions being taken to procure parts and assemblies. The detailed production plan for delivering known good parts along with the full quality assurance plan will be shown.

Speaker: Dr Jan Troska (CERN)

Slides VTXx_status_twepp2014.pdf

138 Design, Production, and Reliability of the New ATLAS Pixel Opto-Boards

New fiber optic transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed on the ATLAS pixel detector and for the new pixel layer. Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver/driver ASICs. The new opto-board design benefits from the first generation production and operational experience and contains several improvements. Most of the new opto-boards have been installed with completion expected in early June. We will present the design, production and operational experience, and reliability study of the new opto-boards.

Speaker: Prof. Kock Kiam Gan (Ohio State University (US))

Paper

Slides TWEPP2014_Gan.pdf

139 The VCSEL Based Array Optical Transmitter (ATx) Development Towards 120 Gbps Link for the High-Luminosity LHC (HL-LHC) Experiments.

A compact radiation-tolerant Array Optical transmitter module (ATx) integrating micro optics, a VCSEL array and a custom driver is demonstrated. ATx uses an edge warp substrate for the electrical interface and micro-lens array for the optical interface. A simple, high-accuracy and reliable active alignment method for micro-lens assembly is introduced. The coupling insertion loss is less than -3 dB with channel-to-channel variation less than 1 dB. Data transmission of 8Gbps per channel is measured. ATx will be irradiated under x-ray to 10 Mrad(SiO2) total dose to evaluate the radiation induced power penalty.

Speaker: Tiankuan Liu (Southern Methodist University)

Paper

Slides Slides__ATx_TWEPP14.pdf

Power, Grounding and Shielding: B6

Convener: Philippe Farthouat (CERN)

140 Radiation-Hard Power Electronics for the ATLAS New Small Wheel

The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the ATLAS forward region. The large LV power demands of the NSW necessitate a point-of-load architecture with on-detector power conversion. The radiation load and magnetic field of this environment, while significant, are nevertheless still in the range where commercial-off-the-shelf power devices may suffice. We present studies on the radiation-hardness and magnetic-field tolerance of several candidate buck converters and linear regulators. Device survival and performance are characterized when exposed to gamma radiation, neutrons, protons and magnetic fields.

Speaker: Ryan Christopher Edgar (University of Michigan (US))

Paper

Slides TWEPP2014.pdf

141 The DC-DC Conversion Power System of the CMS Phase-1 Pixel Upgrade

The CMS Phase-1 Pixel detector, to be installed in the year-end technical stop 2016/17, will feature a power system based on DC-DC conversion. The power system, including the final DC-DC converters based on the FEAST2 ASIC by CERN, DC-DC main boards, power distribution PCBs, power supplies and thermal management, will be described, and the performance of the components will be discussed. The results of a system test, in which the complete power chain with final components is used to power CMS upgrade pixel modules, will be presented.

Speaker: Dr Katja Klein (RWTH Aachen)

Paper

Slides KatjaKlein_TWEPP14.pdf KatjaKlein_TWEPP14.pptx

142 HVMUX, the High Voltage Multiplexing for the ATLAS Tracker Upgrade

The increased luminosity of the HL-LHC will require more channels in the upgraded ATLAS Tracker, as a result of the finer detector segmentation.Thus, a more efficient power distribution and HV biasing of the sensors are among the many technological challenges facing the ATLAS Tracker Upgrade. A number of approaches, including the sharing of the same HV line among several sensors and suitable HV switches, along with their control circuitry, are currently being investigated for this purpose. The proposed solutions along with latest test results and measurements will be described.

Speaker: Dr Enrico Giulio Villani (STFC RAL)

Paper

Slides EGV_HVMUX.pdf EGV_HVMUX.pptx

16:05 Coffee Break

Microelectronics User Group

Convener: Kostas Kloukinas (CERN)

143 News on Foundry Access Services via CERN

Speaker: Kostas Kloukinas (CERN)

Slides MUG_TWEPP2014_intro_Kloukinas.pdf (Protected) MUG_TWEPP2014_intro_Kloukinas.pptx (Protected)

144 Design Kits and IP Blocs for Supported IC Technologies

Speaker: Sandro Bonacini (CERN)

Slides TWEPP2014-PDK-IPblocks-public.pdf (Protected)

145 Plans for Radiation Characterization of Supported IC Technologies

Speaker: Federico Faccio (CERN)

Slides MUGTalk.pdf

146 RD53 Activities on IP Blocks and Radiation Qualification for the 65nm Technology

Speaker: Jorgen Christiansen (CERN)

Slides RD53_MUG_2014.pdf RD53_MUG_2014.pptx

147 Europractice Software Services for the HEP community

Speaker: Emily Van der Heijden (STFC)

148 Open Discussion

Power Working Group

Convener: Magnus Hansen (CERN)

Friday 26 September

Plenary 7

Convener: Jorgen Christiansen (CERN)

Plenary 8

Convener: Philippe Farthouat (CERN)

149 Sensors and Front-end Electronics for the Large Synoptic Survey Camera

The Large Synoptic Survey Telescope (LSST) is the flagship US ground-based optical astronomy facility for the next decade. At the heart of its 3Gpixel camera are the 21 focal plane modules, each of which is a fully autonomous and serviceable unit comprised of 9 CCDs and 144 channels of low-noise processing electronics. To minimize noise, power, and beam obscuration the electronics is ASIC-based and operates in shared vacuum space in close proximity to the CCDs. Successful demonstration of an end-to-end prototype meeting its noise, power, speed, and compactness goals is presented in this talk.

Speaker: Dr Paul O'Connor (Department of Physics)

Slides 01_CONNOR.pdf 01_CONNOR.pptx

150 Active Pixel Sensors for the ATLAS Upgrade - Concepts and Test Chip Results

We explore the concept of using deep-submicron HV-CMOS and/or imaging processes to produce a drop-in replacement for radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a readout chip. This approach yields most advantages of MAPS, without the complication of full integration on a single chip. After outlining the basic concept and the design of recent test ASICs, characterization results after irradiation up to 1e16 neq/cm2 and 1GRad will be presented, and future plans with active sensors for the ATLAS Upgrade will be discussed.

Speaker: Daniel Muenstermann (Universite de Geneve (CH))

Slides Muenstermann_HV-CMOS_TWEPP.pdf

10:35 Coffee break

Plenary 9

Convener: Philippe Farthouat (CERN)

151 10 MGy Total Dose Evaluation of 65 nm CMOS Technology for the High Luminosity LHC Upgrades

The radiation tolerance of the 65 nm bulk CMOS devices is investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 10 MGy and the implications on the DC performance of n and p channels transistors are presented. For a dose level of 10 MGy, transconductance loss is near 100% for the narrow channel pmos device making the device completely off. Annealing at 100°C helps devices to recover driving capabilities but the threshold voltage is increased to 1 V for the narrowest pmos device reducing hence the noise margin in digital circuits.

Speaker: Mohsine Menouni (Centre National de la Recherche Scientifique (FR))

Paper

Slides CPPM_TWEPP2014_TID65_V4.pdf

152 Neutron and X-ray Irradiation of Silicon Based Mach-Zehnder Modulators

We report on our recent investigation into the potential for using silicon-based Mach-Zehnder modulators in the harshest radiation environments of the High-Luminosity LHC. The effect of ionizing and non-ionizing radiation on the performance of the devices have been investigated using the 20 MeV neutron beam line at the Cyclotron Resource Centre in Louvain-La-Neuve and the X-ray irradiation facility in the CERN PH department to a total fluence of 1.2e15 n/cm2 and a total ionizing dose of 2 MGy.

Speaker: Sarah Seif El Nasr (CERN, University of Bristol (GB))

Paper

Slides TWEPP_2014_SStorey.pdf

Closeout

153 Closeout

Speaker: Jorgen Christiansen (CERN)

Slides 05_CHRISTIANSEN.pdf 05_CHRISTIANSEN.pptx

154 Closeout from local committee

Speaker: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

Closeout: from Local Organizer