TWEPP 2021 Topical Workshop on Electronics for Particle Physics
On-line, from 20 to 24 September 2021
The workshop covers all aspects of electronic systems, components and instrumentation for particle and astro-particle physics experiments such as: electronics for particle detection, triggering, data-acquisition systems, accelerator and beam instrumentation.
Operational experience of electronic systems and R&D in electronics for LHC, High Luminosity LHC, FAIR, neutrino facilities and other present or future accelerator projects are the major focus of the workshop.
The purpose of the workshop is:
- Present original concepts and results of research and development for electronics relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities;
- Review the status of electronics for running experiments and accelerators;
- Identify and encourage common efforts for the development of electronics;
- Promote information exchange and collaboration in the relevant engineering and physics communities.
The main topics of the workshop will be recent research and developments in the following areas:
- Highly integrated detectors and electronics;
- Custom Analogue and Digital Circuits;
- Programmable Digital Logic Applications;
- Optoelectronic Data Transfer and Control;
- Packaging and Interconnect Technologies;
- Radiation and Magnetic Field Tolerant Systems;
- Testing and Reliability;
- Power Management and Conversion;
- Grounding and Shielding;
- Design Tools and Methods.
The workshop programme will include invited plenary talks, sessions for oral presentations and poster presentations. The workshop programme will be modified to the number and kind of submitted abstracts to adapt to the online format of the workshop.
No attendance fee will be charged, however registration is mandatory to access the workshop and off-line documentation.
Registration is already open and can be accessed here: https://indico.cern.ch/event/1019078/registrations
Authors are invited to submit abstracts and summaries describing original developments and new contributions, including recent progress, in the workshop topic areas.
Abstracts (max. 100 words long) and summaries (max. 500 words long) along an optional file containing diagrams or plots must be submitted through the Integrated Digital Conference tool at https://indico.cern.ch/e/twepp2021
The summary will be the basis for paper selection. It should be complete and describe the work, its relevance to one or more of the workshop topics and important conclusions. A submission without comprehensive summary will not be considered.
The extended deadline for submissions is May 16, 2021
Abstracts will be made available at the time of the workshop and will include all contributions selected for either oral or poster presentation.
The proceedings of the workshop will be published in a peer reviewed Journal.
Enquiries concerning the workshop scientific programme and submissions can be directed to the Workshop Secretariat, by email at twepp@cern.ch
Scientific organisation
A. Kluge (CERN, CH, Chair)
J. Alme (UiB, NO)
J.P. Cachemiche (CPPM–IN2P3, FR)
H. Chen (BNL, US)
W. Dabrowski (AGH, PL)
S. Danzeca (CERN, CH)
M. French (RAL, UK)
P. Gui (SMU, US)
M. Hansen (CERN, CH)
C. G. Hu (IPHC-IN2P3, FR)
G. Iles (Imperial College, UK)
C. Joram (CERN, CH)
A. Ricci (CERN, CH, Secretary)
A. Rivetti (INFN, IT)
W. Snoeys (CERN, CH)
F. Vasey (CERN, CH)
K. Wyllie (CERN, CH)
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Introduction
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Introduction 20mSpeaker: Alex Kluge (CERN)
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Systems, Planning, Installation, Commissioning and Running ExperienceConvener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
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11:40
The CMS Inner Tracker electronics system development and tests 16m
A new Silicon Tracker will be built for the Phase 2 Upgrade of the CMS experiment. The innermost part, called the Inner Tracker, will be featuring high-granularity pixelated silicon sensors and will need to cope with extreme radiation levels and hit rates. The pixel electronics system is based on innovative solutions such as a new pixel ASIC developed by the RD53 collaboration, the novel serial powering scheme and advanced technologies for the high bandwidth readout system. The recently optimised design of the CMS Inner Tracker electronics system will be presented along with system test results with prototype components.
Speaker: Stella Orfanelli (CERN) -
12:00
Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC 16m
To meet new TDAQ buffering requirements and withstand the high expected radiation doses at the high-luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. Developments of low-power preamplifiers and shapers and of a low-power 40 MHz 14-bit ADCs are ongoing. The signals will be sent at 40 MHz to the off-detector electronics, where FPGAs connected through high-speed links will perform energy and time reconstruction. The data-processing, control and timing functions will be realized by dedicated boards. Results of tests of front-end component prototypes will be presented, along with design studies on the off-detector readout system.
Speaker: Fabrice Gensolen (Aix Marseille Univ, CNRS/IN2P3, CPPM, Marseille, France) -
12:20
The Mu3e Detector 16m
The Mu3e experiment searches for the lepton flavour violating decay µ→ eee with an ultimate aimed sensitivity of 1 event in 10^16 decays. This goal can only be achieved by reducing the material budget per tracking layer to X/X0 ≈ 0.1%. For this purpose, the vertex detector is based on HV-MAPS thinned to 50 µm. Also, the powering and data transmission is performed by means of kapton-aluminum HDIs, which serve as mechanical support as well. This talk will show the detector concept, focusing on the technical aspects of the pixel tracker and its several challenges.
Speaker: Luigi Vigani (Ruprecht Karls Universitaet Heidelberg (DE)) -
12:40
The Apollo ATCA design for CMS Track Finder and Pixel Readout at the HL-LHC 16m
The challenging conditions of High-Luminosity LHC (HL-LHC) require tailored hardware designs for the trigger and data acquisition systems. The Apollo platform features a "Service Module" (SM) with a powerful system-on-module (SoM) computer that provides standard ATCA communications and application-specific "Command Module"s (CM) with large FPGAs and high speed optical fiber links. The CMS design of Apollo will be used for Track Finder and pixel readout. It features up to two large FPGAs and 100+ optical links with speed up to 25 Gbps. This presentation will give updates on the design and show link quality results and power and thermal performance.
Speaker: Dr Rui Zou (Cornell University (US))
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Lunch break 1h
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Systems, Planning, Installation, Commissioning and Running ExperienceConvener: Ken Wyllie (CERN)
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Recent results from the first lpGBT-based prototype of the End-of-Substructure card for the ATLAS Strip Tracker Upgrade 16m
The building blocks of the upgraded ATLAS Strip Tracker for HL-LHC are modules that host silicon sensors and front-end ASICs. The modules are mounted on carbon-fibre substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card on each substructure connects up to 28 differential data lines at 640 Mbit/s to lpGBT and VL+ ASICs that provide data serialisation and 10 GBit/s optical data transmission to the off-detector systems respectively. Prototype EoS cards have been designed and extensively tested using lpGBT and VL+ prototypes. The status of the electronics design and recent test results are presented.
Speaker: Lars Rickard Strom (Deutsches Elektronen-Synchrotron (DE)) -
14:20
Readout electronics for the CMS Phase II Endcap Calorimeter: system overview and prototyping experience 16m
The frontend readout system for the silicon section of the CMS Phase II Endcap Calorimeter faces unique challenges due to the high channel count and associated bandwidth, limited physical space, as well as radiation tolerance requirements. This presentation will give an overview of the frontend electronics design and will discuss the recent experience obtained from the first test system that integrates the HGCROC2 readout ASIC, lpGBT, and VTRX+ in a realistic manner, linking together prototypes of the hexaboard, engine board, and wagon board.
Speaker: Nadja Strobbe (University of Minnesota (US)) -
14:40
Upgrade of the RPC detectors’ data collection and transmission electronics for the ATLAS experiment at High Luminosity LHC 16m
RPC detectors are used to trigger muons in the ATLAS Muon Spectrometer barrel region. The foreseen HL-LHC operation imposes replacing their trigger and readout electronics with a data collector and transmitter (DCT) system, which implements the LPGBT optical link to handle data bandwidth up to 10.24Gb/s. A testing system will be implemented to assess all DCT prototypes and mass production. Since the first DCT prototype is under irradiation tests, a methodology has been developed that renders feasible indispensable implementations towards the complete validation of the functionalities of the DCT and of any board that implements the LPGBT.
Speaker: Ioannis Mesolongitis (University of West Attica (GR)) -
15:00
The CMS HGCAL Silicon Region Architecture Specification and Optimisation 16m
An overview of the electronics readout/trigger architecture for the CMS HGCAL will be given. To respond to physics performance requirements, data rates, trigger-primitive generation and radiation tolerance has been extremely challenging. Each HGCAL endcap includes ∼300m² of active silicon in 50 layers, with a largely inhomogenous layout with limited commonality between layers. An agile, python-based counting scheme was implemented that creates tables of component counts. These are subsequently incorporated in the architecture specifications document and costbook, providing critical input to the mechanical design and integration optimisation.
Speaker: Matthew Noy (CERN)
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Break 20m
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Systems, Planning, Installation, Commissioning and Running ExperienceConvener: Hucheng Chen (Brookhaven National Laboratory)
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The JUNO experiment and its readout electronics system 16m
The main goal of the Jiangmen Underground Neutrino Observatory (JUNO) under construction in China is to determine the neutrino mass hierarchy. The detector consists of 20 ktons of liquid scintillator instrumented by 17612 20-inch photomultiplier tubes, and 25600 3-inch small PMTs, with photocathode coverage of 77%. The electronics system is separated into two main parts. The front-end system, sitting under water, performs analog signal processing. The backend electronics system, sitting outside water, consists of the DAQ and the trigger. The design of the electronics system as well as the current production status will be reported in the presentation.
Speakers: Pierre-Alexandre Petitjean, Pierre-Alexandre Petitjean (Université Libre de Bruxelles) -
16:00
The CMS Barrel Calorimeter Processor demonstrator (BCPv1) board evaluation 16m
For the Phase 2 of the LHC, the central electromagnetic (EB) and hadronic (HCAL) calorimeters of the CMS experiment require a new back-end electronics for its readout. The first version of the ATCA-based blade, the Barrel calorimeter processor (BCPv1), has been developed with a large flexibility to allow evaluation of the different strategies. The performance of the optical links as well as clock distribution options are presented. BCPv1 is tested together with new Front-End and Trigger boards, as well as with the DAQ and trigger interface board, namely DTH, in order to demonstrate that it meets the required specifications.
Speaker: Nikitas Loukas (University of Notre Dame (US)) -
16:20
High-accuracy 4D particle trackers with Resistive Silicon Detectors (AC-LGADs) 16m
Future particle trackers will have to measure concurrently position and time with unprecedented resolutions, approximately 5 microns and 10 ps respectively. A promising good candidate are the AC-LGADs, silicon sensors of novel design, with internal gain and an AC-coupled resistive read-out to achieve signal sharing among pads. This design leads to a drastic reduction of read-out channels, has an intrinsic 100% fill factor, and adapts easily to any read-out geometry. I will present the challenges in the design, the signal formation, recent test results, and the reconstruction techniques that exploit the distributed nature of the signal, including machine learning.
Speaker: Roberta Arcidiacono (Universita e INFN Torino (IT)) -
16:40
Front-end hybrid designs for the CMS Phase-2 Upgrade towards the production phase 16m
Sixteen thousand 2S front-end hybrids and twelve thousand PS front-end hybrids will be produced for the CMS Tracker Phase-2 Upgrade. The hybrids consist of flip-chips, passives and mechanical components mounted on a flexible substrate, laminated onto carbon-fibre stiffeners with thermal expansion compensators. In the prototyping phase, several critical issues have been solved to manufacture these complex circuits. Final designs are now reaching readiness for the full-scale production. High-density circuit design practices, lessons learned during the prototyping phase and different improvements for manufacturability will be presented in this contribution.
Speaker: Mark Istvan Kovacs (CERN) -
17:00
Power, Readout and Service Hybrids for the CMS Phase-2 Upgrade 16m
The CMS Tracker Phase 2 Upgrade modules integrate DCDC powering stages and an optical transceiver to power and control the front-end hybrids. The strip-strip (2S) module contains a Service Hybrid (2S-SEH) with two stage DC-DC power conversion, an lpGBT with optical interface (VTRx+), high voltage biasing and temperature sensor ports. The pixel-strip (PS) module utilizes a separate two stage DCDC converter circuit (PS-POH) and a Readout Hybrid (PS-ROH) containing the communication interface. The design and performance of these three hybrids and their integration in their respective modules will be presented.
Speaker: Angelos Zografos (CERN)
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Systems, Planning, Installation, Commissioning and Running ExperienceConvener: Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
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Prototype Design of Timing and Fast Control in the CBM experiment 16m
The Compressed Baryonic Matter (CBM) experiment is designed to handle interaction rates of up to 10 MHz and up to 1 TB/s of raw data generated. With free-streaming data acquisition in the experiment and beam intensity fluctuations, it is expected that occasional data bursts will surpass bandwidth capabilities of the Data Acquisition System (DAQ) system. In order to preserve event data, the bandwidth of DAQ must be throttled in an organized way with minimum information loss. The Timing and Fast Control (TFC) system provides a latency-optimized datapath for throttling commands and distribute a system clock together with a global timestamp.
Speaker: Vladimir Sidorenko (Karlsruhe Institute of Technology) -
12:00
CMS Phase-2 data acquisition, clock distribution, and timing: prototyping result and perspectives 16m
The CMS detector will undergo a major upgrade for Phase-2 of the LHC program: the HiLumi LHC. The Phase-2 CMS back-end electronics will be based on the ATCA standard, with node boards receiving the detector data from the front-ends via custom,
radiation-tolerant, optical links. An ATCA hub board, the DAQ and Timing Hub, will provide the interface between the back-end nodes and the central Trigger, Timing, and DAQ systems. This paper presents the progress on the development towards the DTH design. Measurements are presented showing the performance achieved for all main DTH tasks: clock distribution, DAQ throughput, and hub-to-node networking.Speaker: Jeroen Hegeman (CERN) -
12:20
The Scalable Readout System as a common initiative - a personal review 16m
When the RD51 collaboration formed in 2008, the community initiated efforts for a standardised common readout system, the Scalable Readout System (SRS). The APV25 chip, originally designed for the CMS silicon strip detector, was the working horse within the first decade reading out gaseous detectors. Meanwhile, the VMM chip has taken over and further ASICs were (Timepix, SiPMs) or are currently (Timepix3, SAMPA) included. The SRS found many applications, not only in its core field.
I will review the system and collaborative effort from the perspective of a user and developer involved over the last decade.Speaker: Michael Lupberger (University of Bonn (DE)) -
12:40
FELIX: the new ATLAS readout system from Run 3 to High Luminosity LHC 16m
The Front-End Link eXchange (FELIX) system is a new ATLAS DAQ component designed
to for detector readout in the High-Luminosity LHC era. FELIX acts as the interface
between the data acquisition, detector and trigger timing systems. FELIX routes data between
custom serial links from front-end electronics to data collection and processing components
via a commodity switched network. This presentation covers the current design of FELIX and its
evolution for High-Luminosity LHC, including the development of a new hardware platform
based on a Xilinx Versal Prime FPGA, incorporating PCIe Gen4 and a new 25Gbps optical link
standard.Speakers: Frans Schreuder, Frans Schreuder (Nikhef National institute for subatomic physics (NL))
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Lunch break 1h
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Systems, Planning, Installation, Commissioning and Running ExperienceConvener: Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
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14:00
Installation, integration and first operating experiences of the ALICE ITS Upgraded Readout System 16m
The ALICE Inner Tracking System has gone through a significant upgrade for the upcoming third running period of the CERN LHC. The new detector consists of seven layers of high-granularity pixel sensors, while 192 custom FPGA-based readout units control the sensors and transmit the data upstream for analysis. This contribution describes the current system status and the expertise gained by moving from commissioning to the installation and throughout the data-taking preparation period, focusing on the intricate integration with other system components. Furthermore, we outline strategies applied to identify and handle various error conditions of the readout system.
Speaker: Ola Slettevoll Groettvik (CERN)
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Power, Grounding and ShieldingConvener: Magnus Hansen (CERN)
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Serial powering and signal integrity characterisation for the TEPX detector for the Phase-2 CMS Inner Tracker 16m
The entire CMS silicon pixel detector will be replaced to operate at High Luminosity LHC. The novel scheme of serial powering will be deployed to power the pixel modules and new technologies will be used for a high bandwidth readout system. In this contribution the new TEPX detector will be presented, with particular focus on a novel concept to provide both power and data connectivity to the modules through a disk-shaped PCB. As TEPX also features the longest serial powering chains in IT, an emphasis on serial powering results will be shown, together with signal integrity and data transmission performance.
Speaker: Dr Arne Christoph Reimers (Universitaet Zuerich (CH)) -
14:40
rPOL2V5: a compact radiation-hard resonant switched-capacitor DC-DC converter for the CMS HGCAL 16m
A high power density resonant switched capacitor DC-DC converter (rPOL2V5) has been developed as a possible alternative to the bPOL2V5, of particular interest to the CMS High-Granularity Calorimeter (HGCAL) due to the relatively compact 12nH air-core inductor that it requires. The converter is based on an ASIC developed in a 130nm CMOS technology. It is powered by a 2.5V input, it can supply a maximum current of 3A to the output voltage range 1-1.5V. This work presents the strategies adopted at ASIC and PCB level to bring the converter to maturity, and the electrical and radiation characterization results.
Speaker: Stefano Caregari (National Central University (TW)) -
15:00
48V input rad-hard DCDC converters for HEP experiments: development and results 16m
Two new radiation-hard DCDC converters are in development, which tolerate a higher input voltage (up to 48V) and provide a larger output power compared to existing solutions. They are called bPOL48V and rPOL48V, and they employ Gallium Nitride devices. bPOL48V can provide 12A of output current with 90% efficiency and is close to production readiness, while rPOL48V is in an early stage of development and is designed to provide an output current up to 30A. A linear regulator (linPOL48V) able step down the voltage from up to 48V with maximum output current of 200mA has been also designed and tested.
Speaker: Pablo Daniel Antoszczuk (CERN)
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Break 20m
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Optoelectronics and LinksConvener: Francois Vasey (CERN)
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Towards Optical Data Transmission for High Energy Physics Using Silicon Photonics 16m
Future upgrades of CERN Experiments will require low power optical data links to support ever-increasing data-rates at ever-higher radiation levels. Silicon Photonics is a CMOS optoelectronics technology compatible with such requirements. We present the results of an optical transceiver proof of concept based on a Silicon Photonic Integrated Circuit coupled to existing radiation tolerant ASICs.
Speaker: Theoni Prousalidi (National Technical Univ. of Athens (GR)) -
16:00
40 Gbps optical transceiver for particle physics experiments 16m
QTRx is an optical transceiver for particle physics experiments. The transmitters, each at 10 Gbps, are based on QLDD and 1x4 VCSEL array. The receivers, with data rates between 2.56 Gbps and 10 Gbps, are based on QTIA and 1x4 photodiode array, GaAs or InGaAs. QTRx is 20 mm × 10 mm × 5 mm and couples to an MT fiber connector. Preliminary tests indicate that QTRx meets design data rates with a power of 124 mW per Tx channel at 10 Gbps and 72 mW per Rx channel at 2.56 Gbps. More tests, including irradiation, will be carried out.
Speaker: Mr Xing Huang (Southern Methodist University (SMU)) -
16:20
A prototype optical link board with redundancy design for the ATLAS Liquid Argon Calorimeter Phase-2 Upgrade 16m
A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board. The board has 22 simplex optical links to transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector electronics. The board implements 2 duplex optical links for clocks, control, and monitoring with redundancy design to improve the system reliability. Major functions of the board have been verified.
Speaker: Tiankuan Liu (Southern Methodist University (US)) -
16:40
CMS HCAL VTRx-induced communication loss and mitigation 16m
The Compact Muon Solenoid (CMS) Phase 1 Hadron Calorimeter Upgrade (HCAL) saw the first large-scale use of VTRx modules, optical transceivers designed to be radiation and magnetic field tolerant. During Run II of the Large Hadron Collider, the CMS HCAL experienced a short period of communication loss that revealed a manufacturing weakness in the VTRx affecting nearly half of the communication links. The CMS HCAL Team provided the first observation of this phenomenon, revealed its temperature dependence, and pioneered the mitigation tactic adopted by other LHC experiments. We will present these aspects of the larger VTRx investigation.
Speaker: Grace Cummings (University of Virginia)
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Posters ASIC
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17:20
Monolithic pixel sensor with 25µm x 35µm pixel size and high time resolution implemented in 180nm technology 3m
A monolithic pixel sensor named HVMAPS25 has been implemented in a 180nm HVCMOS technology. The pixel size is 25µm x 35µm. The pixel electronics contains a fast and low power charge sensitive amplifier, comparator, threshold tune DAC and a digital circuit that measure the arrival time of the hit with 10 bit resolution, <10ns bin width, and the amplitude (ToT) with 6 bit resolution.
The sensor is implemented in a commercial process of TSI Semiconductors on 200Ωcm substrate. Deep p-well has been used for isolation of the pixel electronic from the sensor substrate. The design and measurement will be presented.Speaker: Hui Zhang (Karlsruhe Institute of Technology (KIT)) -
17:23
2 ps rms Jitter Analog PLL Running at 2.56 GHz in 130nm CMOS Technology 3m
The aim of this work is to develop an internal PLL for ASIC developments which integrates time measurement or which requires an internal clock in the range of GigaHertz. For future upgrades in High Energy Physic detectors experiments, time measurement becomes a decisive element, which will make it possible to reduce the data flow and improve the spatial accuracy of the interaction point. This design is based on a top down design methodology including a behavioural and a linearized PLL. Two PLLs were designed with two different VCOs based on ring and LC tank oscillator.
Speaker: Mr Herve Mathez (Centre National de la Recherche Scientifique (FR)) -
17:26
Radiation hardness of the ITkPixV1 and RD53A chips 3m
The ITkPixV1 chip is the pre-production pixel readout chip for the Phase-2 Upgrade of the ATLAS experiment at the HL-LHC. The harsh environment of HL-LHC, including a peak luminosity of 5x10^34cm-2s-1 and an estimated total ionising dose (TID) of more than 500 Mrad throughout its lifetime is placing strong requirements on the radiation tolerance of the chip. This contribution outlines investigations into the radiation tolerance of ITkPixV1. The impact of TID damage to the digital and analog front-end up to total doses of 1 Grad (at dose rate 4 Mrad/h) is reported.
Speaker: Maria Mironova (University of Oxford (GB)) -
17:32
Event driven readout system with non-priority arbitration for radiation detectors 3m
A new data driven readout architecture for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz’ arbiters thanks to which there is no imposed prioritization and protection against glitches during readout is provided. The system allows not only reading the pixel activity, but also retrieving additional data, both analog and digital, from them. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal so there is no dead time between readouts.
Speaker: Dominik Górni (Brookhaven National Laboratory) -
17:35
Certification of the amplifier-shaper-discriminator ASICs produced for the ATLAS MDT chambers at the HL-LHC 3m
The front-end electronics of the ATLAS muon drift-tube chambers will be upgraded in the experiment's phase-II upgrade to comply with the new trigger and read-out scheme at the HL-LHC. A new amplifier shaper discriminator chip was developed in 130 nm Global Foundries technology for this upgrade. A preproduction of 7500 chips was launched in 2019 and tested in 2020. The functionality of the chips, the test set-up and test procedure and results showing a yield of 92% are presented. The certification of the preproduction was followed by the production of 80,000 chips in fall 2020 showing 92% yield.
Speaker: Oliver Kortner (Max-Planck-Institut fur Physik (DE)) -
17:38
FastIC: A Fast Integrated Circuit for the Readout of High Performance Detectors 3m
This work presents the 8-channel FastIC ASIC developed in CMOS 65nm technology suitable for the readout of positive and negative polarity sensors in High Energy Physics experiments, Cherenkov detectors and Time-of-Flight systems. The front-end can be configured to perform analog summation of up to 4 single-ended channels before discrimination in view of exploiting area segmentation. The outputs encode the Time-Of-Arrival information and linear Energy measurement in the 5uA – 20mA input range, with a power consumption of 12mW/ch with preset settings. Measurements of Single Photon Time Resolution with a red-light laser source and a Hamamatsu SiPM S13360-3050CS are ~140ps FWHM.
Speaker: Sergio Gomez Fernandez (University of Barcelona (ES)) -
17:41
A Dual-mode NRZ/PAM4 Transmitter IP Purposed for Advanced CMOS Technology Nodes 3m
While the potential of PAM4 is becoming more practical, many designs still choose the NRZ approach. This paper presents a customisable dual-mode PAM4/NRZ transmitter IP (with 4/2-tap channel equalisation) deployable in multiple CMOS technologies. IP has been fabricated in 65nm (28Gbps/14Gbps), 180nm (10Gbps/5Gbps) technologies. A radiation-hardened 65nm (20Gbps/10Gbps) flavour is in active development. The serialization process is achieved using 16 self-generated synchronised clocks and produces 2 data streams with 4 equalisation streams to minimise inter-symbol inference. IP can be customised to transmit 1 PAM-4 (non-standard encoding) or 2 NRZ (Aurora 64b66b) data streams (with additional IO) prior to fabrication.
Speaker: Thomas Gardiner (STFC) -
17:44
Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC 3m
The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, a novel SEE verification strategy was proposed and implemented. In this paper we present the revamped UVM verification framework of lpGBTv1 and discuss the verification process, tools, techniques and metrics used to sign-off the design before submission.
Speaker: Mr Adithya Pulli (CERN) -
17:47
QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology 3m
The Quad Transimpedance and limiting Amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode to look for the optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, mitigating radiation effects on the photodiodes. QTIA circuit functions pass preliminary but successful tests.
Speaker: Ms Hanhan Sun (Southern Methodist University) -
17:50
Development of a 20 Gbps PAM4 Data Transmitter ASIC for Particle Physics Experiments 3m
Abstract: GBS20 is a transmitter ASIC for particle physics experiments. Two serializers each at 5.12 or 10.24 Gbps share a 5.12 GHz PLL clock. The serializers’ output is combined to a PAM4 signal that drives a VCSEL. The input data channels, each at 1.28 Gbps, is scrambled by a PRBS7 that is also the internal test pattern generator. Preliminary tests indicate that the prototype works at 10.24 and 20.48 Gbps PAM4 with a TOSA. More tests, including irradiation, will be carried out. The next step is to develop a pluggable transmitter module GBT20 base on this ASIC.
Speaker: Ms Li Zhang (Southern Methodist University and Central China Normal University) -
17:53
A radiation-tolerant clock generator for the CMS Endcap Timing Layer readout chip 3m
We present the test results of the ETROC PLL prototype chip. This chip is based on the latest version of ljCDR from the lpGBT project and is designed to test ljCDR in its PLL mode as the clock generator for the CMS Endcap Timing Layer readout chip (ETROC). An automatic frequency calibration (AFC) block with the data protector is implemented for LC-VCO calibration. Triple Modular Redundancy (TMR) is used for all digital circuits to protect against SEUs. The chip’s performance has been extensively tested, including SEU testing with heavy ions from 1.3 MeV.cm2/mg up to 62.5 MeV.cm2/mg.
Speaker: Datao Gong (Southern Methodist University (US)) -
17:56
Low Noise Charge Sensitive Amplifier - ASIC with Adaptive Gain Setting and Active Reset 3m
The ASIC design group at GSI developed an Amplifier With Adaptive Gain Setting (AWAGS) chip. The input stage based on a folded cascode architecture followed by a single-ended to differential conversion and output buffers. In difference to usual designs the capacitive feedback is divided in five capacitances with different values. Starting with the smallest one the capacitances were adaptively added to the feedback depending on the input charge. This concept allows to measure over a high dynamic range (upto 50pC) with the highest precision in the individual gain setting.
The AWAGS ASIC is produced in a MPW run 2020.Speaker: Peter Wieczorek (GSI Darmstadt, Germany) -
17:59
A low power clock generator 400-1800 MHz for ADPLL 3m
This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 MHz to 50 MHz and generates an output signal ranging from 400 MHz to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28nm CMOS technology of TSMC. The power consumption and chip area of the block are 1.5 mW and 80x80 $µm^2$ correspondingly. A wide range of reference and output frequencies makes this block versatile in application.
Speakers: Pavel Ivanov (NRNU MEPhI), Dmitry Normanov (NRNU MEPHI) -
18:02
A Four-Channels Front End Electronics for ATLAS Muon-Drift-Tubes Detectors in 65nm CMOS Technology 3m
Front-End-Electronics are utilized by ATLAS muon chamber (MDT) to detect charge and give information regarding charge arrival time and amount of charge being detected. Read-Out-Electronics along with being robust, should operate faster, be area and power efficient. This paper presents improved version of AFE, ASD designed in 130nm technology, that is actually used for MDT chambers of ATLAS Experiment. AFE is designed in 65nm CMOS Process, with single Mode of operation and minimal architecture by eliminating two stages without effecting performance. Along with scaling down technology this AFE consumes 16mW per channel, which is 46% efficient than the previous design.
Speaker: Adeel Syed Ali Shah (UNIMIB) -
18:05
DIAMASIC: A multichannel front-end electronics for high-accuracy time measurements for diamond detectors 3m
This paper describes the design and testing results of an 8 channels preamplifier-discriminator circuit based on a resistive feedback Transimpedance Amplifier architecture and a Leading-Edge Discriminator stage for fast high-accuracy time measurement systems. The circuit has been designed in a 130 nm CMOS technology. It is intended to be used as a Front-End-Electronics for measuring the Time Of Flight using diamond detectors. The size of the chip is 1.27x1.22mm² and the total power consumption of one channel is 1.5mW with a power supply of 1.2V. Testing results shows a timing jitter of about 80ps for a 10fC input charge pulse.
Speakers: Mr Abderrahmane GHIMOUZ (Univ. Grenoble Alpes, Grenoble INP, CNRS, LPSC-IN2P3), Mr Fatah Ellah Rarbi (Univ. Grenoble Alpes, CNRS, LPSC-IN2P3, Grenoble INP), Fatah Ellah Rarbi (Centre National de la Recherche Scientifique (FR)) -
18:08
2.56 Gbps CML transceiver for the data concentrator ASIC 3m
2.56 Gbps CMOS CML-transceiver is presented. The key feature of the design is capability of working with a specific inductive load at both power consumption and radiation tolerance constraints. The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron (Dubna).
Speaker: Arthur Serazetdinov (National Research Nuclear University MEPhI) -
18:11
Onchip digital calibrated 2mW 12b SAR ADC with reduced input capacitance 3m
We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 4fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to digitally compensate for the mismatch non-linearity directly over the ADC output. The circuit consumes 2mW on a core area of 300um x 500um in 180nm CMOS technology. ENOB of 11.5-bits was post-layout simulated after calibration. Sample characterization is ongoing.
Speaker: Hugo Hernandez Herrera (Federal University of Minas Gerais) -
18:14
The Front End and Trigger Unit for an Analogue Transient Recorder ASIC 3m
A front end and trigger circuit was developed at GSI which is foreseen to be used in a transient recording read out ASIC. It consists of an input buffer with configurable low pass characteristics and a trigger which could be operated as leading edge discriminator as well as switched capacitor trigger which is sensitive to the first derivative of the input signal. The front end was produced on a test ASIC and characterisation results will be presented.
Speaker: Holger Flemming (GSI Helmholtzzentrum für Schwerionenforschung GmbH) -
18:17
A Family of Transient Recorder ASICs for Detector Readout 3m
A set of highly integrated read out ASICs with a common digitising and data aquisition back end but different front ends is currently under development at the GSI electronics department. The concept consists in using an analogue transient recorder stage for an efficient application of the area and power consuming analogue to digital converter. A focus of these ASICs is the read out of detectors with a large dynamic range. Possible applications could be the electromagnetic calorimeter of the PANDA detector or the GEM TPC of the Super-FRS at FAIR.
Speaker: Holger Flemming (GSI Helmholtzzentrum für Schwerionenforschung GmbH) -
18:20
Experimental characterisation of the RD50-MPW2 High Voltage-CMOS sensor chip 3m
The CERN-RD50 collaboration aims to develop and study High Voltage-CMOS (HV-CMOS) sensors for use in very high luminosity colliders. Measurements will be presented for the RD50-MPW2 chip, a prototype HV-CMOS pixel detector with an active matrix of 8 x 8 pixels. The active matrix is tested with injection pulses, a radioactive source and a proton beam. This talk will cover the FPGA based DAQ system, the software and firmware developed to take and analyse data. Proton test-beam telescope measurements will be presented as well as the detector gain and noise characterisation using charge injection and radioactive source measurements.
Speaker: Samuel Powell (University of Liverpool (GB)) -
18:23
CIC2: a radiation tolerant 65nm data aggregation ASIC for the future CMS tracking detector at LHC 3m
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. A first prototype, CIC1, was tested successfully in early 2019 and was followed by the development of a final radiation tolerant version of the chip: the CIC2. CIC2 design, implementation, and complete test results, are presented.
Speaker: Sebastien Viret (Centre National de la Recherche Scientifique (FR)) -
18:26
Towards a Software-Adaptable Receiver Chain for Particle Detectors 3m
Chip design, is a lengthy process, which comes with high development efforts and costs and is a crucial milestone for the overall success of the project. Readout electronics for particle detectors resemble each other to a high degree, thus developing a software-adaptable receiver chain covering a large range of application scenarios is an attractive concept. With a generic approach, designed independently, these risks are shifted to project-independent stages, which substantially reduces development time and costs, enabling also smaller projects and rapid prototyping.
A generic receiver low power system-on-chip is conceptualized. The central block is a software-scalable, high-performance ADC combined with a configurable front-end with adjustable impedance. Succeeded by an SRAM memory as a buffer and a digital signal pre-processing system. The high integration degree and complexity of the system is accompanied by an advanced 28nm CMOS technology, mitigating the area overhead of a generic approach and enabling high-speed electronics at an acceptable power consumption. Common approaches in detector readout use blocks like TDCs for the extraction of information from detector signals. While simpler and inherently efficient, they reduce the options for direct reusability in various application areas and require a repeated design effort. In this novel approach, the sampled waveforms enable sophisticated signal processing, leveraging the potential of a complex system-on-chip in a modern technology. This will enable an increased resolution for time and energy measurements, as demonstrated by (Jokhovets, 2019). Such methods enable a timing resolution below 100ps from sampling at nanosecond intervals. Furthermore, it will allow a pre-clustering and data reduction on chip, reducing the transmission bandwidth and amount of necessary post-processing hardware. An integrated 16kByte SRAM buffer will allow for local data buffering and reduction of transmission speed, adjustable to the expected hit rates.
For these developments, an in depth study of existing readout solutions was performed, whose results are summarized in this contribution. Additionally, it will give an introduction in the algorithm development process and the developed Simulink framework.
Another focus of this contribution is the software-scalable ADC that consists of similar ADC cores. They can be arranged in different ways to adjust to different specifications. For the core ADC, successive approximation register (SAR) ADCs are implemented as their mostly digital nature scales well with technology, leading to higher performance and decreased chip area. The ADCs can be concatenated which increases the resolution without penalties in sample rate. For the first engineering sample, a high-precision mode with 12 bit resolution and a medium-precision mode with 9 bit is foreseen. The maximum sample rate is 500 MS/s with no bound for the lowest sample rate. For higher rates, the ADCs can also be multiplexed in time (time-interleaving). Using two time-interleaved ADCs for the first prototype, a maximum sample rate of 1 GS/s can be achieved. It is also investigated to use both time-interleaved ADCs independently to read out two channels, gaining flexibility for multichannel designs. The silicon area for the ADC pair is conservatively estimated to 0.24 mm2 , allowing an upscaling of the number of channels in future developments.Speakers: Lukas Krystofiak (Juelich Research Centre), Florian Rössing (Forschungszentrum Jülich GmbH (FZJ))
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18:40
Posters Optoelectronics and Links
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17:20
Hermes - A robust, low latency, optical link protocol for synchronous data transfer at commercial asynchronous line rates 3m
The Phase-2 CMS Level-1 Trigger and associated upstream systems consist of more than 20,000 25Gb/s optical links, transferring almost a Pb/s synchronously between different back-end processing nodes. The stable operation of these links is essential to avoid the injection of an erroneous signals into the trigger path, potentially leading to a flood of false triggers.
The Hermes protocol, implemented on Xilinx UltraScale+ FPGAs, provides this stability while operating at asynchronous, industry standard, line rates. The protocol design as well as the performance from extensive tests are presented here
Speaker: Kosmas Adamidis (University of Ioannina (GR)) -
17:23
Development of a high bandwidth readout chain for the CMS Phase-2 pixel upgrade 3m
The CMS collaboration is building a new inner tracking pixel detector for the High-Luminosity LHC. Each pixel chip will be controlled with a single serial input stream at 160 Mbps and will send out data via four CML 1.28 Gbps outputs. The modules will be connected with up to 1.6 m long low-mass electrical links to the low power gigabit transceivers (lpGBT) and versatile transceivers (VTRx+) that send the data optically to off-detector electronics at 10 Gbps. The development and the characterization of these components will be presented along with system tests of the readout chain.
Speaker: Dr Caleb James Smith (The University of Kansas (US)) -
17:26
The Versatile Link+ Demo Board (VLDB+) 3m
The Versatile Link Plus Demonstrator Board (VLDB+) is a board designed by CERN’s EP-ESE group to provide an evaluation kit for the new Versatile Link ecosystem (VL+). This reference design gathers three custom and radiation hard devices, namely, the Low-Power Gigabit Transceiver (lpGBT), the Versatile Link Plus Transceiver (VTRx+) and the FEASTMP DCDCs. These components are common to some of the HL-HLC experiments and constitute the main elements of the board. The VLDB+ is already being extensively used by several experiments to get acquainted with the whole ecosystem in order to facilitate their final Front-end system design.
Speaker: Daniel Hernandez Montesinos (GBTx - BE Group) -
17:29
Developments on Radiation-Hard Silicon Photonic Devices towards Integrated Transmitters for High Energy Physics 3m
Custom silicon photonics intensity modulators for data readout in particle detectors will be presented together with preliminary experimental results. A variety of devices has been designed to explore the technological requirements to achieve data rate up to 25 Gb/s while sustaining extremely high dose levels (1 Grad total ionizing dose). Packaging constraints have been carefully considered to allow hybrid integration between photonic components, radio-frequency boards and integrated electronics.
Speaker: Simone Cammarata (Università di Pisa & INFN Pisa (IT)) -
17:32
Radiation hard TwinAx for ATLAS ITk pixel electrical data transmission 3m
Abstract
The high radiation dose and the cold environment at the HL-LHC pixel detector regions presents serious challenges for the survival of optical components. Radiation hard twinax cables are developed for the ATLAS ITk pixel data transmission within the pixel detector volume for up to 6m before transitioning to optical links at larger radius where radiation dose is reduced to acceptable level for optical components. We will present the design, qualification and industrialization process of the ATLAS ITk pixel electrical links using such twinax cables.
Speaker: Mr Andrew Young (SLAC National Accelerator Laboratory (US))
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17:20
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18:40
Posters Power, Grounding and Shielding
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17:23
Smart Switch based High Voltage Distribution System for Mu2e Electron Tracker 3m
The design and development of a High Voltage distribution system (HVDS), Smart Switch (SS) which acts as a Demultiplexer, to distribute one high voltage(HV) input into six High Voltage output channels. It provides, and independently voltage and current monitors. Each output channel of the SS has independent, ON-OFF, current and HV monitoring, as well as filtration, isolation, and a crowbar for over-current protection. The inter-communication system is based on TCP/IP protocol through a Raspberry Pi. The performance of the HVDS was found to be comparable to commercial High Voltage Power supplies.
Speaker: Dr Waqar Ahmed (University of Houston) -
17:26
Upgrade of the ATLAS Tilecal High Voltage system 3m
The high voltage (HV) system of TileCal, the ATLAS central hadron calorimeter, is being upgraded for the HL-LHC, in the so called Phase II Upgrade. In the new configuration for the upgrade, the HV regulation boards are not located inside the detector anymore, they are deployed far from the radiation in a room where there is permanent access for maintenance. This option requires a large number of 100 m long HV cables but removes the requirement of radiation hard boards. HVremote regulation boards and the respective HV supplies boards have been developed and tested, as well as a crate to
Speaker: Agostinho Da Silva Gomes (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part) -
17:29
High precision scalable power converter for accelerator magnets 3m
The lower conduction power losses and the positive temperature coefficient that favours parallel connections, make Silicon Carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) to be an excellent replacement of existing Silicon insulated gate bipolar transistors (IGBTs) technology. These characteristics combined with high switching frequency operation, enables the design of high-accuracy DC-DC converters with minimised filtering requirements. This paper compares two designs for a converter with high-accuracy current (0.9ppm) supplying a 0.05H electromagnetic load; one design with the topology and filter for a typical IGBT-based full-bridge and a second one with a SiC MOSFET based topology without filter.
Speaker: Krister Leonart Haugen (Norwegian University of Science and Technology (NTNU) (NO))
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17:23
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Posters Production, Testing and Reliability
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17:20
Development of the probe station for the hybrid assemblies of the European XFEL camera AGIPD 3m
The European XFEL facility delivers bunches of high brilliance pulses with a unique time structure, which requires a specially designed photon detectors for taking and recording the high quality scientific data. The Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector developed to cope with crucial requirements like 4.5 MHz frame rate and a dynamic range of 104 12.5 keV-photons. An important part for the data quality is the hybrid front-end module and its yield. In order to improve it a special probe station was designed and commissioned, the challenges and results are to be reported.
Speaker: Dr Alexander Klujev (Deutsches Elektronen-Synchrotron) -
17:23
Blade-board for stability studies of the slow-control functionality of the CMS muon DT uTCA backend 3m
In recent years, some minor issues were observed during operation of CMS Muon specific TM7 blade-boards, which are data concentrators for the hit-data from Drift-Tube chambers. These blade-boards reside in the uTCA crates in the service cavern of CMS. Talk presents a recently developed test-board, which is used as an inexpensive substitution of TM7. The developed test-board implements a Module Management Controller (MMC) and some further functional aspects of TM7. It facilitates extensive tests for observing operational stability with many TM7-alike blades within one uTCA crate. Along with presenting the test-board and its firmware, talk also covers ongoing stability studies.
Speaker: Dmitry Eliseev (Rheinisch Westfaelische Tech. Hoch. (DE)) -
17:26
A system test platform for the CERN power converter control electronics 3m
The power converters at CERN deliver a broad range of complex functionalities to assure the correct magnetic field throughout the beam acceleration cycle. The power converter controls are composed of remotely programmable electronics, however such flexibility is also vulnerable to regression that requires thorough testing. Further, testing requires a significant investment in infrastructure to allow systems capable of supplying up to 10MW, 100kV and 100kA to be validated. This paper describes a system test platform using continuous integration techniques and hardware-in-the-loop modelling to validate the controls before deployment.
Speakers: Ms Gabriela Cabrera Castellano (CERN), Mr Robert Grimmer (CERN), Mr Peter Haynes (CERN) -
17:29
Test system for the Service Hybrid of the 2S Module for the CMS Phase-2 Outer Tracker Upgrade 3m
In the context of the second phase of the CMS Outer Tracker upgrade two complementary systems for the testing of the service hybrids for two-sided silicon strip modules are presented. To enable prototype testing and long term active thermal cycling during series production a dedicated test board for stand-alone operation has been produced. In addition, a test card compatible with a production scale system has been developed. It is embedded in a common test system for all CMS-OT hybrids. The test systems will be introduced and first test results with both systems on prototype 2S service hybrids will be presented.
Speaker: Alexander Josef Pauls (RWTH Aachen University (DE)) -
17:32
PANDORE: an environmental box for ITk integration tests. 3m
PANDORE is the environmental box that is going to be used for the quality control (QC) of loaded local supports of the ATLAS ITk Pixel Outer Barrel (OB) at LAPP. First PANDORE, its interlock system, diphasic CO2 cooling station, and data acquisition system are described. Subsequently, the results of the qualification tests are shown. Given the complexity of the OB system, several other loading sites are going to be needed. By documenting the state-of-the-art of PANDORE, this note aims to help the wide OB community in the discussion for standardizing the QC procedure and equipments of the loaded local supports.
Speaker: Francesco Costanza (Centre National de la Recherche Scientifique (FR)) -
17:35
Performance and Plans for Production of the Powerboard for ATLAS ITk Strip Barrel Modules 3m
The Inner Tracker silicon strip detector (ITk Strips) is a part of the ATLAS upgrade for the HL-LHC. It employs a parallel powering scheme for the high voltage sensor bias and the low voltage to power readout ASIC’s. This design requires on-module DCDC conversion and high voltage switching. These are implemented on the Powerboard using a buck converter (bPOL12V) to drop the low voltage, a GaNFET for the HV switch, and a custom ASIC (AMAC) for control and monitoring. This contribution will present the Powerboard performance and the test system that will be used for the production of 15,0000 Powerboards.
Speaker: Karol Krizka (Lawrence Berkeley National Lab. (US)) -
17:38
SMX and front-end board tester for CBM readout chain 3m
The SMX chip is a front-end ASIC dedicated for the readout of STS and MUCH detectors in the CBM experiment.
The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure the quality.
The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard.
In the standalone configuration the tester is controlled via IPbus and enables full functional testing of connected SMX, FEB, or a full detector module.
The software written in Python may easily be integrated with higher-level testing software.Speaker: Dr Wojciech Zabolotny (Institute of Electronic Systems, Warsaw University of Technology)
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17:20
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Posters Programmable Logic, Design Tools and Methods
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17:20
Isolated USB Programmer for LpGBT (UPL) for the ATLAS-HGTD upgrade 3m
The CERN developed radiation-tolerant data transmission chip lpGBT will be used on the peripheral electronics board (PEB) of High Granularity Timing Detector (HGTD) in ATLAS. In order to configure the lpGBT on the PEB, we designed a dedicated isolated USB programmer. Compared with the 2 existing lpGBT configuration toolkits, piGBT and CERN USB-I2C dongle, the programmer has very good cross-platform compatibility, electrical isolation performance and compact dimensions, which make it a better choice for PEB configuration.
Speaker: Mr Liangliang Han (Nanjing University (CN)) -
17:23
Proton Sound Detector for Beam Range Measurement in FLASH Hadron Therapy 3m
Proton-Sound-Detectors (ProSDs) sense (at <1 ms latency) the thermoacoustic signal generated by the fast energy deposition at the Bragg peak of proton beams penetrating energy absorbers.
ProSDs are especially promising for experimental monitoring of high pulse rate (FLASH) hadron therapy treatments working in-sync with the beam.
This paper presents a mixed-signal detector capable of sensing and processing high rate (1k beam shots/sec) ionacoustic signals with <1 ms latency. The system was validated by measuring the dose deposition of a 20 MeV proton beam in water, achieving 3.43% precision (±2.75 GyRMS) after 50 ms acquisition (77.56 Gy total dose deposition).Speaker: Elia Arturo Vallicelli (University of Milano Bicocca) -
17:26
Easy and structured approach for software and firmware co-simulation for bus centric designs 3m
Although software and firmware co-simulation is gaining popularity, it is still not widely used in the FPGA designs.
This work presents easy and structured approach for software and firmware co-simulation for bus centric designs.
The proposed approach is very modular and software language agnostic.
The only requirement is that the firmware design is accessible via some kind of bus.
The concept has been used for testing DAQ system being developed for high energy physics experiment.Speaker: Michal Kruszewski (Warsaw University of Technology) -
17:29
Versatile free-running ADC-based data acquisition system for particle detectors 3m
A high density data acquisition system integrating over 2000 channels inside of a single OpenVPX crate is intended to be used in different applications e.g. gaseous or scintillator-based particle detectors. 14 payload slots, controller and data concentrator communicate one with other via multi-gigabit backplane. Each payload slot consists of a front module for digital and a rear transition module for analog processing. This single pair implements 160 full chains including amplification/shaping, sampling, and feature extraction. Sampling rate and ADC resolution are configurable for 80-1000 MS/s, 8-14 bit. The system has been tested at COSY at Jülich Research Center (Germany).
Speaker: Lioubov Jokhovets (Forschungszentrum Jülich GmbH) -
17:32
Machine Learning for Real-Time Processing of ATLAS Liquid Argon Calorimeter Signals with FPGAs 3m
Within the Phase-II upgrade of the LHC, the readout electronics of the ATLAS LAr Calorimeters is prepared for high luminosity operation expecting a pile-up of up to 200 simultaneous pp interactions. Real-time processing of digitized pulses sampled at 40 MHz is thus performed using FPGAs.
To cope with the signal pile-up, new machine learning approaches are explored that outperform the optimal signal filter currently used, both in assignment of the reconstructed energy to the correct bunch crossing and in energy resolution.
Latest performance results and experience with prototype implementations will be reported.Speaker: Nemer Chiedde (Centre National de la Recherche Scientifique (FR)) -
17:35
Firmware Architecture of the back-end DAQ system for the CMS High Granularity Endcap Calorimeter detector. 3m
During the High-Luminosity phase of the LHC, the CMS endcap calorimeter will be replaced by the High-Granularity Calorimeter (HGCAL). A first firmware for the back-end DAQ system of the CMS Phase-2 upgrade HGCAL was implemented in the Serenity ATCA hardware. The system is responsible not only for the readout of the detector but also for its slow control and timing. To facilitate system maintenance, the firmware is optimized to handle all the different Front-End electronics configurations and data rates using a single — highly configurable — design. The architecture and implementation of the back-end DAQ system will be presented here.
Speaker: Stavros Mallios (CERN) -
17:38
QEMU-based hardware/software co-development for DAQ systems 3m
Modern DAQ systems typically use the FPGA-based PCIe cards to concentrate and deliver the data to a computer used as an entry node of the data processing network.
This paper presents a QEMU-based methodology for the co-development of the FPGA-based hardware part, the Linux kernel driver, and the data receiving application. That approach enables quick verification of the FPGA firmware architecture, organization of control registers, the functionality of the driver, and the user-space application.
The developed design may be tested in different emulated architectures with a changeable type of CPU, IOMMU, size of memory, and the number of DAQ cards.Speaker: Dr Wojciech Zabolotny (Institute of Electronic Systems, Warsaw University of Technology) -
17:41
Verification of ATLAS detector readout with FPGA-based front-end emulator 3m
The FrontEnd LInk eXchange (FELIX) is an FPGA-based data router designed to interface custom detector readout systems, and commodity switched networks as part of the ongoing upgrade of the ATLAS experiment at CERN. FELIX relies on synchronous data aggregation with GBT and lpGBT protocols to control and readout multiple detector front-ends. To facilitate validation and benchmarking, we designed and used an FPGA-based emulator of the front-end systems, FELIG. FELIG uses the same hardware as FELIX, FLX-712 board and inherits selected firmware blocks from FELIX. However, FELIG features clock and data recovery and a configurable data generator specifically designed for it.
Speaker: Ricardo Luz (Argonne National Laboratory (US))
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17:20
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Posters Radiation Tolerant Components and Systems
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17:20
Test of Low-Dropout voltage regulators with neutron and protons 3m
The ATLAS Muon System will be upgraded for the High-Luminosity phase of LHC. Its new on-detector electronics should withstand a non-ionizing dose equivalent to 10^13 n/cm2 (1 MeV eq on Si) and have a negligible rate of single-event effects. Commercial low-dropout (LDO) voltage regulators have been considered as a practical solution for powering on-detector electronics. We present results from the irradiation of 7 types of CMOS LDOs at the fast neutron reactor RSV TAPIRO at ENEA Casaccia (Roma) and at the 200 MeV proton beam at PSI (Zurich).
Speaker: Iacopo Longarini (Sapienza Universita e INFN, Roma I (IT)) -
17:23
Fully-integrated set-up for gate current characterization in 28nm CMOS technology 3m
This work introduces design and simulation validation, of a monolithic setup, based on a current amplifier, for accurate gate current measurement in NMOS devices integrated in 28nm technology. The Devices-Under-Test (DUTs) include transistors with gate width between 60μm and 300μm and length between 400nm and 1μm. Current in the DUT is amplified by a 100x factor, with an accuracy above 90%. The current amplifier achieves low noise operation for an accurate gate-current parallel noise estimation. The device will also be exploited to study radiation (up to 500Mrad-TID) damage effects on the noise current and on its associated parallel noise.
Speaker: Federico Fary (University of Milano-Bicocca) -
17:26
Irradiation of VFAT3: A 128-channel charge-sensitive front-end chip for the CMS GEM phase-2 upgrade 3m
VFAT3 is the 128-channel charge-sensitive front-end chip explicitly designed for the CMS GEM phase-2 upgrades. LHC is undergoing major upgrades for HL-LHC where the particle rate is expected to increase up to 5 times. It is therefore necessary to monitor the evolution of the VFAT3 response due to aging in the radiation environment by total ionizing dose (TID) tests. The device operation could also be interrupted by a single high-energy particle. Thus, the estimation of the single event upset (SEU) cross-section is essential as well. We summarize irradiation test results that validate the suitability of VFAT3 for CMS GEM upgrades.
Speaker: Mr Aamir Irshad (Universite Libre de Bruxelles (BE)) -
17:29
Investigation of Radiation-Induced Effects in a Front-end ASIC designed for Photon Counting Sensor Systems 3m
This work outlines the measurements done to evaluate the second SPACIROC generation in ionizing radiation environments, i.e., particle beams: ions, protons, and X-rays. The SPACIROCs are front-end ASICs designed for the readout requirements of photomultiplier technologies like: SiPMs, MaPMTs. Several radiation-induced effects were observed but they proved to be benign application-wise. The threshold LET for SEUs was measured and two cross-sections for different LETs are provided. At extremely high dose rates (~100 rad/s) and TID above 50 krad proton/X-ray induced TID effects were observed, however a room-temperature annealing process was determined to mitigate the harmful TID effects in 24 hours.
Speaker: Vlad-Mihai Placinta (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO)) -
17:32
Readiness of the radiation tolerant link Daughterboard for the High Luminosity upgrade of the ATLAS Hadronic Calorimeter 3m
The upgrade of the ATLAS TileCal for the HL-LHC uses a Daughterboard that serves as a hub interfacing the on-detector with the off-detector electronics. The Daughterboard design features ProASIC FPGAs, Kintex Ultrascale FPGAs and CERN GBTx ASICs. The design minimizes single points of failure and radiation damage by employing a double-redundant scheme, using TMR and Xilinx SEM strategies, adopting CRC verification in the uplinks and FEC in the downlinks, and using a dedicated SEL protection circuitry. We present a summary of the studies on the Daughterboard revision 6 performance and the radiation qualification tests of the design components.
Speaker: Eduardo Valdes Santurio (Stockholm University (SE)) -
17:35
Successive Approximation Register ADC Single Event Effects Protection and Evaluation 3m
This work analyses seven different alternatives to implement an ADC based on the successive approximation register (SAR) architecture. The influence of the encoding is taken into account while evaluating the importance of its reset approach. Different protection strategies against single event upsets are addressed, including the comparison of per module and per cell triplication. All versions of the SAR were designed and prototyped in the TSMC 130 nm technology. The ASIC was packaged in an open window QFN64 and irradiated in the IFUSP Pelletron particle accelerator, which revealed the impact of the encoding and reset choices in the block cross-section.
Speaker: Bruno Sanches (EPUSP)
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17:20
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Posters Systems, Planning, Installation, Commissioning and Running Experience
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17:20
The charge sensitivity calibration of the upgraded ALICE Inner Tracking System 2m
The ALICE detector is undergoing an upgrade for Run 3 at the LHC. A new Inner Tracking System is part of this upgrade. The upgraded ALICE ITS features the ALPIDE, a Monolithic Active Pixel Sensor. Due to IC fabrication variations and radiation damages, the threshold values for the ALPIDE chips in ITS need to be measured and adjusted periodically to ensure the quality of data-taking. The calibration is implemented within the $O^2$ system, thus it runs in the same framework as the normal operation. This paper describes the concept and implementation of the calibration for the upgrade ALICE ITS.
Speaker: Shiming Yuan (University of Bergen (NO)) -
17:24
Design of a IoT based multi-channel temperature monitoring system 2m
In the scope of the Jiangmen Underground Neutrino Observatory (JUNO) project, 6 back-end card (BEC) mezzanines connected to one BEC base board are in charge of compensating the attenuated incoming data from 48 front-end channels over 48 100-meters-long ethernet cables. Each of the mezzanines has 16 equalizers that may be subject to overheating. It is important to monitor their temperature in real time. However, collecting data from a relatively large (1080) number of mezzanines is not a trivial task. In this work we propose a solution based on Wi-Fi mesh. Both technical details and test results will be reported.
Speaker: Daniel Gomez de Gracia (ULB) -
17:26
Precision luminosity measurement at CMS with the Pixel Luminosity Telescope 2m
The Pixel Luminosity Telescope (PLT) is a silicon pixel detector dedicated to luminosity measurement at the CMS experiment. It is arranged into 16 "telescopes" of three planes each, with eight telescopes arranged around the beam pipe at either end of the CMS detector, outside the pixel endcap. In the talk, the commissioning, calibration, operational history, and performance of the detector during Run 2 (2015-2018) of the LHC is presented. Studies of detector performance and the monitoring and mitigation of radiation damage effects will be highlighted.
Speaker: Andres Guillermo Delannoy Sotomayor (University of Tennessee (US)) -
17:28
The Fast Beam Condition Monitor as a standalone luminometer of the CMS experiment at the HL-LHC 2m
In the Phase-2 CMS upgrade, a luminosity uncertainty of 1% is targeted. To achieve this goal, measurements from multiple luminometers with orthogonal systematics are required. A standalone luminometer, the Fast Beam Condition Monitor (FBCM) is being designed for online bunch-by-bunch luminosity measurement. Its fast timing properties also enable the measurement of beam induced background. In this talk, the hardware architecture and the read-out protocol of the FBCM is described. The expected performance with a simple behavioral model of the front-end comprising a constant fraction discriminator is discussed, though the final implementation in the ASIC is still under discussion.
Speaker: Mohammad Sedghi (Isfahan University of Technology (IR)) -
17:30
A precision Time of Flight measurement system for the TORCH prototype detector 2m
The TORCH detector provides low-momentum particle identification, combining Time of Flight (TOF) and Cherenkov techniques to achieve charged particle pi/K/p separation between 2-20 GeV/c over a flight distance of 10m. The measurement requires a timing resolution of 70ps for single Cherenkov photons. For precision photon detection, customised Micro-Channel Plate Photomultiplier Tubes (MCP-PMTs) with high precision TOF measurement electronics have been developed. The electronics measures time-over-threshold from the MCP-PMT and features a 10-Gigabit Ethernet readout. A 50ps MCP/electronics time resolution has been demonstrated. This paper reports the design and performance of the system with 5120 channels, instrumenting ten customised MCP-PMT devices.
Speaker: Rui Gao (University of Oxford (GB)) -
17:32
SRS-based Timepix3 readout system 2m
Based on Timepix3 several detector types can be built by combining it with a sensor or a photolithographically postprocessed gas amplification stage. With these combinations applications like beam telescopes and gas-based X-ray detectors can be realized.
The detectors can range from single- to multichip and from low- to high-rate applications, thus a modular and scalable system is needed. It is based on the basil framework and supports several FPGAs. Furthermore, it offers optional monitoring interfaces for detector parameters.
I will present the readout system, its scalability and how it offers the needed functionality for different detector types.Speaker: Mr Markus Gruber (University of Bonn (DE)) -
17:34
TEPX as a high-precision luminosity detector for CMS at the HL-LHC 2m
The CMS BRIL project upgrades its instrumentation for the Phase-2 detector to provide high-precision luminosity and beam-induced background measurements. A part of the CMS Inner Tracker - the Tracker Endcap Pixel Detector (TEPX) - will allocate a fraction of the read-out bandwidth for luminometry. In the talk, the advantages and implications of the proposed approach are highlighted. A dedicated luminosity trigger distribution system is introduced together with its demonstrator system. A demonstrator of the real-time on-FPGA pixel cluster counting algorithm is also presented.
Speaker: Mykyta Haranko (CERN) -
17:36
The TileCal TDAQ interface module for the Phase II Upgrade of the ATLAS Tile Calorimeter 2m
In order to meet the requirements for the High Luminosity-Large Hadron Collider (HL-LHC), a completely new architecture will be used to redesign the readout electronics of the ATLAS Tile Calorimeter (TileCal) system for the ATLAS Phase-II Upgrade. In the new Trigger and Data AcQuisition (TDAQ) architecture, the output signals of the Tile detector cells will be digitized in the front-end electronics and transferred for every bunch crossing to the off-detector Tile PreProcessor (TilePPr) modules through high-speed optical links. The TilePPr will then reconstruct energy deposited in each cell from the digitized samples and transfer the pre-processed cell energy data further
Speaker: Tigran Mkrtchyan (Ruprecht Karls Universitaet Heidelberg (DE)) -
17:38
Description and status of the EMCI-EMP interface 2m
A novel DCS front-end interface for slow control, composed of two devices, the Embedded Monitoring and Control Interface (EMCI) and the Embedded Monitoring Processor (EMP), is presented. The EMCI, based on the lpGBT and the VTRx+, is placed in a radiation hard environment and is connected to multiple front-ends via eLinks. Up to 12 different EMCIs can transmit data via optical fibre to a single EMP, placed in the back-end in a radiation soft area. The EMP, based on commercial MPSoC module, is configured for data processing and monitoring and is accessible from the network via Ethernet.
Speaker: Mr Daniel Blasco Serrano (CERN)Additional materials -
17:40
A flexible and low-cost open-source IPMC mezzanine for ATCA boards based on OpenIPMC 2m
We present the development of an Intelligent Platform Management Controller mezzanine in a Mini DIMM form factor for use in electronic boards compliant to the Advanced Telecommunication Computing Architecture standard. The module is based on an STMicroelectronics STM32H745 microcontroller running the OpenIPMC open-source software, and its design has been published under open-source hardware license. The mezzanine has been successfully tested on a variety of ATCA boards being proposed for the upgrade of the experiments at the HL-LHC.
Speaker: Luigi Calligaris (UNESP - Universidade Estadual Paulista (BR)) -
17:42
ATLAS LAr Calorimeter Commissioning for LHC Run-3 2m
Liquid argon (LAr) sampling calorimeters are employed by ATLAS for all electromagnetic calorimetry in the pseudo-rapidity region |η| < 3.2, and for hadronic and forward calorimetry in the region from |η| = 1.5 to |η| = 4.9. Phase-I detector upgrades began after the end of ATLAS Run-2. New trigger readout electronics of the LAr Calorimeter have been developed. Installation began at the start of the LHC shut down in 2019 and is expected to be completed in 2021.This contribution will give an overview of the new trigger readout commissioning, as well as the preparations for Run-3 detector
Speaker: Florent Bernon (Aix Marseille Universite (FR)) -
17:44
A complete readout system for the CGEM detector 2m
An innovative Cylindrical Gas Electron Multiplier (CGEM) detector is under construction for the upgrade of the inner tracker of the BESIII experiment. A novel system has been worked out for the readout, including a new ASIC, dubbed TIGER, designed for the amplification and digitization of the CGEM output signals. The data output by TIGER are collected and processed by a first FPGA-based module, GEM Read Out Card, in charge of ASIC configuration and control. A second FPGA-based module, GEM Data Concentrator, builds the trigger selected event packets containing the data and stores them via the main BESIII data acquisition system.
Speaker: Michela Greco (INFN- Torino; University of Torino) -
17:46
Design and testing of a long Flexible Printed Circuit for the ATLAS High Granularity Timing Detector 2m
The High Granularity Timing Detector for the ATLAS upgrade is under construction to meet the challenges of the HL-LHC. The silicon detectors along with the electronics are installed in two double-sided disks per end-cap and consist of basic units (called modules) connected to the peripheral electronics by Flexible Printed Circuit cables. The reduced space between disks and the positioning constraints as well as the large number of modules pose additional challenges for the power supply distribution and the readout system. We present the design and test results for a 2-layer flexible PCB with a maximum distance of 75cm between connections.
Speaker: Maria Robles Manzano (Johannes Gutenberg Universitaet Mainz (DE)) -
17:48
Electronics Integration for the GE2/1 and ME0 GEM Detector Systems for the CMS Phase-2 Muon System Upgrade 2m
With the projected five-fold increase in instantaneous luminosity resulting from the High Luminosity upgrade of the Large Hadron Collider, the CMS experiment is in the process of upgrading its muon spectrometer. Two triple-GEM detector systems—the GE2/1, which is currently in the early mass-production phase, and the ME0, currently in the prototyping phase—are undergoing frontend electronics integration. This presentation discusses the current status of the electronics integration effort on full-size chamber prototypes by the CMS GEM collaboration, including results of grounding studies to reduce noise in the system, and the future prospects of the frontend electronics readout system.
Speaker: Stephen Butalla (Florida Institute of Technology (US)) -
17:50
ZynqMP-based board-management mezzanines for Serenity ATCA-blades 2m
In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family ATCA blades.
In this talk, we present the current revision of both Serenity baseboards and the developments on the MPSoC mezzanines to execute the Intelligent Platform Management Controller (IPMC) software in the real-time capable processors of the MPSoC. In coordination with the Shelf Manager, once full-power is enabled, a CentOS-based Linux distribution is executed in the application processors of the MPSoC.
Speakers: Torben Mehner (KIT - Karlsruhe Institute of Technology (DE)), Luis Ardila (KIT-IPE) -
17:52
A Generic Streaming Data Acquisition System for High-energy Physics Experiments 2m
The data acquisition system is a vital component in the high-energy physics experiment. To reduce duplication of work during development, D-Matrix, a generic platform, has been developed as a unified software/hardware streaming DAQ system and will be used in CSR External-target Experiments in HIRFL-CSR. Its philosophy is to abstract different tasks in the stream processing and encapsulate them as reusable modules with standard inter-module connectors. Furthermore, D-Matrix builds a unified model to integrate software and hardware design so that the system can be built from a global view. This paper presents the architecture of the D-Matrix DAQ.
Speaker: Tianxing Wang (University of Science and Technology of China) -
17:54
The Microstrip Silicon Detector (MSD) data acquisition system for the FOOT experiment 2m
The FOOT (FragmentatiOn Of Target) multi-detector experiment aims at improving the accuracy of oncological hadrontherapy for tumor treatment. It studies the nuclear fragmentation due to the interactions of charged particle beams with patient tissues. Among the several FOOT detectors, the silicon Microstrip Detector is part of the charged-ions-tracking magnetic spectrometer. Here we describe the MSD architecture and its data acquisition system whose task is to collect and digitize the detectors output, generating a data packet to be sent to the experiment’s central acquisition. This data acquisition system is designed and tested to withstand the high trigger rate and detector’s throughput.
Speaker: Dr Keida Kanxheri (INFN - National Institute for Nuclear Physics) -
17:56
A modular and flexible data acquisition system for a cosmic rays detector network 2m
We describe a modular data acquisition system developed as the foundation of a cosmic ray detector network. Each detector setup is composed of an independent hardware device that can be controlled and read out through the Internet. This device is designed to acquire and process the signal of up to eight different detector planes. Each of these detector planes uses plastic scintillator slabs that are optically coupled to silicon photomultipliers (SiPM). The main readout is based on a programmable system-on-a-chip (PSoC), a flexible and re-configurable commodity hardware that is used to implement the trigger and timing logic.
Speaker: Guilherme Tomio Saito (Universidade de Sao Paulo (BR)) -
17:58
The new waveform digitizer (DIRAC-V2) for the Mu2e electromagnetic calorimeter at Fermilab 2m
This paper describes design and performance of the new Digitizer ReAdout Controller of the Mu2e electromagnetic calorimeter, which consists of two 674 CsI crystal annular matrices readout by SiPMs. The 20-channel board performs a 200 MHz sampling of the SiPM signals transmitted by the front-end electronics. The operation in the Mu2e harsh environment, with an expected total ionizing dose of 12krad and neutron fluence of 5x1010n/cm2@1MeVeq(Si)/y, 1T magnetic field, level of vacuum of 10-4 Torr made the design challenging. We report on the board architecture, and design, as well as on the results of the prototype qualification and performance test.
Speaker: Elena Pedreschi (Universita & INFN Pisa (IT)) -
18:00
New Generation RCE system for the Rd53 Pixel Front End chip readout 2m
The RCE (Reconfigurable Cluster Element) platform is a general-purpose system-on-chip data acquisition system, which is broadly deployed in various experiments, including ATLAS. A new generation of bench-top RCE system, based on Xilinx UltraScale+ MPSoC, is developed to support the Rd53a/b module and system testing with high performance. The RCE system also serves as the primary platform for validating the data transmission design of the ATLAS ITk pixel system with the same or equivalent components as the eventual ITk pixel system.
Speaker: Zijun Xu (SLAC National Accelerator Laboratory (US)) -
18:02
DAMIC-M electronics and acquisition system 2m
We present the status of the DAMIC-M (Dark Matter In CCD at Modane) electronics and acquisition system. This first version controls a skipper CCD and measure the pixel charge with a single electron resolution. It was designed to allow optimization with respect to clocking and readout parameters to achieve the best tradeoff between noise and readout speed. We present the implementation of the full system composed of a mother board, a front end ASIC, the sequencer and ADC boards.
Speaker: Romain GAIOR (LPNHE) -
18:04
The Caribou DAQ System – Current Status and Ongoing Developments 2m
Caribou is a flexible open-source DAQ system designed for laboratory and high-
rate beam tests and easy integration of new silicon-pixel detector prototypes. It
uses common hardware, firmware and software components that can be shared
across different projects, thereby reducing the development effort and cost for
such readout systems significantly.Speaker: Eric Buschmann (CERN) -
18:06
CMS Muon Drift Tubes HL-LHC Slice Test 2m
To tolerate the High Luminosity LHC (HL-LHC) data taking conditions on the detector electronics of the CMS Drift Tubes (DT) chambers need to be replaced during Long Shutdown 3. The first prototype of the HL-LHC electronics for the On detector Board for the DT chambers (OBDT) have been installed in CMS connected to the DT chambers of one out of sixty sectors and integrated in the central data acquisition and trigger system. The signals from the chambers are split and reach both the legacy and Phase 2 demonstrator chains, which will allow them to operate in parallel during LHC collisions.
Speaker: Barbara Alvarez Gonzalez (Universidad de Oviedo (ES)) -
18:08
Development of AC-LGADs for high-rate Particle Detection 2m
Low-Gain Avalanche Detectors (LGADs) are thin silicon detectors with moderate internal signal amplification yielding excellent time resolution of close to 10’s ps. AC-LGADs (aka Resistive Silicon Detectors RSD) have un-segmented gain layer and N-layer, and a di-electric layer separating the metal readout pads, guaranteeing a 100% fill-factor. The high spatial precision of few 10‘s µm is achieved by using the pulse height information from multiple pads.
We present an evaluation of the high-rate suitability of AC-LGADs based on focused IR-Laser scans wrt the limitations that high-speed readout ASICs can expect from high-flux charged particles and X-rays.Speaker: Gabriel Saffier-Ewing
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Posters Trigger
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Ultra-low jitter clock distribution for the trigger electronics of the ATLAS New Small Wheel experiment. 3m
The low radiation levels on the outer rim of the New Small Wheels of the the ATLAS experiment gave the opportunity of utilizing commercial FPGAs for the trigger electronics of the sTGC detectors. The demanding requirements of the Xilinx FPGA transceivers in terms of jitter imposed the development of an ultra-low jitter clock distribution scheme. This scheme includes a custom board placed in the USA15 which distributes 32 clocks over 100 m fiber cables with a jitter of about 700fs. The design techniques for noise reduction and the results are presented.
Speaker: Panagiotis Gkountoumis (CERN) -
17:23
The MDT Trigger Processor development for the ATLAS Level-0 Muon Trigger at HL-LHC 3m
The novel MDT Trigger Processor (MDTTP) is a fundamental component of the ATLAS Level-0 Muon trigger upgrade, designed to meet High-Luminosity LHC requirements. The MDTTP will use MDT hits to improve the momentum resolution of muon candidates provided by RPC and TGC detectors and to reduce the fake rate.
A hardware demonstrator has been developed based on the Apollo ATCA platform.
The demonstrator includes two large FPGAs, high-speed FireFly optical transceivers, and other peripheral hardware. We present here demonstrator test results, plans for the prototype design, firmware implementation, including the core algorithm and control and monitoring.Speaker: Guillermo Loustau De Linares (University of Massachusetts (US)) -
17:26
The ATLAS Electron Feature Extractor Module: Design, Manufacture and Test 3m
In Run 3, the ATLAS Level-1 Calorimeter Trigger (L1Calo) will be augmented by an Electron Feature Extractor (eFEX), which will identify isolated electron/photon and tau particles. Each eFEX module accommodates 424 signals at 11.2 Gb/s. Three generations of eFEX have been manufactured, and the design, manufacturing, and testing processes have been optimised. The firmware for the eFEX is managed using a custom system that has since been adopted by ATLAS TDAQ as the standard for the Phase-II upgrade. Presented here are the eFEX design, test results, and lessons learned from prototype and pre-production manufacturing.
Speaker: Saeed Taghavirad (Science and Technology Facilities Council STFC (GB)) -
17:29
The NA62 liquid krypton electromagnetic calorimeter fast readout implementation and data taking performances 3m
The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay $K^+\rightarrow\pi^+\nu\bar{\nu}$. The calorimeter level 0 trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 trigger processor, readout data is collected to be sent to L1 software trigger level. We present the novel implementation of the readout data collection and forwarding system in the multiple layers of the calorimetric trigger structure. We will also present the performance evaluation of the new system that will be measured in the incoming data taking.
Speaker: Roberto Ammendola (INFN e Universita Roma Tor Vergata (IT)) -
17:32
Progress report on the online processing upgrade at the NA62 experiment 3m
In 2021 the NA62 experiment at CERN is restarting data taking with upgraded instrumentation. In this framework we present the commissioning test of the new L0 trigger processor offering enhanced bandwidth, updated interconnection technology and increased logic capabilities with respect to its predecessor. We also present the latest performances of two computing-intense additional components dedicated to the online processing of RICH detector information: a ring reconstruction algorithm on GPU for electron identification and a fast neural network developed with HLS tools on FPGA for ring multiplicity counting. Finally we evaluate the impact of introducing such features in the TDAQ system.
Speaker: Matteo Turisini (Sapienza Universita e INFN, Roma I (IT)) -
17:35
Upgrade of the CMD-3 trigger system. 3m
In 2017, the luminosity at the VEPP-2000 collider at the Budker Institute of Nuclear Physics SB RAS, Novosibirsk, has increased. In this regard, it was decided to upgrade the trigger system of the CMD-3 detector. For this, the development of a device called the “Final Decision Block” was started. In this paper, we consider the designing and debugging process of the created block, as well as its implementation in the Data Acquisition System of the CMD-3 detector. The test results are presented both at the test bench and directly as part of the Data Acquisition System on the detector.
Speaker: Mr Leonid Epshteyn (Budker Institute of Nuclear Physics) -
17:38
Hardware Design of the Generic Rear Transition Module for Global Trigger System of the ATLAS Phase II Upgrade 3m
In the ATLAS Phase-II upgrade, Global Trigger is a new subsystem that will bring event filter-like capability to the Level-0 trigger system. A common hardware platform in ATCA form factor named Global Common Module (GCM) is proposed to be configured as nodes in the Global Trigger. To mitigate the risk and simplify the GCM hardware design, a Generic Rear Transition Module (GRM) is developed. GRM, which is implemented with a Xilinx Versal Prime FPGA and sufficient multi-gigabit transceivers, aims at system control and communication with FELIX, it could also provide additional processing or readout capacity.
Speaker: Weigang Yin (Brookhaven National Laboratory (US)) - 17:41
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ASICConvener: Angelo Rivetti (Universita e INFN Torino (IT))
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11:40
Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC. 16m
The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that show limited coverage and long testing time. Scan-chain design, memory and Logic Built-In-Self-Test have been adapted for radiation-hard ASICs and introduced on-chip for a novel testing approach. Design flow and implementation choices will be presented together with silicon results.
Speaker: Gianmario Bergamin (CERN) -
12:00
Test results of RD53B chips for ATLAS and CMS phase-2 pixel upgrades 16m
Following the RD53A demonstrator, the ItkPix (ATLAS) and CROC (CMS) pixel readout chips are being developed within the RD53 collaboration for the HL-LHC pixel detector upgrades of the two experiments. The two chips are based on a common design, called RD53B, in 65nm CMOS technology and are optimized for very high rate (3GHz/cm2) and radiation levels (>500Mrad). The ATLAS pre-production chip ItkPixV1 was submitted in March 2020 and the CMS pre-production chip CROCv1 is being submitted in May 2021.
This contribution gives a general overview of the chip architecture and discusses the characterization and testing of the pre-production chips.Speaker: Dominik Koukola (CERN) -
12:20
Performance simulations and characterization of RD53 pixel chips for ATLAS and CMS HL-LHC upgrades 16m
The RD53B pixel readout chip has been submitted for fabrication, meeting specifications of the ATLAS and the CMS experiments for HL-LHC upgrades. Performance characterization of a readout chip in terms of link data rate, average readout latency and efficiency of hit data is essential to evaluate operation of pixel sensors at an extreme interaction rate. At the same time it is complex due to its dependence on various environmental conditions and operational settings. In this work, readout performance parameters and their simulation results for various detector positions of the ATLAS and the CMS experiments are presented.
Speaker: Attiq Ur Rehman (University of Bergen (NO)) -
12:40
HGCROC3: the front-end readout ASIC for the CMS High Granularity Calorimeter 16m
For the CMS HGCAL, the final version of the 72-channel front-end ASIC (HGCROC3) was submitted in December 2020. HGCROC3 includes low-noise/high-gain preamplifier/shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge measurement over the linear range of the preamplifier. In the saturation range a discriminator and TDC provide the charge information from TOT (200ns dynamic range, 50ps binning). A fast discriminator and TDC provide timing information to 25ps accuracy. The chip embeds all necessary ancillary services: bandgap circuit, PLL, threshold DACs. We present the experimental results on the latest and final version HGCROC3 received in April 2021.
Speaker: Mr Frederic Dulucq (OMEGA - Ecole Polytechnique - CNRS/IN2P3)
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Lunch break 1h
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ASICConvener: Walter Snoeys (CERN)
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14:00
Precision timing ASIC for LGAD sensors based on a Constant Fraction Discriminator – FCFD0 16m
Silicon detectors with excellent time resolution will play a critical role in future collider experiments, providing a new tool in event reconstruction. The Low Gain Avalanche Detectors (LGAD) have been demonstrated to provide the required time resolution and radiation tolerance. We will present the FCFD0 ASIC developed to read out LGAD signals. The FCFD0 utilizes Constant Fraction Discriminator (CFD) algorithm to time-stamp the time-of-arrival, which has several advantages compared to Leading Edge discriminator, and promises to be more reliable in operation. Results from the first prototype chip produced in TSMC 65 nm node, will be presented.
Speaker: Thomas Zimmerman (Fermi National Accelerator Lab. (US)) -
14:20
Detection Performance of MIMOSIS-1, a CMOS Sensor Prototype Developed for the CBM-MVD 16m
The Micro-Vertex Detector of the CBM experiment at FAIR/GSI requires very light detector stations equipped with highly granular and thin pixel sensors adapted to hostile running conditions. A specific CMOS pixel sensor, called MIMOSIS, is being developed for this purpose. Inspired by the ALPIDE sensor equipping the ALICE ITS, its design is adapted to higher hit rate and radiation tolerance. The first full scale prototype was fabricated in 2020 with several epitaxial layer variants. The chips were assembled in a beam telescope which was operated at DESY. First results of the signal-to-noise and detection performance evaluations will be presented.
Speaker: Dr Roma BUGIEL (IPHC) -
14:40
First Measurement on TimeSPOT1 ASIC: a Fast-Timing, High-Rate Pixel-Matrix Front-End 16m
This work presents the first measurements on the Time SPOT1ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32×32 channels hybrid-pixel matrix. Targeted to 4D-Tracking applications in High Energy Physics experiments, the system aims to achieve a timing resolution of 30 ps or better at a maximum event rate of 3 MHz/channel with a Data Driven interface. Power consumption can be programmed to range between 1.2 W/$cm^{2}$ and 2.6 W/$cm^{2}$. The presented results include operation and performance characterization.
Speaker: Lorenzo Piccolo (INFN Torino) -
15:00
FAST2: a new family of front-end ASICs to read out thin Ultra-Fast Silicon detectors achieving picosecond time resolution. 16m
We present the first results obtained with the FAST2 family of ASICs. The FAST2 ASIC family, designed in the 110 nm CMOS technology, has been optimized for the read-out of Ultra-Fast Silicon Detectors, aiming to achieve a combined total time resolution of less than 40 ps. In the FAST2 family, the ASIC (FAST2_A) presents 16 channels and has only the amplification stage with a timing jitter lower than 16 ps experimentally, and power dissipation of 1 mW/ch.
Speakers: Alejandro David Martinez Rojas (INFN - National Institute for Nuclear Physics), Marco Ferrero (Universita e INFN Torino (IT))
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Break 20m
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ASICConvener: Ping Gui
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Towards the next generation of CERN radiation monitoring front end ASICs 16m
The front-end electronics of Ionization chamber for radiation protection demands challenging sensitivity requirements in the femtoampere range and a wide dynamic range. This work details the development trajectory that culminated in a single chip solution with current measurement capability spanning nine decades. The various Application Specific Integrated Circuits designed in the Radiation Protection team at CERN are explained. The challenges faced and the methodology adopted in designing ASICs for ultra-low current measurement is detailed. The latest version of the ASIC designed in 130nm technology can measure currents from -6 fA to -20 µA with an accuracy of 7%.
Speaker: Sarath Kundumattathil Mohanan (Bergische Universitaet Wuppertal (DE)) -
16:00
A radiation tolerant 12 bits, 160 MS/s data conversion and transmission ASIC for the CMS electromagnetic calorimeter 16m
The readout electronics for the CMS Electromagnetic Calorimeter is
undergoing a re-design in order to cope with the LHC ugrade.
In particular, a fourfold increase in the sampling frequency
(from 40 to 160 MS/s) is required. Therefore a new readout ASIC
has been developed.
The ASIC, named LiTE-DTU, is designed in a CMOS 65 nm technology.
The LiTE-DTU embeds two 12 bits, 160 MS/s ADCs, a time window
based sample selection, lossless data compression and 1.28 Gb/s
serialization. An on-chip PLL provides the 1.28 GHz clock required by
the ADCs and the serializers from the 160 MHz clock.Speaker: Gianni Mazza (Universita e INFN Torino (IT)) -
16:20
The ETROC1: The first full chain precision timing prototype for CMS MTD Endcap Timing Layer (ETL) upgrade 16m
The Endcap Timing Readout Chip (ETROC) is being developed for the CMS MTD Endcap Timing Layer (ETL) for the HL-LHC, to process LGAD signals with time resolution down to 30ps per track. The ETROC1 is the first full chain precision timing prototype, including preamplifier and discriminator, as well as a new low power TDC design that performs time-of-arrival (TOA) and time-over-threshold (TOT) measurements. It also includes a 4x4 pixel array with precision clock distribution network that is scalable to the final full size 16x16 array. The performance of ETROC1 with bench test and beam test results are presented.
Speaker: Tiehui Ted Liu (Fermi National Accelerator Lab. (US)) -
16:40
A Sub-Picosecond Digitally-Controlled Phase Delay 16m
The use of precision timing measurements will be a major tool at the HL-LHC, where it will be used to suppress pile-up and to search for long-lived particles. To control a reference clock with sub-picosecond accuracy, we have fabricated in the TSMC 65nm process a digitally controlled phase shifter. It is composed of a chain of 66 cells, each with a digitally controlled planar wave guide with either a short or long delay. With this a reference clock's phase can be controlled to a precision of 200 fs with dynamic range of 13 ps.
Speaker: Prof. Yahya Tousi (The University of Minnesota)
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Poster session
Same content as the poster session of Tuesday 21 at 10h00:
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ASICConvener: Wladyslaw Dabrowski (AGH University of Science and Technology (PL))
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First experimental results with the version TOFHIR2X of the front-end ASIC of the MTD/BTL detector in the CMS experiment 16m
TOFHIR2 is the front-end ASIC for the barrel timing layer (BTL) of the MIP timing detector for the CMS upgrade for HL-LHC, aiming at 30-60 ps resolution throughout HL-LHC lifetime. The BTL consists of LYSO:Ce crystals coupled to SiPMs which will suffer radiation damage. Relative to the first version of the front-end ASIC (TOFHIR2A), TOFHIR2X implements improved circuitry for mitigation of the SiPM dark count noise (DCR) as well as a new current mode discriminator. We present an overview of the TOFHIR2 requirements and design, simulation results and the first measurements with TOFHIR2X silicon samples associated to LYSO/SiPM prototype sensors.
Speaker: Tahereh Sadat Niknejad (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part) -
12:00
The Gotthard-II readout ASIC and detector system 16m
Gotthard-II is a charge-integrating microstrip detector developed for experiments and diagnostics at free-electron lasers using hard X-rays of 5 keV–20 keV. Its potential scientific applications include X-ray absorption/emission spectroscopy, energy dispersive experiments, as well as veto signal generation for pixel detectors. The Gotthard-II ASIC has been designed in several optimization steps in order to meet the requirements of the European XFEL, i.e. single photon sensitivity, large dynamic range as well as a high frame rate of 4.5 MHz. The ASIC design and performance will be presented. The detector system as well as the results from beam tests will be discussed.
Speaker: Jiaguo Zhang (Paul Scherrer Institut)
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Programmable Logic, Design Tools and MethodsConvener: Johan Alme (University of Bergen (NO))
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12:20
Hog: handling HDL repositories on git 16m
Handling HDL project development within large collaborations presents many challenges in terms of maintenance and versioning, due to the lack of standardized procedures. Hog (HDL on git) is a tcl-based open-source management tool, created to simplify HDL project development and management by exploiting git and Gitlab Continuous Integration (CI).
Hog is compatible with the major HDL IDEs from Xilinx and Intel-FPGA, and guarantees synthesis and placing reproducibility and binary file traceability, by linking each binary file to a specific git commit. Hog-CI validates any changes to the code, handles automatic versioning and can automatically simulate, synthesise and build the design.
Speaker: Davide Cieri (Max Planck Society (DE)) -
12:40
PAM-4 implementation study for future high-speed links 16m
With the ever-increasing amount of data from HEP experiments, the transmission rates must keep up. To mitigate the exponential growth of the total loss due to the increased frequency, the 4-Level Pulse-amplitude Modulation (PAM-4) could be envisaged, allowing to reach 56 Gbps or even 112 Gbps in extremely high-end applications. A system using PAM-4 encoders and transceivers has been built based on FPGA as a proof-of-concept to demonstrate potential future links. In this talk, the PAM-4 modulation will be introduced, the performance of this initial system will be presented and the challenges for future links will be discussed.
Speaker: Chaowaroj Wanotayaroj (CERN)
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12:20
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Lunch break 1h
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14:00
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Programmable Logic, Design Tools and MethodsConvener: Johan Alme (University of Bergen (NO))
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14:00
Hough-transform-based FPGA track processor for the ATLAS experiment at CERN 16m
The Hough-transform-based FPGA track processing is considered for the trigger system of the ATLAS detector at the Large Hadron Collider at CERN as a part of the upgrade for the High-Luminosity program. The prototype firmware has been developed to evaluate system size. The track processing is organized as a pipeline to increase data processing and clock rates. This Hough transform accumulator can use input pixel and strip hits, stubs, and space-points. It outputs track candidates for bins that meet the track reconstruction requirements. The accumulator is configurable with number of bins in φ and q/pT, and number of input hits.
Speaker: Tong Xu (Argonne National Laboratory (US)) -
14:20
Automated firmware generation and continuous testing for the CMS HGCAL trigger primitive generator 16m
A first version of the firmware blocks of the trigger primitive generator for the CMS endcap calorimeter upgrade (HGCAL) are being implemented, in order to assess the FPGA resource requirements and dimension the system. For the development of some of these blocks, a data-driven design flow is used to automate the production of multiple firmware variants based on VHDL and HLS C/C++ templates. In addition, the design steps are integrated into Continuous Integration tools to automatically test and validate every change, and as much as possible avoid repetitive human tasks and the associated errors.
Speaker: Jean-Baptiste Sauvan (Centre National de la Recherche Scientifique (FR)) -
14:40
FPGA implementation of RDMA for ATLAS Readout with FELIX in High Luminosity LHC 16m
The FELIX system is used as an interface between front-end electronics and commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. RDMA communication is implemented using software on both end of the links. Exploring opportunities to improve data throughput as part of the High Luminosity LHC upgrade, an implementation for RDMA support in the front-end FELIX FPGA is being developed. We present a proof-of-concept RDMA FPGA implementation, which will help inform the design of the FELIX platform for High Luminosity LHC.
Speaker: Matei Vasile (IFIN-HH (RO))
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Radiation Tolerant Components and SystemsConvener: Salvatore Danzeca (CERN)
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15:00
Design and qualification of the Mu2e electromagnetic calorimeter radiation monitor system 16m
The Mu2e calorimeter and read-out electronics are hosted inside the superconducting magnet cryostat and exposed to an intense flux of ionizing and non-ionizing particles. The performance of a number of components is compromised by radiation damage. This includes the scintillating crystals and silicon photomultipliers (SiPM) whose performance degrades proportionally to both dose and neutrons fluence. The development of a radiation monitor is of vital importance for a reliable detector operation. A system that measures the dose and neutron fluence based on 24 peripheral stations and 4 master units distributed along the detector was built and calibrated.
Speakers: Dr Franco Spinella (INFN Pisa (IT)), Franco Spinella (Universita & INFN Pisa (IT))
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Break 20m
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Radiation Tolerant Components and SystemsConvener: Salvatore Danzeca (CERN)
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Single Event Effects on the RD53B Pixel Chip Digital Logic and On-chip CDR 16m
The RD53B chip for HL-LHC upgrades of ATLAS and CMS needs to provide reliable operation in a radiation hostile environment with inevitable Single Event Effects. To answer the challenge, substantial efforts are made to protect and evaluate the critical parts of digital logic with different TMR schemes and to characterize the on-chip CDR. Cross-section for each TMR scheme and its effective SEE sensitivity are measured in several SEE campaigns. The on-chip CDR is characterized by measuring the SEE-induced phase shifts of its output clocks and their implication on the high-speed link stability. Results from these campaigns will be presented.
Speaker: Jelena Lalic (CERN) -
16:00
Low dose rate irradiation of the RD53A chip with Kr-85 beta source 16m
To test the performance of the future pixel readout chip in the harsh High Luminosity LHC (HL-LHC) environment, an irradiation experiment has been setup with gaseous Kr-85 beta source with dose rate of about 7 rad/s. This setup was designed to emulate as closely as possible operation in the HL-LHC conditions of the ATLAS detector inner layer, including temperature, radiation, and continuous electrical operation. The low dose rate irradiation setup has been running since September 5th 2018 at a temperature of -15 degrees Celsius. The first results will be presented with a 500 Mrad total dose received.
Speaker: Aleksandra Dimitrievska (Lawrence Berkeley National Lab. (US)) -
16:20
Radiation hardness and timing performance in MALTA monolithic Pixel sensors in TowerJazz 180 nm 16m
The MALTA family of depleted monolithic Pixel sensors produced in TowerJazz 180 nm CMOS technology target radiation hard applications for the HL-LHC and beyond. Several process modifications and front-end improvements have resulted in radiation hardness up to 2e15 n/cm2 and time resolution below 2 ns, with uniform charge collection efficiency across the Pixel of size 36.4 x 36.4 um2 with a 3 um2 electrode size. This contribution will present the results from new cascoded front-end flavour that further reduces the RTS noise and improves the threshold reach, and the comparison of samples produced on high-resistivity epitaxial silicon with Czochralski substrates.
Speaker: Milou Van Rijnbach (University of Oslo (NO)) -
16:40
The radiation-hard low-Voltage LDO for HGCAL in the CMS Phase-2 upgrade 16m
The CMS detector will see the replacement of its existing endcap calorimeter with a new high granularity calorimeter (HGCAL), which will need to withstand much higher radiation levels than the present endcaps. This poses tight constraints on the front-end electronics, including the powering chain. As part of this chain, a low-dropout linear regulator (LDO) has been designed and prototyped for post-regulation for HGCAL, providing extremely low noise stable power to the analog front-end. We present results from tests of the LDO, including from a detailed irradiation campaign (TID, SEE, neutrons).
Speaker: Mr Aamir Irshad (Universite Libre de Bruxelles (BE))
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SC meeting 1h 30m
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TriggerConvener: Gregory Michiel Iles (Imperial College (GB))
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Integration and commissioning of the ATLAS Muon-to-Central-Trigger-Processor Interface for Run-3 16m
The Muon-to-Central Trigger Processor Interface (MUCTPI) was completely redesigned as part of the ATLAS Level-1 trigger upgrade for Run 3 of the LHC. The new system is implemented as a single ATCA module, using three large state-of-the-art FPGAs and high-density fibre-optic modules. 208 high‑speed links receive trigger information from the muon trigger detectors, while 60 links are used to send processed trigger information to the Topological Trigger and the Central-Trigger-Processor. Extensive integration tests with all input and output systems have shown that the data transfer is stable and reliable. We will also report on the commissioning of the MUCTPI.
Speaker: Sabrina Perrella (CERN) -
12:00
The Ocean and Octopus designs for the Phase-2 upgrade of the CMS L1 muon trigger 16m
The throughput and processing requirements of the CMS L1 Trigger for HL-LHC require platforms with high-end FPGAs and many high speed optical links. The Ocean platform features the largest ZYNQ Ultrascale+ SoC and 72 transceivers connected to on-board optics reaching rates up to 28 Gbps. The Octopus^2 design targeted for the CMS Muon Trigger at HL-LHC features a Virtex Ultrascale+ 13P FPGA in and 128 bi-directional links connected through copper to QSFP and QSFP-DD optics. Signal integrity results, comparison of different layout strategies and heat management for large FPGAs featuring lidless packages will be discussed.
Speaker: Michail Bachtis (University of California Los Angeles (US)) -
12:20
The Prototype Hardware Design and Test of Global Common Module for Global Trigger System of the ATLAS Phase II Upgrade 16m
The HL-LHC will start operations in 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined. Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition system. Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The hardware implementation of the Global Trigger consists of three primary components: Multiplexer Processor layer, Global Event Processing layer, and demultiplexing Global-to-CTP Interface, all of which have identical hardware. The single Global Common Module hardware is implemented across the Global Trigger system.
Speaker: Filiberto Bonini (Brookhaven National Laboratory (US)) -
12:40
A CMS Level-1 Track Finder for the HL-LHC 16m
The High-Luminosity LHC will put significant demands on trigger systems. To control trigger thresholds, the CMS Collaboration is designing a novel Level-1 track trigger. The Outer Tracker will use modules with pairs of sensor layers to read out hits compatible with charged particles above 2-3 GeV. The system will combine these front-end trigger primitives to reconstruct tracks, providing a measurement of P_T, \eta , \phi, and z_0. This presentation will introduce the CMS L1 track finding system: the algorithm and its estimated performance, hardware prototypes, and the unique challenges associated with this system.
Speaker: Brent Yates (Ohio State University (US))
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Lunch break 1h
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14:00
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TriggerConvener: Gregory Michiel Iles (Imperial College (GB))
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14:00
FPGA-based real-time data processing for accelerating reconstruction at LHCb 16m
In Run-3 beginning in 2022, the LHCb software trigger will start reconstructing events at the LHC average crossing rate of 30 MHz. Within the upgraded DAQ system, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction, in view of future runs at even higher luminosities.
One such solution is a highly-parallelized custom tracking processor (“Artificial Retina”), implemented in state of the art FPGA devices connected by fast serial links.
We describe the status of the development of a life-size demonstrator system for the reconstruction of pixel tracking detectors, that will run on real data during Run-3.
Speaker: Federico Lazzari (Universita di Siena & INFN Pisa (IT)) -
14:20
A 3D FPGA Track Segment Seeding Engine Based on the Tiny Triplet Finder 16m
An exercise of implementing and testing a 3D track segment seeding engine core based on the Tiny Triplet Finder in a low-cost FPGA device is reported. The seeding engine is designed to preselect and group hits (stubs) from cylindrical detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hugh transform space for r-z view and a Tiny Triplet Finder for r-phi view to implement 3D constraints. The seeding engine is organized as a pipeline so that each hit is processed in a single clock cycle. Test results show that the seeding engine operates as expected.
Speaker: Jinyuan Wu (Fermi National Accelerator Lab. (US))
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14:00
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Production, Testing and ReliabilityConvener: Marcus Julian French (Science and Technology Facilities Council STFC (GB))
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14:40
Frontend and backend electronics for the ATLAS New Small Wheel Upgrade 16m
The present ATLAS innermost endcap muon station will be replaced by a New Small Wheel (NSW) detector to handle large trigger and readout data rates expected at high luminosity LHC runs. Two new detector technologies, Resistive Micromegas (MM) and small-strip Thin Gap Chambers (sTGC), will be used for triggering and tracking. A common readout path and two separate trigger paths are developed. It is challenging to integrate and commission this complicated detector-electronics system with 128 MM and 192 sTGC detector modules and 2.4M readout channels. I will discuss the design of the NSW electronics and the status of detector-electronics intergration.
Speaker: Siyuan Sun (University of Michigan (US)) -
15:00
Design, Production, Burn-in and Tests of the hybrid circuits of the Upstream Tracker at the LHCb detector 16m
Abstract: We present a detailed description of the design, prototyping and production of the hybrid circuits for the front-end electronics of the Upstream Tracker at LHCb. The multilayer flexible circuits are design to host the front-end chips, ensure a low radiation length and withstand the harsh environment conditions of the data taking.
Speaker: Federico De Benedetti (Università degli Studi e INFN Milano (IT))
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Break 20m
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Production, Testing and ReliabilityConvener: Marcus Julian French (Science and Technology Facilities Council STFC (GB))
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15:40
Augmenting Quality and Throughput of Functional Testing and Device Characterization for the ABCStar ATLAS-ITk Strips Readout ASIC Through a Semiconductor Test Industry Partnership 16m
To instrument the 60 million ATLAS ITk Strips Sensor channels, CERN developed the mixed-signal ABCStar front-end readout ASIC. Over 350,000 devices on 753 wafers containing 466 ASICs each will be extensively tested to provide the chips required for sensor modules. Carleton achieved a 3-10 times improvement in throughput, without compromising test coverage or data collection, by developing new tools and techniques in partnership with a specialist wafer testing company – jointly overcoming the methodological, technical, and semantic divides that exist between physics laboratories and the semiconductor test industry, and opening new possibilities in ASIC testing for future particle physics projects.
Speaker: James Michael Botte (Carleton University (CA)) -
16:00
Hybrids Acceptance Tools for the CMS Phase Two Tracker Upgrade 16m
Up to fifty thousand front-end and service hybrids are required for the CMS Tracker Phase Two Upgrade. These hybrids, which are built on carbon fibre stiffened circuits and contain several flip-chip ASICs, will be glued in module structures, making repairs almost impossible. Due to their complexity, testing within production is a very important aspect. A multiplexed testing infrastructure, based on custom crates and test cards will be presented. This testing hardware is supported by software tools to enable the exhaustive verification of hybrids at the manufacturing sites and for their acceptance within the collaboration.
Speaker: Irene Mateos Dominguez (CERN) -
16:20
The lpGBT production testing system 16m
The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC designed to implement multipurpose high-speed bidirectional serial links in HEP experiments. Having more than 320 programmable registers, the ASIC is highly configurable. Its test must cover a large variety of functionalities which will be validated at three different power-supply voltages, two temperatures and over more than 1000 parameters. As more than 175 000 chips will be produced, optimizing the test duration is also a strong requirement. In this talk, an overview of the lpGBT v1 production test system will be given, challenges will be presented, and performance will be discussed.
Speaker: Nour El Houda Guettouche (Centre National de la Recherche Scientifique (FR))
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Closing
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