TWEPP 2010 Topical Workshop on Electronics for Particle Physics

20 Sept 2010, 14:00 → 24 Sept 2010, 18:00 Europe/Zurich

Aachen, Germany

Francois Vasey (CERN), Philippe Farthouat (CERN)

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

Presentations are available here

Proceedings are available here
 

Monday, 20 September

Introduction and Welcome

Conveners: Francois Vasey (CERN), Prof. Lutz Feld (RWTH Aachen University)

1 Introduction and Welcome

Speakers: Francois Vasey (CERN), Mrs Heather Hofmeister (RWTH Aachen University), Lutz Feld (RWTH Aachen University)

Slides

• Local_Information.pdf
• Local_Information.pptx
• TWEPP10OpeningVasey.pdf
• TWEPP10OpeningVasey.ppt

OPENING 1

Convener: Francois Vasey (CERN)

2 High Energy Physics in Germany: Activities and Perspectives

Speaker: Bernhard Spaan (Fachbereich Physik - Universitaet Dortmund)

Slides Twepp.pdf Twepp.ppt

3 Advanced Electronics for Particle Physics and Beyond - Projects at German University Labs

We will present an overview of current major electronics projects carried out by German groups in the framework of the S-LHC, b-factories and future linear colliders. Cooperations with other scientific fields like hadron physics, medical physics and biophysics will be shown. Finally, the challenge of maintaining a competitive infrastructure for the development of advanced electronics technologies at universities will be discussed with special emphasis on the Helmholtz-Alliance "Physics at the Terascale".

Speaker: Karlheinz Meier (Kirchhoff-Institut fur Physik (KIP))

Slides TWEPP2010-kme.pdf TWEPP2010-kme.pptx

4 Particle Physics at RWTH Aachen University

The physics department of RWTH Aachen University has a long tradition in particle physics. Today, four institutes are active in this field, three in experiment and one in theory. A common focal point is LHC physics. All experimental institutes have contributed to the construction of the CMS experiment, mainly to the silicon tracker, muon system and computing, and are now analysing the data. Some groups have started R&D projects for the upgrade of the pixel, tracking and muon systems of CMS for SLHC. The institutes are participating in a number of other particle and astroparticle physics experiments as well. Among these are AMS, Auger, balloon-borne experiments, D0, and several neutrino experiments including IceCube and DoubleChooz. This talk will review the current activities and future plans.

Speaker: Prof. Lutz Feld (RWTH Aachen University)

Slides Particle_Physics_at_RWTH.pdf Particle_Physics_at_RWTH.pptx

16:00 Break

OPENING 2

Convener: Philippe Farthouat (CERN)

5 Physics for pedestrians

Speaker: Patrick Michel Puzo (Laboratoire de l''Accelerateur Lineaire (LAL) (IN2P3) (LAL))

Slides twepp_puzo.pdf

6 Electronics for the European XFEL: AGIPD a high frame rate camera

The European free electron laser (EuXFEL) facility will generate coherent and intense X-ray flashes at rates up to 27000 per second. X-rays flashes are generated by passing bunches of electrons, accelerated to 17.5GeV by a superconducting linear accelerator, through magnetic undulators in which electrons emit X-ray flashes by a SASE lasing process. Each flash is intense enough to produce a full diffractive picture of scattering targets, such as biological molecules, which, whe reconstructed, will allow new insights into material structure and dynamics. Dedicated two dimensional area camera systems, e.g. AGIPD, are being developed to record up to 5000 images/second with a resolution of 1Mega-Pixel and a dynamic range of 0 – 104 photons/pixel. This talk will present the accelerator and detectors techniques used and will emphasis the electronics developments being made.

Speaker: Peter Goettlicher (Deutsches Elektronen Synchrotron (DESY))

Slides TWEPP2010_goettlicher.pdf TWEPP2010_goettlicher.ppt

7 LHC project, Status and Plans

The Large Hadron Collider is presently in its first year of operation for High Energy Physics. The status of beam operation is discussed, presenting the evolution of beam parameters, achieved performance, beam energy and delivered luminosity. Expected and observed limitations are analyzed and the plans for further increases in LHC intensity, luminosity and beam energy are reviewed. Both short term and long term plans are presented

Speaker: Dr Ralph Assmann (CERN)

Slides slides

18:45 Welcome Drink

Tuesday, 21 September

PLENARY 1 - ASICs and FPGAs at ESA

Convener: Philippe Farthouat (CERN)

8 Single Event Effect mitigation in digital integrated circuits for space

Integrated circuits (IC) used in a space environment are exposed to solar and cosmic radiation, causing several adverse effects in the IC. Total Ionising Dose (TID) effects may lead to threshold voltage shift, increased leakage currents and reduced circuit speed. With advanced (deep-) sub-micron technologies, TID is of decreasing concern for most of the space applications (~ 100 krad) and might not need special mitigation. For certain long-duration deep-space missions however, exposed to doses in the Mrad domain, the dose effects are mitigated by adequate transistor geometries and guard-rings in library cells, and by taking sufficient design margins (derating), anticipating the end-of-life degradation. The main focus of this presentation is on how to protect space IC's against the second group of radiation effects, called Single Event Effects (SEE), which are caused by the interaction of (heavy) ions with the semiconductor material, generating electron-hole pairs leading to voltage peaks (glitches) within the drains of CMOS transistors. With decreasing capacitance of circuit nodes in advanced technologies, the SEE sensitivity increases. Depending on where in the circuit these glitches occur, the SEE can result in latch-up (SEL), transient pulses (SET) or bit upsets (SEU). SEU hardening design techniques usually involves some form of redundancy. The redundancy can take different forms, for example triple redundancy and voting at bit-level or error correcting codes (BCH/Hamming/Reed-Solomon). SET hardening is usually done by increasing buffer sizes and node capacitances or by temporal filtering. These modifications can be introduced at different levels of the design, at transistor, gate/flip-flop level implemented within a standard cell ASIC library, in the gate-level netlist, during place & route of an FPGA, in the HDL code, at the level of sub-blocks of an IC or even of complete IC's. The choice of the right method and degree of protection is one of the main concerns in space IC design. It depends on the IC technology (e.g. FPGA, standard cell ASIC) and very largely on the requirements, the requested degree of robustness. Not all circuits need to be 100% error free, and overdoing protection can be detrimental to the main goal of an IC, to fulfil its functional requirement within a given area and power budget. This is why a sound radiation assurance approach is required: at first specify requirements, investigate technology capabilities, define the radiation hardening strategy, calculate/validate the error rate. In many cases, adding redundancy contradicts the optimisation goals of commercial Electronic Design Automation (EDA) tools which were designed to avoid or remove redundancy, trying to select the smallest structure fulfilling a certain functional specification. Very often, specific tool set-ups or hand editing are required to produce a functional and rad-hard circuit. The effectiveness of the radiation mitigation has to be proven before the IC is manufactured and launched to space. Before manufacturing, formal verification is employed to analyse the correctness of the redundancy on one hand, but also to verify that the circuit retains its functionality after adding the hardening 'features'. Fault simulation or fault emulation on FPGA prototypes can be applied. After manufacturing, earth-based radiation testing in particle accelerators are performed.

Speaker: Roland Weigand (ESA)

Slides TWEPP2010-RW.pdf TWEPP2010-RW.ppt

ASICs: Parallel Session A1

Convener: Luciano Musa (CERN)

9 Wideband (8 GHz GBW) pulse amplifier for the integrated camera of the Cherenkov Telescope Array

A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC performing the digitization at 1-3 GS/s with a dynamic range of 16 bits. Input amplifiers have a voltage gain up to 20 and a bandwidth of 400 MHz. Being impossible to design an 8 GHz GBW fully differential operational amplifier in a 0.35 um CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that required GBW is achieved, with a linearity error smaller than 1% for a differential output voltage range of 2 V.

Speaker: Dr David Gascon (Universitat de Barcelona (ICC-UB))

Paper http://iopscience.iop.org/1748-0221/5/12/C12034/

Slides

• TWEPP2010_ACTA.pdf
• TWEPP2010_ACTA.ppt
• TWEPP2010_ACTA_Static.pdf

10 Design and Assessment of a Robust Voltage Amplifier with 2.5 GHz GBW and >100 kGy Total Dose Tolerance

In this work a voltage amplifier with a gain-bandwidth (GBW) product of 2.5Ghz utilizing adaptive biasing has been designed, using a standard CMOS technology. The amplifier was tested under gamma-radiation and temperature and features a gain degradation of 4,5 % up to a total dose of 100kGy and 5.6 % within a temperature range of -40 till 130°C. Finally the importance of including the standard deviation of the radiation induced threshold voltage in the simulation and design phase has been shown based on preliminary separate transistor measurements.

Speaker: Mr Jens Verbeeck (K.U. LEUVEN)

Paper http://iopscience.iop.org/1748-0221/6/01/C01076/

Slides TWEPP2010_final_jv.pdf TWEPP2010_final_jv.pptx

Systems, planning, installation, commissioning and running experience: Parallel Session B1

Convener: Stephen Quinton (Rutherford Appleton Laboratory)

11 The ALICE Silicon Pixel Detector: commissioning and optimization of the detector performance

This paper describes the tests and measurements made during the final commissioning of the ALICE Silicon Pixel Detector (SPD) in the first year operation with beams and the optimization of its performance. The ALICE Silicon Pixel Detector (SPD) is the innermost detector of the ALICE experiment. It consists of two cylindrical layers of pixel detectors, with a total of ~10^7 pixels. The detector has the unique feature of providing a prompt trigger signal that contributes to the first level trigger decision in ALICE. The trigger signal has been extensively used in the first trigger level of the ALICE experiment, for recording data of proton-proton collisions at energies of 900 GeV, 2.36 TeV and 7 TeV.

Speaker: Ms Costanza Cavicchioli (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12001

Slides 100916_Cavicchioli_twepp2010.pdf

12 The Silicon Pixel Readout Architecture for the Micro Vertex Detector of the PANDA Experiment

The electronic readout architecture for the silicon pixel sensors of the PANDA Micro Vertex Detector is presented. The pixels will provide timing, position and energy information; moreover, no trigger signal is foreseen, thus leading to a huge amount of data to be transmitted. The foreseen readout system is based on a custom ASIC development, named ToPiX, which provides time information via a time stamp synchronous with the 155 MHz global clock signal and energy information via the Time-over-Threshold technique. High speed serial links and early electrical to optical conversion are adopted to reduce the amount of cables and material.

Speaker: Mr Paolo De Remigis (INFN sez. di Torino)

Paper http://iopscience.iop.org/1748-0221/5/12/C12028

Slides deremigi.odp deremigi.pdf

10:40 Break

ASICs: Parallel Session A1

Convener: Luciano Musa (CERN)

13 Developments on SPIROC family chips (SiPM Integrated Read-Out Chip): Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

SPIROC embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 1 ns accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4kbytes RAM.

Speaker: Mr Ludovic Raux (Laboratoire de l'Accélérateur Linéaire (Orsay) / OMEGA)

Paper http://iopscience.iop.org/1748-0221/6/01/C01098

Slides TWEPP2010_SPIROC-5.pdf TWEPP2010_SPIROC-5.ppt

14 Readout Electronics for Low Dark Count Geiger Mode Avalanche Photodiodes Fabricated in Conventional HV-CMOS Technologies for Future Linear Colliders

The high sensitivity and excellent timing accuracy of Geiger-mode Avalanche PhotoDiodes makes them ideal sensors for particle tracking pixel detectors in high energy physics experiments. However, it is well known that they suffer from dark counts which in practice enlarge the necessary area of the readout electronics. Dark count can be dramatically reduced lowering the bias overvoltage of the diode to a few mV from the ground. Consequently, it is mandatory to replace the conventional front-end electronics by a readout circuit that enables low bias overvoltage operation. In this contribution, different readout topologies for low overvoltage biased GAPDs are presented.

Speaker: Mrs Eva Vilella (University of Barcelona)

Paper http://iopscience.iop.org/1748-0221/6/01/C01076/

Slides eva_TWEPP.pdf

15 Front end electronics for silicon strip detectors in 90nm CMOS technology; advantages and challenges

We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. A primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors on Super LHC experiments. On the example of presented design we will show critical aspects of the front end stages implemented in the deep submicron technologies. Particular effort has been put on the minimization of the power consumed by the front end electronics. The nominal power consumption providing ENC level below 800e- for the chip loaded with 5pF input capacitance is around 220uW per channel.

Speaker: Mr Jan Kaplon (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11024/

Slides Twepp2010Present.pdf Twepp2010Present.pptx

16 A Front-end ASIC for the readout of the PMT in the KM3NeT Detector.

A number of possible techniques exists for detecting high energy neutrinos from space. The most widely exploited method is the detection of neutrinos in large volumes of water or ice, using the Cherenkov light from the muons and hadrons produced by neutrino interactions with matter around the detector. A photon sensor (photo multiplier tube aka PMT) is housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. A new String structure approach for the readout of the OMs with multi-PMTs has been proposed for the KM3NeT[1] project. Stringent power budgeting, area constraints and cost command us to design a custom front-end ASIC for the PMT. The circuit amplifies the PMT signal and discriminates against a threshold level and delivers the information via LVDS signals. These LVDS signals carry highly accurate information on the Time of arrival (< 2ns) of photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of incident photons. A PROM block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I2C bus. The data is transmitted real-time to shore via fiber optics, where Time-stamping is done.

Speaker: Mr Deepak Gajanana (NIKHEF)

Paper http://iopscience.iop.org/1748-0221/5/12/C12040/

Slides TWEPP2010_dg_final.pdf TWEPP2010_dg_final.pptx

17 A 25 GS/s sampling ASIC in a 130nm CMOS technology.

In the scope of time of flight measurements at the scale of a few pico-seconds, a CMOS fast sampler chip is being developed in a 130nm CMOS technology. It includes a 10-20GS/s timing generator comprising a Delay Locked Loop and programmable sampling windows, and four channels of 256 sampling cells able to record up to of 25 ns of analog information. An input discriminator triggers the freezing of the sampling cells which comprise a comparator allowing an on-chip 12-bit analog to digital conversion. The design and tests results of the sampler ASIC and associated test structures are presented.

Speaker: Mr Jean-Francois C. GENAT (University of Chicago)

Slides 1250_GENAT_TWEPP_2010_JFGenat.pdf 1250_GENAT_TWEPP_2010_JFGenat.pptx

Systems, planning, installation, commissioning and running experience: Parallel Session B1

Convener: Stephen Quinton (Rutherford Appleton Laboratory)

18 Data Acquisition with the Transition Radiation Detector of the AMS-02 Experiment

The Alpha Magnetic Spectrometer (AMS-02) will measure primary cosmic ray particle and gamma ray spectra on board the International Space Station. A transition radiation detector (TRD) provides the capability to identify positrons and antiprotons. Space qualified electronics, developed for the TRD, supply its 5248 proportional counter tubes with high voltage and read out all channels running on board data reduction routines. Flight hardware and electronics integrated into AMS-02 passed tests in a particle beam and a space simulator in 2010. Structure of the flight control and readout system as well as the performance of data acquisition is presented.

Speaker: Dr Andreas Sabellek (KIT - Karlsruhe Institute of Technology)

Slides Sabellek_TWEPP_Sep10_AMSTRD.pdf Sabellek_TWEPP_Sep10_AMSTRD.ppt

19 The NA62 straw detector read-out system

The NA62 straw detector, made of 7200 cylindrical straws, is a combined spectrometer and veto detector, which is part of the NA62 experiment at the CERN SPS accelerator. A new version of the full read-out system has been designed and tested on a detector prototype. A description of this system will be given, as well as test results and plan for future scaling.

Speaker: Peter Lichard (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12053

Slides twepp10_pl.pdf twepp10_pl.pptx

20 Upgrade of the ALICE-TPC read-out electronics

A large volume (90 m^3) Time Projection Chamber (TPC) is exploited at the dedicated heavy ion experiment ALICE ("A Large Ion Colliding Experiment") at CERN LHC as the main tracking detector. Equipped with 557,578 active read-out channels distributed over 4,356 Front-End Cards (FECs) and two endplates of 1.8-5 m in diameter, it is designed to track up to 20,000 particles emerging from a single, head-on PbPb collision. The huge number of active elements together with a fine sampling of the arrival time (960 samples over 96 us of drift time) results in raw event sizes of about 700 MByte, a number that gets reduced to around 70 MByte for central collisions by sophisticated on detector digital signal processing. Currently the read-out network is partitioned into 216 independent units, each connected via a 160 MByte/s optical link to the off-detector data acquisition. Extrapolating the experience gathered from \sqrt{s}=7 TeV pp collisions, this set-up would allow for reading out minimum bias PbPb collisions at about 300 Hz. The increasing capabilities of online data reconstruction and selection of interesting events, however, asks for much higher rates. Using state of the art electronics allows to reduce the size of the read-out units such that a significantly higher read-out network density can be achieved. The planned upgrade consists of 4,356 interface cards that establish a high speed serial connection between FECs and about 500 concentrator nodes. The latter provide the link to the trigger and data acquisition systems as well as to the detector control system. To connect to this "outside world" the backend is targeting the "versatile link", the radiation hard link tailored to LHC experiments, which is currently developed at CERN. The current read-out is reviewed with focus on limiting factors that are addressed by the upgrade. Studies from first prototypes, theoretical considerations and a detailed planning for the upgrade are presented and put in context with the current LHC and ALICE planning. Emphasis is also given to the decision to use the versatile link - making the TPC one of its first large-scale users.

Speaker: Mr Magnus Mager (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12026

Slides ALICE-TPC-upgrade.pdf

21 The Front-end Electronics of the LHCb Upgrade

The LHCb detector and its electronics architecture are optimized for the measurement of b-physics at LHC. The current detector is complete and taking data, and will run at a luminosity of 2 x 10^32 cm-2s-1 to collect around 6fb-1. It is expected to reach this target around 2016 and hence a programme is already underway towards an upgrade of the detector and its electronics systems at this time. The aim of this upgrade is to allow a large statistical improvement in the data as well as a search for new physics by running at an increased luminosity of 2 x 10^33 cm-2s-1. This increase is only advantageous if certain limitations imposed by the existing electronics architecture are removed. Hence a new architecture has been developed, a specific feature of which is the requirement that all detectors process and transmit data from every LHC bunch crossing. Triggering is then done in a high-performance farm of CPUs. This paper will describe the architecture and review the status of the development work underway in all the sub-detectors, with focus on those sub-systems unique to LHCb.

Speaker: Dr Jan Buytaert (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12035

Slides LHCb_uppgrade_Twepp2010.pdf LHCb_uppgrade_Twepp2010.pptx

22 Calibration systems for SiPM detector uses a novel UV-LED drivers

We will report on several versions of the calibration and monitoring system for the SiPM-based scintillator tile hadron calorimeter for the ILC. Built and tested in the beam, the 1 m3 calorimeter prototype, uses 7600 SiPMs embedded in the small scintillator tiles and represents the biggest up-to date detector equipped with these new and perspective photodetectors. SiPMs requires a highly flexible calibration system, which can deliver stable and steerable-intensity light. We present a novel qasi-resonant LED driver solution, which can deliver light from the LED in 3.5 ns pulse. We use a novel notched-fiber optical distribution on many tiles per per single fiber basis.

Speaker: Ivo Polak (Institute of Physics, Prague)

Slides Ivo_TWEPP_2010b.pdf Ivo_TWEPP_2010b.ppt

13:05 Lunch

PLENARY 2 - 3D MPW runs for HEP

Convener: Mr Ray Yarema (FNAL)

23 3D-IC MPW runs for HEP

3D-IC integration world is a rapidly growing where several scientific communities and companies are addressing important R&D resources. Among them the HEP community, through the FermiLab action who made in the few last years a significant leapfrog offering some fabrication’s runs. The number of events and publications in this field is also growing significantly. CMP is a non-profit / non-sponsored organization offering services, for IC manufacturing for prototyping and low volume production. Since 1981, the service is providing the support for design-kits distribution & support, CAD tools, wafer fabrication, and sawing / packaging. CMP jointly with MOSIS (USA) and CMC (Canada) announced the intention to offer services on the 3D-IC process from Tezzaron based on a 130nm CMOS process. Different developments achieved already and others are ongoing regarding especially the design flow supporting the users, and the choice of the 3D-IC process options. Processes and design-flows are linked, since modifying one or several features in the 3D process will involve changes in the design flow then inducing new features and developments in the design-kits and CAD tools. The selection of the 3D process has been fixed. The Design Platform (TDP) containing the (PDK) Process Design Kit and the cells libraries has been integrated in a unified environment. The collaborative work between CMP, the HEP community and the partners MOSIS and CMC, resulted in a unique and unprecedented design environment. Innovative tools and solutions inside this platform are making a much more productive environment. New features in the design methodology 3D-IC were needed for both the full-custom design-flow and the automatic semi-custom flow. They involve the layout edition, and verification (3D DRC, 3D LVS), 3D automatic place and route, dummies filling strategy, etc … 3D-IC integration needs new design paradigms making the difference with SiPs (system in package). The main difference would be the use of the 3rd dimension as a regular interconnection. That 3rd dimension represents TSVs (Through Silicon Via) or DBIs (Direct Bond Interface). They have to be used not only as connections through the IOs in the periphery of the tiers’ chips or blocks, but connecting in a way that a blocks or chips are distributed across the tiers. CAD tools enabling optimized partitioning don’t exist yet in the industry. The more the partitioning involves small blocks and small leaf-cells, the more the floor-planning will be efficiently optimized. The resulting system will not be easy to test as it will not be a simple stack of “Known Good Dies” as this is done for SiPs systems. Real 3D-IC integration will then not be considered as a simple stack of dies like for SiPs. This is like for buildings. They cannot be made by simply stacking individual houses.

Speaker: Kholdoun TORKI (CMP)

Slides TWEPP_2010_K_TORKI.pdf

ASICs: Parallel Session A2

Convener: Ken Wyllie (CERN)

24 A Silicon Pixel Readout ASIC with 100 ps time resolution for the NA62 Experiment

The silicon tracker of the NA62 experiment requires the measurement of the particles arrival time with a resolution better than 200 ps rms and a spatial resolution of 300 um. A time measurement technique based on a Time to Amplitude Converter has been implemented in an ASIC in order to prove the possibility of integrate a TDC with resolution better than 200 ps in a pixel cell. Time walk problem has been addressed via the Constant Fraction Discriminator technique. The ASIC has been designed in a CMOS 130 nm technology with single event upset protection of the digital logic.

Speaker: Mr Giovanni Mazza (INFN sez. di Torino)

Paper http://iopscience.iop.org/1748-0221/6/01/C01087/

Slides GMazza_TWEPP2010_ID41.pdf

25 GOSSIPO-3: Measurements on the Prototype of a Read-Out Pixel Chip for Micro-Pattern Gas Detectors

GOSSIPO-3 is the demonstrator of a front-end chip for the read-out of Micro Pattern Gas Detectors designed in IBM 130 nm CMOS in collaboration of Nikhef and the Physics Department Bonn. The prototype features charge sensitive amplifiers, discriminators, a high resolution Time to Digital Converter, Low Drop Out voltage regulators for supply voltage control of the TDC, biasing circuits and control logic on a 2x1 mm² die. It can be operated in a time measuring or an event counting mode. Following the prototype announcement at the TWEPP 2009, measurement data on noise performance, channel to channel gain, ToT spread and LDO load step response are now available.

Speaker: Dr Andre Konrad Kruth (Physics Department, University of Bonn)

Paper http://iopscience.iop.org/1748-0221/5/12/C12005/

Slides G3_Twepp2010_upload.pptx

26 A 3D vertically integrated deep n-well CMOS MAPS for the SuperB Layer0

This work is concerned with the design of analog circuits for processing the signals from deep n-well (DNW) monolithic CMOS sensors. The DNW MAPS approach takes advantage of the properties of triple well structures to lay out a sensor with relatively large area (as compared to standard MAPS) read out by a classical processing chain for capacitive detectors. Recently, a very promising approach based on the use of a vertically integrated CMOS technology (3D) has also been considered. Vertical integration processes may be very effective in providing increased functional density and charge collection efficiency. The purpose of the final paper is to describe the features of the front-end electronics with the first experimental results from the test of 3D DNW MAPS.

Speaker: Dr Gianluca Traversi (University of Bergamo and INFN Pavia)

Paper http://iopscience.iop.org/1748-0221/6/01/C01010/

Slides traversi.pdf

Power, Grounding and Shielding: Parallel Session B2

Convener: Philippe Farthouat (CERN)

27 Low power High Voltage supply circuit for Photo Multiplier tubes in the Km3Net experiment

The described system is developed in the framework of a deep-sea submerged Very Large Volume neutrino Telescope where photons are detected by a large number of Photo Multiplier Tubes [2]. These PMTs are placed in optical modules (OM). A basic Cockcroft-Walton (CW) voltage multiplier circuit design is used to generate multiple voltages to drive the dynodes of the photomultiplier tube. To achieve a long lifetime and a high reliability the dissipation in the OM must be kept to the minimum. The design is also constrained by size restrictions, load current, voltage range, and the maximum allowable ripple in the output voltage. A surface mount PMT-base PCB prototype is designed and successfully tested. The system draws less than 1.5 mA of supply current at a voltage of 3.3 V with a HV output up to -1200 Vdc, a factor 10 less than the commercially available state of the art.

Speaker: Mr Paul Timmer (Nikhef)

Paper http://iopscience.iop.org/1748-0221/5/12/C12049

Slides Presentation_TWEPP.pdf Presentation_TWEPP.ppt

28 Development of custom radiation-tolerant DCDC converter ASICs

The development of a custom radiation-tolerant DCDC converter ASIC is under way, aiming at an input voltage of 10V and an output power up to 8W. CMOS technologies for the development have been tested for radiation, and two of them satisfied the specifications even for upgraded trackers to SLHC levels. The design of 2 ASIC prototypes is presented, with measurements indicating that both the efficiency and radiation tolerance requirements are met. A third and more complete design has been submitted for fabrication in January and its full characterization, including radiation effects, will also be presented.

Speaker: Dr Federico Faccio (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11016

Slides Faccio_ASIC_forIndico.pdf

29 Progress and Advances in Serial Powering of Silicon Modules for the ATLAS Tracker Upgrade

Future detector systems will face technical difficulties with the supply of electrical power to a multitude of sub-detectors. The Serial Powering (SP) scheme is an elegant solution which leads to a great reduction in cable mass, whilst increasing efficiency and reducing cost. In recent years, substantial developments in SP have been made by the ATLAS Tracker Upgrade Community. Initial demonstrator modules and supermodules (known as staves) used the ABCD chip and shunt regulators made from discrete components. Continuous development of the SP architecture has led to shunt regulation within the latest ABCN-25 ASICs themselves. From a system point of view, studies of protection schemes and current sources have advanced greatly. We report recent progress, including first results from a serially powered stavelet using the ABCN-25 chip.

Speaker: Dr John Matheson (Rutherford Appleton Laboratory)

Paper http://iopscience.iop.org/1748-0221/6/01/C01019

Slides jm_twepp_2010_11.pdf jm_twepp_2010_11.ppt

16:20 Break

ASICs: Parallel Session A2

Convener: Ken Wyllie (CERN)

30 Characterisation Of The NA62 GigaTracker End Of Column Readout ASIC

The architecture and characterisation of the End Of Column readout chip for the NA62 GigaTracker hybrid pixel detector will be presented.This chip must perform time stamping to 100 ps (RMS) or better, provide 300 µm pitch position information and operate with a dead time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. Current results indicate the pixel operates with a jitter of 40.2 ± 0.3 ps (RMS) for a 2.5fC input charge. The time to digital converter operates with a 97 ps time bin and exhibits a differential non-linearity of 0.17 ± 0.03 LSBs and an integral non-linearity of 0.27 ± 0.05 LSBs.

Speaker: Dr Matthew Noy (CERN)

Paper http://iopscience.iop.org/1748-0221/6/01/C01086/

Slides mnoy.twepp.21.09.2010.pdf

31 The FE-I4 Pixel Readout System-on-Chip for ATLAS Experiment Upgrades

This article elaborates on a novel pixel readout system-on-chip (SoC) that has been designed to meet the ever increasing demands of the present and future generation of LHC pixel detectors. The FE-I4 architecture has higher luminosity and rate capability as well as a smaller single pixel area compared to its predecessors and is currently the most complex chip designed for particle physics applications. The IC has been designed in 130nm CMOS technology. The state of the art of the FE-I4 will be presented, including the architecture overview, simulation results, preliminary measurements and a global design flow.

Speaker: Tomasz Hemperek (Physikalisches Institut - Universität Bonn)

Slides FE-I4.pdf FE-I4.pptx

32 ULTIMATE: a High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade

A pixel detector, composed of two layers of high resolution Monolithic Active Pixel Sensors (MAPS), is being designed for the STAR Heavy Flavor Tracker (HFT) upgrade. It allows topological identification of D mesons in heavy ion collisions at RHIC. The sensor chip: named ULTIMATE, is optimized for the ultimate phase of the upgrade in terms of resolution, power consumption and radiation tolerance. It features a matrix of 928x960 pixels, covering an active area of ~382 mm2. Its architecture is based on that of MIMOSA26 allowing a fast readout frequency of ~5 k frames/s. This paper presents the sensor design.

Speaker: Dr Christine HU-GUO (DRS-IPHC (IReS), University of Strasbourg, CNRS-IN2P3)

Slides TWEPP2010_IPHC.pdf TWEPP2010_IPHC.ppt

Power, Grounding and Shielding: Parallel Session B2

Convener: Philippe Farthouat (CERN)

33 DC-DC Buck Converters for the CMS Upgrade at SLHC

The CMS experiment foresees the deployment of DC-DC buck converters in its pixel and strip tracker upgrades, to facilitate the supply of the required currents with the installed cable plant and with a minimal amount of material. We have developed DC-DC buck converters based on radiation-tolerant ASICs from the CERN electronics group. Their performance in terms of power efficiency and conductive and radiative noise emissions will be introduced, and system tests with silicon strip modules as well as pixel modules, using the original pixel power supply chain, will be presented. The implementation in the foreseen applications will be discussed.

Speaker: Dr Katja Klein (I. Physikalisches Institut (B), RWTH Aachen University)

Paper http://iopscience.iop.org/1748-0221/6/01/C01020

Slides KatjaKlein_TWEPP10_21092010.pptx

34 A serial powering scheme for the ATLAS pixel detector at SLHC

Powering of future trackers at SLHC requires low current distribution for high power efficiency and low material budget. In this framework, we investigate a serial powering scheme for the ATLAS pixel detector at SLHC. A dedicated regulator has been prototyped and largely characterized, both as single device and in a serial powering configuration. System aspects, such as AC-coupled module readout, are investigated with a pixel stave emulator, and the effort is now converging to the development of a serially powered outer layer stave prototype. Results and status of each activity will be presented.

Speaker: Laura Gonella (Universität Bonn)

Paper http://iopscience.iop.org/1748-0221/5/12/C12002

Slides Gonella_TWEPP10.pdf Gonella_TWEPP10.pptx

35 Low Noise DC to DC Converters for the sLHC Experiments

The development of front-end systems for the ATLAS tracker at the sLHC is now in progress and the availability of radiation tolerant buck converter ASICs enables the implementation of DC to DC converter based powering schemes. The front-end systems powered in this manner will be exposed to the radiated and conducted noise emitted by the converters. The electromagnetic compatibility between DC to DC converters and ATLAS short strip tracker hybrid prototypes has been studied with specific susceptibility tests. Different DC to DC converter prototypes have been designed following a noise optimization methodology to match the noise requirements of these front-end systems. The DC to DC converter developed in this manner presents a negligible emission of noise that was confirmed by system tests on an ATLAS tracker front-end module prototype. As a result of this, power converters can now be integrated in close vicinity of front-end chips without compromising their overall noise performance.

Speaker: Georges Blanchot (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11011

Slides Low_Noise_Dc_to_DC_Converters_for_the_sLHC_experiments.pptx

POWER WG

Convener: Philippe Farthouat (CERN)

36 Serial power protection

Speaker: David Lynn (Brookhaven National Laboratory)

Slides SPP_Aachen.pdf

37 Study and methodology for decreasing noise emissions of DC-DC converters through PCB layout

Speaker: Cristian Fuentes (CERN, UTFSM)

Slides Twepp2010_Presentation.pdf

38 EMC CMS tracker upgrade project status

Speaker: Fernando Arteche (Instituto Tecnológico de Aragón)

Slides EMCstatusSep2010V1.pdf EMCstatusSep2010V1.pptx

39 Follow-up of previous meeting

Wednesday, 22 September

PLENARY 3 - Optical Technologies for Data Communication in Large Parallel Systems

Convener: Francois Vasey (CERN)

40 Optical Technologies for Data Communication in Large Parallel Systems

Large, parallel systems have been employed by scientists for both computation and data collection, but performance scaling now relies on chip and system-level parallelism. This has happened because power density limits have caused processor frequency growth to stagnate, driving the new multi-core architecture paradigm, which would seem to provide generations of performance increases as transistors scale. However, this paradigm will be constrained by electrical I/O bandwidth limits; first off the processor card, then off the processor module itself. We will present best-estimates of these limits, then show how optical technologies can help provide more bandwidth to allow continued system scaling. We will describe the current status of optical transceiver technology which is already being used to exceed off-board electrical bandwidth limits, then present work on silicon nanophotonic transceivers and 3D integration technologies which, taken together, promise to allow further increases in off-module and off-card bandwidth. Finally, we will show estimated limits of nanophotonic links and discuss breakthroughs that are needed for further progress, and will speculate on whether we will reach Exascale-class machine performance at affordable powers.

Speaker: Mr Mark Ritter (IBM US)

Paper http://iopscience.iop.org/1748-0221/6/01/C01012

Slides 0900_RITTER_Ritter_TWEPP_Sept2010_vf.pdf 0900_RITTER_Ritter_TWEPP_Sept2010_vf.ppt

ASICs: Parallel Session A3

Convener: Luciano Musa (CERN)

41 Radiation-hard ASICS for optical data transmission in the first phase of the LHC upgrade

The LHC at CERN will be upgraded in two phases to increase the design luminosity by a factor of ten. The ATLAS experiment plans to add a new pixel layer to the current pixel detector during the first phase of the upgrade. The optical data transmission will also be upgraded to handle the high data transmission speed. A new driver and receiver ASIC has been designed for this new generation of optical links to incorporate the experience gained from the current system, including redundancy circuitry to bypass a bad channel in a VCSEL or PIN array.

Speaker: Prof. K.K. Gan (The Ohio State University)

Paper http://iopscience.iop.org/1748-0221/5/12/C12006/

Slides TWEPP2010_Gan.pdf

42 Signal processing for High Granularity Calorimeter: amplification, filtering, memorization and digitalization

A very-front-end chip dedicated to high granularity calorimeters has been designed and its performance measured. This electronics is composed of a low-noise Charge Sensitive Amplifier followed by a bandpass filter based on a gated integrator. This shaper performs intrinsically the analog memorization of the signal before its delayed digital conversion. The analog-to-digital conversion is obtained through a low-power 12-bit cyclic ADC. Measurements show a global non-linearity better than 0.1%. The ENC is evaluated to 1.8 fC, compare to the maximum input charge of 10 pC. The power consumption of a complete channel is limited to 6.5mW.

Speaker: Laurent Royer (Lab. de Physique Corpusculaire (LPC)-IN2P3-Pole Michrau)

Paper http://iopscience.iop.org/1748-0221/5/12/C12014/

Slides TWEPP_1009_LR.pdf TWEPP_1009_LR.ppt

Systems, planning, installation, commissioning and running experience: Parallel Session B3

Convener: Ken Wyllie (CERN)

43 Application of new PICMG MicroTCA for physics specifications to accelerator control

The PICMG xTCA for Physics Specifications Extensions nearing completion are being tested in linac controls applications at DESY (EU XFEL) and at SLAC (ILC R&D, LCLS). New standard crate and module prototypes have been developed through industry partners while a flexible controls architecture is emerging based on a few powerful generic AMC modules backed by application-specific µRTMs. The lab-industry collaboration is proving highly successful in leveraging the strengths of the community for rapid development and deployment of crates and modules for the next-generation standard. Specific applications in progress at DESY and SLAC as well as work of the standards collaboration will be described. PICMG – PCI Industrial Computer Manufacturers Group AMC – Advanced Mezzanine card µRTM – Micro Rear Transition Module

Speaker: Mr Raymond S. Larsen (SLAC)

Slides SLAC-DESY_TWEPP_2010_092110_R7.pptx

44 Development of a MicroTCA Carrier Hub for CMS at SLHC

We are developing a MicroTCA Carrier Hub card which will provide timing, control and data acquisition functions in a MicroTCA crate for SLHC readout electronics. This module may be mounted in the primary or redundant MCH slot in a MicroTCA crate, and distributes low-jitter LHC RF clock and encoded fast timing signals to up to 12 AMC modules. In addition, it receives buffer status signals and DAQ data at up to 600 MBytes/sec from each AMC. The module is built on a commercial MCH base board with a custom mezzanine board stack. The latest Xilinx Virtex-6 FPGA are used to provide a clear upgrade path. Prototype modules are being developed initially for a CMS HCAL test beam in summer 2010. We will report on the specifications of the module, its application in a MicroTCA system beyond CMS HCAL, and our experience in commissioning the module for the test beam.

Speaker: Eric Shearer Hazen (Department of Physics-Boston University-USA)

Paper http://iopscience.iop.org/1748-0221/5/12/C12042

Slides Hazen_uTCA4.pdf

10:40 Break

ASICs: Parallel Session A3

Convener: Luciano Musa (CERN)

45 A 256 channel 8 bit current digitizer ASIC for the Belle-II PXD

The international DEPFET collaboration is developing a low mass vertex detector (PXD)for the future BELLE-II experiment at the SuperKEKB particle accelerator in Japan. The PXD is based on monolithic arrays of DEPFETs which are read out in a rolling shutter mode. The Drain Current Digitizer ASIC (DCD-B) is used for reading out this detector matrix. It provides 256 channels of Analog-Digital converters with a resolution of 7-8 bits each, running at a conversion speed of 12.5 MHz.The chip design and first measurement results will be presented.

Speaker: Mr Jochen Knopf (Heidelberg University)

Paper http://iopscience.iop.org/1748-0221/6/01/C01086/

Slides DCDB-TWEPP10.pdf

46 The GBT-Serdes ASIC prototype: test features and preliminary results

In the framework of the GigaBit Transceiver project (GBT), a prototype of the GBT-SERDES ASIC has been developed. In charge of the serialization-deserialization of the data, including Reed-Solomon encoding, clock recovery, precise PLLs and complex frame-alignment procedure, this chip has been designed in a commercial 130nm CMOS technology to sustain high radiation doses and operate at 4.8 Gb/s. The first wafer of these chips arrived at the end of May 2010. In this paper, we present the GBT prototype chip, his testing features, the system designed to fully qualify the component and the preliminary results obtained.

Speaker: Mr PAULO MOREIRA (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11022/

Slides slidesMoreiraId100.pdf slidesMoreiraId100.pptx

47 The Design for Test Architecture in Digital Section of the ATLAS FE-I4 Chip

This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used during the experiment, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.

Speaker: Dr Vladimir Zivkovic (NIKHEF Institute)

Paper http://iopscience.iop.org/1748-0221/6/01/C01090/

Slides TWEPP2010-zivkovic.pdf TWEPP2010-zivkovic.pptx

48 A 16:1 Serializer ASIC for Data Transmission at 5 Gbps

A high speed, low power 16:1 serializer is developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. It operates from 4.0 to 5.8 Gbps in the lab test. Its total jitter is measured to be 62 ps and the bathtub scan demonstrates a 122 ps opening at BER of less than 10-12 level at 5 Gbps. The measured power consumption is 507 mW at this data rate. A proton test of this chip is scheduled in June and test results will be discussed when available.

Speaker: Datao Gong (Southern Methodist Univeristy)

Paper http://iopscience.iop.org/1748-0221/5/12/C12009/

Slides LOCs1slides10.pdf LOCs1slides10.pptx

49 Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

We present designs and hopefully the first test results of two DC-DC switched capacitor converters developed in 0.13μm technology. Both circuits will be used as the building blocks in the power distribution system proposed for the upgraded ATLAS Inner Detector.

Speaker: Mr Michal Bochenek (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12031

Slides twepp10_bochenek.pdf twepp10_bochenek.pptx

Systems, planning, installation, commissioning and running experience: : Parallel Session B3

Convener: Ken Wyllie (CERN)

50 Status Report on a MicroTCA Card for HCAL Trigger and Readout at SLHC

We will discuss our recent experiences designing and testing a prototype MicroTCA card for HCAL Trigger and Readout at SLHC. Our second generation prototype uses a Xilinx XC5VFX70T FPGA to perform the high-speed communication and data processing for up to 8 Readout Module fibers that are streaming data at 4.8 Gbps each. The FPGA also uses two SFP+ optical interfaces at 6.4 Gbps each for data transfer to the Trigger System. A local DAQ interface in the FPGA communicates via Gigabit Ethernet with the MicroTCA MCH. We will discuss results from our Bit Error Rate Tests under a variety of challenging clocking environments including a legacy TTC system and our own 40 MHz "spread spectrum" clock generation boards. Results from the 2010 LHC Test Beam demonstrations will include issues arising from integration with legacy hardware and the level of success achieved in meeting performance expectations for future SLHC architectures.

Speaker: Mr Erich Frahm (University of Minnesota/CMS)

Paper http://iopscience.iop.org/1748-0221/5/12/C12027

Slides TWEPP_2010.pdf

51 A demonstrator for a level-1 trigger system based on μTCA technology and 5Gb/s optical links.

A demonstrator for a level-1 trigger system has been designed and manufactured. The prototype card uses the AMC double width form factor, 5Gb/s links and a Xilinx XC5VTX150T or XC5VTX240T FPGA. Testing of the prototype is in an advanced stage. Results on the performance will be presented.

Speaker: Dr Gregory Michiel Iles (Imperial College, London)

Paper http://iopscience.iop.org/1748-0221/5/11/C11015

Slides 2010_09_20_TWEPP_v4.pdf 2010_09_20_TWEPP_v4.ppt

52 Study for the LHCb readout board

The LHCb experiment envisages to upgrade its readout speed from 1 MHz to 40 MHz. The consequence for the electronics is higher densities and an increase of serial links speed. Moreover the architecture must be reviewed to cope with links carrying data, clock and slow control at the same time. Relying on boards compliant with the xTCA standard, we demonstrate how it is possible to build a flexible, scalable system consistent with the requirements. Measurements related to signal integrity, clock distribution and performance of the supervision system are also presented.

Speaker: Jean-Pierre Cachemiche (Centre de Physique des Particules de Marseille)

Paper http://iopscience.iop.org/1748-0221/5/12/C12036

Slides Study_for_the_LHCb_readout_board.pdf

53 Data Acquisition System for Belle II

At the Belle II upgrade of the Belle experiment at KEKB, we expect about20 kHz level-1 trigger rate at the design luminosity of 8 times 10^34/cm^2/s. The Belle II data acquisition system is designed to read out the data from the entire detector at up to 30 kHz, with minimum amount of deadtime of several percent that is unavoidable due to hardware constraints. The system consists of subsystems for timing distribution, data links, event building and high level triggering. We present the system which is designed to be ready in 2013 for the start of Belle II.

Speaker: Mikihiko Nakao (KEK)

Paper http://iopscience.iop.org/1748-0221/5/12/C12004

Slides nakao-twepp.pdf

54 A Reconfigurable Cluster Element (RCE) DAQ Test Stand for the ATLAS Pixel Detector Upgrade

The RCE DAQ system is based on System-On-Chip building Blocks (RCEs) residing in Virtex-4/5 FPGAs and hosted within an ATCA based ecosystem with generic high bandwidth capabilities and 10-GE support. User applications in C++ run on the PowerPC core of the RCEs under the real-time operating system RTEMS. We will present a new application of these flexible DAQ building blocks targeted for the ATLAS pixel detector upgrade with full implementation of calibrations and multi-channel read-out. This application is used in both test-beam and cosmic telescope experiments, and in exploring the viability of this concept for an upgraded readout system.

Speaker: Matthias Wittgen (Stanford Linear Accelerator Center (SLAC))

Slides TWEPP2010_wittgen.pdf

13:05 Lunch

PLENARY 4 - New interconnect technologies

Convener: Jorgen Christiansen (CERN)

55 New interconnect technologies

Although CMOS technology has a proven track record in terms of performance, there are limitations of a single chip (and even more of a full system containing many chips) in terms of the traditionally lateral interconnects. The past years a lot of R&D was spent to develop 3D interconnect and integration technologies such as high density bump interconnects, through Si vias and advanced assembly. Implementation of these technologies in 3D stacked systems are expected to enable more preformant electronic systems. In this talk, an overview of the technology building blocks and their maturity status will be given, as well as a number of examples in imaging applications developed at imec.

Speaker: Piet de Moor (IMEC)

Slides TWEPPPdMimec.pdf

Optoelectronics and Links: Parallel Session B4

Convener: Francois Vasey (CERN)

56 An Optical Link for ATLAS Liquid Argon Calorimeter Front-end Electronics Readout

This paper presents the design, production quality assurance, integration, installation and commissioning of the optical link system for the ATLAS Liquid Argon Calorimeter front-end electronics readout. Operation experience and the recent problems with the optical transmitters are discussed. Also presented are the up-to-date results in searching for failure modes, experiences gained in that process, and a possible drop-in backup solution with redundancy for the optical transmitter.

Speaker: Tiankuan Liu (Department of Physics-Southern Methodist University (SMU))

Slides Liu_TWEPP10_OpticalLink_Presented.pdf Liu_TWEPP10_OpticalLink_Presented.pptx

57 Versatile Transceiver Developments

SLHC experiment upgrades will make substantial use of optical links to enable high-speed data readout and control. The Versatile Link project will develop and assess optical link architectures and components suitable for deployment at SLHC. The on-detector element will be bidirectional opto-electronic module: the Versatile Transceiver (VTRx) that will be based on a commercially available module type minimally customized to meet the constraints of the SLHC on-detector environment in terms of mass, volume, power consumption, operational temperature and radiation environment. This paper will bring together the status of development of the VTRx in terms of packaging, environmental testing and functional testing.

Speaker: Csaba Soos (CERN)

Paper http://iopscience.iop.org/1748-0221/6/01/C01089/

Slides VTRx_TWEPP10_final.pdf VTRx_TWEPP10_final.ppt

58 Link Model Simulation and Power Penalty Specification of Versatile Link Systems

This paper presents simulation and experimental studies of optical power penalties on the Versatile Link, the common R&D project on high-speed optical link for SLHC. It also presents how the 10 GbE fiber link model is incorporated into the Versatile Link system level specification. Receiver sensitivity tests on multi-mode and single-mode fibers over different fiber lengths are demonstrated. The 10 GbE link models are examined and parameter sensitivity analyses are conducted. Transmitter characteristics affect link power penalty most. Optical power budget for a maximum reliable link is then predicted from the simulations for characteristic parameters of the Versatile Link.

Speaker: Dr Annie Xiang (Southern Methodist University)

Paper http://iopscience.iop.org/1748-0221/6/01/C01088

Slides twepp2010_linkmodel_final.pdf twepp2010_linkmodel_final.ppt

Packaging and Interconnects: Parallel Session A4

Convener: Mr Ray Yarema (FNAL)

59 Low-cost bump bonding activities at CERN

Conventional bumping processes use electroplating for under bump metallization (UBM) and solder deposition. This process is laborious, involves time consuming photolithography, can only be performed using whole wafers and is therefore expensive in low volumes. In the low-cost development work, electroless deposition of UBM and novel solder ball placement techniques are studied as substitutes to the electroplating process in certain bump size and pitch window. Preliminary results on test and CMOS chips have shown that electroless deposited UBM’s have prospects to be used as a cost-efficient technology in future detector constructions.

Speaker: Mr Sami Vaehaenen (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11008

Slides S_Vaehaenen-Low-cost_bump_bonding_activities_at_CERN-TWEPP-10.pptx

60 Design and Performance of Serial Powered Single-Sided Modules within an Integrated Stave Assembly for the ATLAS Tracker Barrel Upgrade

The design and performance of prototype single-sided modules with ABCN-25 front-end chips and 10x10 cm2 Hamamatsu silicon strip sensors is presented. A low mass module assembly has been achieved by gluing a single-sided flex circuit, with read out chips, directly onto the sensor. The design exploits the embedded shunt regulation within the ABCN-25 providing for a distributed and scalable powered architecture. This allows for multiple modules to be linked together serially to form larger stave structures of up to 12 modules. The stave’s digital I/O is realised as a multi-drop LVDS bus flex cable glued to the stave core assembly using a custom ASIC receiver/transmitter (BCC). The results of preliminary electrical tests with 4 module stavelets will be presented.

Speaker: Mr Ashley Greenall (The University of Liverpool)

Paper http://iopscience.iop.org/1748-0221/5/12/C12013/

Slides Twepp10.pdf Twepp10.pptx

61 SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC

The on-going production of a demonstrator module for the ATLAS pixel detector upgrade is presented, exploiting thin planar pixel sensors as well as vertical integration technologies developed at the Fraunhofer Institute –IZM in Munich. The Solid-Liquid-InterDiffusion (SLID) technique is employed as an alternative to the bump-bonding process, to connect thin pixel sensors to the ATLAS FE-I3 electronics. Inter-Chip-Vias (ICV) are being investigated on a FE-I3 wafer to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design.

Speaker: Michael Beimforde (Max-Planck-Institut fuer Physik)

Paper http://iopscience.iop.org/1748-0221/5/12/C12025/

Slides BeimfordeTWEPP2010.pdf

16:20 Break

MUG

Convener: Kostas Kloukinas (CERN)

62 ASIC design tools and foundry services at CERN

Speaker: Kostas Kloukinas (CERN)

Slides MUG_TWEPP2010_Kloukinas.pdf MUG_TWEPP2010_Kloukinas.ppt

63 Update on the Design Implementation Methodology for the 130nm process

Speaker: Dr Sandro Bonacini (CERN)

Slides MUG-design-flow.pptx

64 Discussion

Opto WG: Experience with running systems

Convener: Prof. K.K. Gan (The Ohio State University)

65 VCSEL failures in ATLAS

Speaker: Tobias Flick (Bergische Universitaet Wuppertal)

Slides Flick_VcselFailures.pdf Flick_VcselFailures.pptx

66 VCSEL failures in other experiments

Speaker: Ken Wyllie (CERN)

Slides VCSEL_LHCb_TWEPP2010.pdf VCSEL_LHCb_TWEPP2010.pptx

67 Summary document on systems status

Speaker: Francois Vasey (CERN)

68 OWG discussion

xTCA WG

Convener: Magnus Hansen (CERN)

69 xTCA Working Group

This is the first session of the eventual xTCA working group and everybody are invited to participate

Speakers: Dr Gregory Michiel Iles (Imperial College), Jean-Pierre Cachemiche (Faculte des Sciences de Luminy), Magnus Hansen (CERN), Mr Raymond S. Larsen (SLAC)

Slides

• greg_V0.pdf
• Jean-Pierre.pdf
• Magnus.pdf
• Magnus.pptx
• RayL_xTCA__Workshop_Discussion_Topics_TWEPP_10.pdf
• RayL_xTCA__Workshop_Discussion_Topics_TWEPP_10.pptx

Opto WG: Short status of ongoing projects for upgrades

Convener: Prof. K.K. Gan (The Ohio State University)

70 Versatile link

Speaker: Francois Vasey (CERN)

Slides VL_OptoWG.pdf VL_OptoWG.ppt

71 Array lasers and laser drivers

Speaker: Prof. K.K. Gan (The Ohio State University)

Slides Array_Gan.pdf

72 LOC

Speaker: Jingbo Ye (Southern Methodist University, Department of Physics)

Slides The_LOC_Project.pdf The_LOC_Project.pptx

73 OWG discussion

SEU WG

At the conclusion of TWEPP presentations Wednesday afternoon, there will be a short Micro Electronics User Group (MUG) meeting followed by an ASIC designers working group meeting to discuss Single Event Effects (SEE) in the next generation experiments with high radiation levels. Dealing with single event effects covering Single Event Upset (SEU), Single Event Transients (SET), Single Event Latchup (SEL) and Single Event Functional Interrupts (SEFI) will be an increasingly difficult challenge when using modern ASIC technologies with low power supply voltages. Deep submicron IC technologies with low power consumption are getting increasingly sensitive to single event effects and this must therefore be taken carefully into account both at the system level and the ASIC design level. This working group meeting will be an initial forum within the high energy physics community to share acquired knowledge and experience in this particular domain. Our current knowledge and experience with SEE’s will be introduced and summarized by a few presentations followed by an open discussion among the working group participants.

Convener: Mitch Newcomer (University of Pennsylvania)

74 SEE effects in deep submicron technologies

Speakers: Federico Faccio (CERN), Dr Sandro Bonacini (CERN)

Slides

• Bonacini-SEU_130nm.pdf
• Faccio-SEEdeepsub.pdf
• Faccio-SEEdeepsub.pptx
• Intro_SEU_Mitch.pdf
• Intro_SEU_Mitch.pptx
• TWEPP2010_V2_Menouni.pdf
• TWEPP2010_V2_Menouni.ppt

Opto WG: Plans in 2010 and 2011

Convener: Prof. K.K. Gan (The Ohio State University)

75 Irridiation plans in 2010 et 2011

Speaker: Prof. K.K. Gan (The Ohio State University)

Slides Irradiation_Gan.pdf

76 Working groups plans for 2011

19:30 Scientific Committee Meeting and Dinner

Thursday, 23 September

PLENARY 5 - Preparation for Heavy Ions in ALICE and other LHC experiments

Preparation for Heavy Ions in ALICE and other LHC experiments

Convener: Emilio Petrolo (INFN, Sezione di Roma Tor Vergata-Universita degli Studi di Roma)

77 Preparation for Heavy Ions in ALICE and other LHC experiments

The Large Hadron Collider (LHC) will collide lead nuclei in November 2010. Three experiments will collect data during the heavy-ion run: ALICE, which is the dedicated heavy-ion experiment, ATLAS, and CMS. After the successful commissioning and proton-proton data taking phases, these experiments will face the new challenge posed by the extreme conditions of Pb-Pb collisions, with envisaged particle production multiplicities of few thousand units. In this presentation, I will briefly introduce the physics motivations for the LHC heavy-ion program, and then discuss the experimental conditions and the preparation of the experiments for the upcoming run with lead beams. In particular, I will describe the aspects of the ALICE design that are specifically tailored to cope with the high-multiplicity environment, and I will discuss a few examples on how the ATLAS and CMS experiments, not specifically designed for this, are expected to perform and how they will adapt to the heavy-ion environment.

Speaker: Andrea Dainese (INFN Padova)

Slides DaineseTWEPP.pdf

Programmable Logic, design tools and methods: Parallel Session B5a

Convener: Magnus Hansen (CERN)

78 Digitization and real-time analysis of detector signals with GANDALF

The Recoil-Proton Detector at COMPASS is built to identify protons of DVCS-processes and to trigger on the recoil particle. A front-end module was designed that allows both precise digitization of photomultiplier signals and real-time data-processing. With GANDALF, signals of 16 channels are converted by 12-bit 500 MHz ADCs, zero-time approximation is accomplished by DSP-algorithms in a Virtex-5 FPGA. Measurements yield resolutions below 50 ps for amplitudes up to 3.8% of the full dynamic range. In addition, GANDALF can be used as 128 channel TDC-system with a resolution of 150 ps.

Speaker: Louis Lauser (Physikalisches Institut, Albert-Ludwigs-Universität Freiburg)

Slides lauser_230910.pdf

79 The IBL Readout System

With higher instantaneous luminosity, the present Pixel detector system will run into readout inefficiencies. To compensate for those and yet provide good impact parameter resolution with an upgraded LHC, a Layer designed for reading out higher occupancies is to be inserted into Pixel during the Phase1 Upgrade of ATLAS. This additional layer, called IBL (Insertable B-Layer), will include newly designed on-detector electronics to cover the higher radiation and occupancy. It needs to be read out using a renewed readout system, which is under development. Since the distance to the interaction point is reduced the occupancy of the FE chips is higher and the readout bandwidth needs to be adapted to that. A change in the pixel size is reducing this effect so that an increase in readout bandwidth by a factor 2 is sufficient. The adaption of the readout bandwidth must be done on off-detector side within the Back of Crate card (BOC). Therefore, the Back of Crate card needs a redesign of the data receiving part. It will be the off-detector end of the optical link, which transmits data in both directions. From the BOC card the command and control data is sent to the optoboard (the opto-electrical interface inside the detector volume) and from there electrically to the modules. Vice versa, the modules data is sent electrically to the optoboard and from there optically to the BOC card. While the transmission to the detector will be operated at 40 Mb/s, the readout from the detector will be done at 160 Mb/s bandwidth. This higher readout speed has several implications, which need to be fulfilled like getting the correct clocks to the different parts of the detector. Also a balanced signal transmission will be set up for that data link to reduce calibration effort and stabilize the system. It will enable an automated phase adjustment of the detector data to the readout system clocks. Using VME as the form factor helps staying as compatible as reasonably possible to the former Pixel system and eventually allows for upgrading the Pixel Layer 2 readout system to run at 80 MBit/s with few exchange effort.

Speaker: Mr Jens Dopke (University of Wuppertal)

Paper http://iopscience.iop.org/1748-0221/6/01/C01006

Slides 20100923.pdf

Trigger: Parallel Session A5

Convener: Emilio Petrolo (INFN, Sezione di Roma Tor Vergata-Universita degli Studi di Roma)

80 Icarus T-600 Trigger System

The ICARUS-T600 detector at LNGS is the first large mass Liquid Argon TPC (LAr-TPC) going into operation in an underground laboratory. In the development of the electronics, a particular effort has been addressed to study and implement an on-line hit finding algorithm, for the definition of regions of interest (ROI). This feature has shown to be sensitive to small charge depositions (~1 MeV) while keeping a good granularity, necessary for the reduction of the total throughput (~10^11 volumetric pixel per second). The integration of the ROI signals into the trigger management leads to flexible and efficient solutions, perfectly suited for the variety of physical events studied by the present detector, but also by future LAr-TPC.

Speaker: Daniele Dequal (Università degli studi di Padova)

Slides Dequal_Aachen.pdf Dequal_Aachen.ppt

81 Digital Trigger for the COMPASS experiment

The COMPASS digital trigger system is an FPGA based real time trigger logic which detects event signature by analyzing already digitized detector information. The trigger system has distributed multi stage architecture. The first stage is implemented in front-end electronics and it runs in parallel to data acquisition. The COMPASS event selection criteria are based on event geometry, extracted from hits in scintillating counter detectors, and a calorimetric trigger. A signal time of scintillating counters is measured with a specially developed for this project FPGA TDC. The calorimeter trigger logic evaluates a total energy detected in a calorimeter by extracting signal time and signal amplitude from digital waveform of detector signal. The architecture and performance of the digital trigger system are discussed.

Speaker: Mr Igor Konorov (Technische Universitat Munchen)

Slides twepp_2010_IgorKonorov.pdf twepp_2010_IgorKonorov.pptx

10:40 Break

Programmable Logic, design tools and methods: Parallel Session B5a

Convener: Magnus Hansen (CERN)

82 A readout driver for the ATLAS LAr calorimeter at super-LHC

A new readout driver (ROD) is being developed as a central part of the signal processing of the ATLAS liquid-argon calorimeters for operation at the sLHC. In the architecture of the upgraded readout system, the ROD modules will have several challenging tasks: receiving of up to 1.4 Tb/s of data per board from the detector front-end on multiple high-speed serial links, low-latency data processing, data buffering, and data transmission to the ATLAS trigger and DAQ systems. In order to evaluate the different components, prototype boards in ATCA format equipped with modern Xilinx and Altera FPGAs have been built. We will report on the measured performance of the SERDES devices, the parallel signal processing using DSP slices, the implementation of trigger interfaces, using e.g. multi-Gb Ethernet, as well as the development of the ATCA infrastructure on the ROD prototype modules.

Speaker: Steffen Staerz (Inst. fuer Kern- und Teilchenphysik (IKTP)-Technische Universita)

Paper http://iopscience.iop.org/1748-0221/6/01/C01003

Slides TWEPP_Aachen_09_2010_v4.pdf

83 Optimizing latency in Xilinx FPGA implementations of the GBT

The GigaBit Transceiver (GBT) has been developed to provide data transmission and to replace the Timing , Trigger and Control (TTC) system between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, has been released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code was optimized for resource, as the GBT protocol is very heavy, but not for latency – which will yet be a critical parameter of the GBT when used in the trigger path. We have investigated different methods for minimizing the latency in Xilinx Virtex 5 and Virtex 6 components.

Speaker: Steffen Lothar Muschter (Stockholm University)

Paper http://iopscience.iop.org/1748-0221/5/12/C12017

Slides

• GBT-FPGA_optimization.odp
• GBT-FPGA_optimization.pdf
• GBT-FPGA_optimization.pdf

Trigger: Parallel Session A5

Convener: Emilio Petrolo (INFN, Sezione di Roma Tor Vergata-Universita degli Studi di Roma)

84 Level-1 jet trigger board for the ALICE Electromagnetic Calorimeter

The electromagnetic calorimeter (EMCAL) of ALICE is a large acceptance calorimeter that will enhance the capabilities for jet measurement. Based on the previous development made for the Photon Spectrometer (PHOS) level-0 trigger, a specific electronic upgrade was designed in order to allow a fast triggering on high energy jets (level-1). This development was made possible by the use of the latest generation of FPGA which can deal with the instantaneous incoming data rate of 26 Gbit/s and process it in less than 4 µs.

Speaker: Mr Olivier Bourrion (Laboratoire de Physique Subatomique et de Cosmologie (LPSC)-Univ)

Paper http://iopscience.iop.org/1748-0221/5/12/C12048

Slides STU_talk.pdf

85 The performance of the ATLAS Level-1 Calorimeter Trigger with LHC collision data

The ATLAS first-level calorimeter trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates and to measure total and missing ET in the ATLAS calorimeters. After more than two years of commissioning in situ with calibration data and cosmic rays, the system has now been extensively used to select the most interesting proton-proton collision events. Final tuning of timing and energy calibration has been carried out in 2010 to improve the trigger response to physics objects. An analysis of the performance of the level-1 calorimeter trigger will be presented, along with the techniques used to achieve these results.

Speaker: Juraj Bracinik (University of Birmingham, UK)

Paper http://iopscience.iop.org/1748-0221/6/01/C01078

Slides bracinik_twepp_2010_final.pdf

86 Upgrading the ATLAS Level-1 Calorimeter Trigger using Topological Information

The ATLAS Level-1 Calorimeter Trigger (L1Calo) is a fixed latency, hardware-based pipelined system designed for operation at the LHC design luminosity of 10^34cm-2s-1. Plans for a several-fold luminosity upgrade will necessitate a complete replacement for L1Calo (Phase II). But backgrounds at or near design luminosity may also require incremental upgrades to the current L1Calo system (Phase I). This paper describes a proposed upgrade to the existing L1Calo to add topological algorithm capabilities, using Region of Interest (RoI) information currently produced by the Jet and EM/Hadron algorithm processors but not used in the Level-1 real-time data path.

Speaker: Dr Yuri Ermoline (MSU)

Paper http://iopscience.iop.org/1748-0221/5/12/C12046

Slides TWEPP'10_ermoline.pdf TWEPP'10_ermoline.ppt

87 Upgrade of the ATLAS Muon Trigger for the SLHC

The upgrade of the LHC towards luminosity beyond the design value requires improved L1 trigger selectivity in order to keep the maximum total trigger rate at 100 kHz. In the ATLAS L1 muon trigger system this necessitates an increase of the pT threshold for single muons. Due to the limited spatial resolution of the trigger chambers, however, the selectivity for tracks above ~20 GeV/c is insufficient for an effective reduction of the L1 rate. We propose to used the precise track coordinates of the Monitored Drift Tube chambers of the ATLAS muon spectrometer for a decisive improvement of the pT determination and thus of the selectivity of the L1 muon trigger. Requirements on the trigger latency will also be discussed.

Speaker: Robert Richter (Max-Planck-Institut fur Physik)

Paper http://iopscience.iop.org/1748-0221/5/12/C12016

Slides L1_Upgrade_RR_23_09_2010_TWEPP.pdf L1_Upgrade_RR_23_09_2010_TWEPP.ppt

88 Enhancement of the ATLAS Trigger System with a Hardware Tracker Finder FTK

The existing three-level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~200 Hz for permanent storage at the LHC design luminosity of 10^34 cm^-2 s^-1. When the LHC reaches beyond the design luminosity, the load on the Level-2 trigger system will significantly increase due to both the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast Tracker (FTK) is a proposed upgrade to the current ATLAS trigger system that will operate at the full Level-1 accepted rate of 100 KHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories. The system design is being advanced and justified with the performance in important physics areas, b-tagging, tau-tagging and lepton isolation. The system requirement and capability are being evaluated with the ATLAS MC simulation at different LHC luminosities. The prototyping with current technology is undergoing and the R&D with new technologies has been started.

Speaker: Jinlong Zhang (Argonne National Laboratory (ANL))

Paper http://iopscience.iop.org/1748-0221/5/12/C12037

Slides TWEPP2010_Zhang.pdf

Radiation tolerant components and systems: Parallel Session B5b

Convener: Stephen Quinton (Rutherford Appleton Laboratory)

89 The Radiation Hardness of Specific Mulit-mode and Single-mode Optical Fibres at -25 deg. C. to full SLHC doses.

The Versatile Link project is a joint effort between CERN and several experiments to develop a high-speed optical link for use in the LHC upgrades. Of concern to the project is the fact that optical fibres experience higher levels of attenuation at low temperatures for the same integrated dose. This paper describes a CO2 cooling system which was used in a radiation environment for exposures of optical fibres exceeding 500kGy(Si) of 60Co gamma radiation exposed at a rate greater than 20kGy/hr while at the same time maintaining a temperature less than -20oC. The optical fibres under test were both single mode fibres and graded index multimode optical fibres (GRIN fibres). The multimode (single mode) fibres all operate at 850nm (1310 nm) and use VCSEL’s (EELs) as a source. Estimates are given of an upper bound on the effect of radiation on these cold fibres. Because of the harsh environment near radiation sources, there are difficulties making in-situ radiation damage measurements of optical fibres. The implications of these results for the readout of tracking detectors for SLHC are critical, as they will determine how close to the beam region the optoelectronics can be located.

Speaker: Nick Ryder (Unknown-Unknown-Unknown)

Paper http://iopscience.iop.org/1748-0221/5/11/C11023

Slides nickryder_twepp2010.pdf

90 Radiation-hard power LDMOS devices for DC-DC conversion in the ATLAS Upgrade experiment

This work presents radiation hardness studies performed on LDMOS devices of SGB25VGOD technology from IHP Microelectronics. These devices would constitute the power switches of the buck converters on the DC-to-DC powering scheme for the ATLAS Upgrade silicon tracker. Devices were irradiated with neutrons up to the target fluences expected inside ATLAS Upgrade. They exhibited very good radiation tolerance after irradiations, showing only minor increases of the threshold voltage and the on-resistance. These results make the devices suitable for their application in the silicon tracker. Additionally, simulations of the neutron irradiations were performed on technologically emulated LDMOS devices. Simulations reproduced quantitatively the on-resistance variations observed experimentally at the highest fluences.

Speaker: Mr Sergio Diez Cornell (Instituto de Microelectronica de Barcelona - Centro Nacional de Microelectronica IMB-CNM (CSIC))

Slides Diez_LDMOS_TWEPP10_last.pdf Diez_LDMOS_TWEPP10_last.ppt

13:05 Lunch

PLENARY 6 - Obsolescence issues for LHC Electronics

Convener: Wesley Smith (University of Wisconsin)

91 Obsolescence Issues for LHC Electronics

Parts Obsolescence, Diminishing Manufacturing Sources and Material Shortages (DMSMS), and End of Life (EOL) are used interchangeably to describe a variety of sustainability problems. They range from being unable to purchase or procure parts, components, or subcomponents, to being unable to sustain major, complex systems due to a lack of component availability or may result in excessive cost. Unresolved DMSMS issues can cause loss of functionality, and reduced availability of a system which could delay valuable experiments. There are several causes of DMSMS issues, most are out of the control of the user. I will describe how DMSMS problems affect the Defense and Aerospace Industries. I will show how our DMSMS issues and those of the Large Hadron Collider (LHC) maybe similar and why our proven solutions to them offer great promise for sustainment of the LHC. I will share lessons we have learned over the last 10 years in sustaining complex War-Fighter equipment, and how these lessons have been strategically applied to proactively resolve DMSMS problems. I will illustrate various ways our industry provides our customers maximum availability of the equipment through good DMSMS management practices, processes, tools and experienced DMSMS engineering analysis. I will explain the complexities and subtleties of finding optimal, best-value solutions to DMSMS problems, that maximize the availability of the LHC and minimize unexpected costs. Through various types of analysis, I will demonstrate how we evaluate multiple solutions for the best-value to the program and how to go about achieving these same results for the LHC.

Speaker: Vincent Spellane

Slides Obsolesence_of_LHC_Electronics_9_21_10_Spellane.pdf Obsolesence_of_LHC_Electronics_9_21_10_Spellane.pptx

PLENARY 7 - Reports from Working Groups

Convener: Wesley Smith (University of Wisconsin)

92 Power

Speaker: Philippe Farthouat (CERN)

Slides Twepp-10-PowerWG.pdf

93 Opto

Speaker: Prof. K.K. Gan (The Ohio State University)

Slides WG_Gan.pdf

94 MUG

Speaker: Kostas Kloukinas (CERN)

Slides

• MUG_meeting_WrapUp.pdf
• MUG_meeting_WrapUp.ppt
• TWEPP2010_SEEWG_Meeting.pdf
• TWEPP2010_SEEWG_Meeting.pdf
• TWEPP2010_SEEWG_Meeting.pptx

95 xTCA

Speaker: Magnus Hansen (CERN)

Slides Report_xTCA_WG_20100922.pdf Report_xTCA_WG_20100922.pptx

15:40 Break

POSTERS Session

Convener: Mitch Newcomer (University of Pennsylvania)

96 A 10Gb/s Serial Communication Transceiver in 0.13μm CMOS for a 2m Micro Twisted-Pair Cable

Pixel chips generate a large amount of data. In the foreseen application, the data has to be transported off chip via a micro twisted-pair cable. Because of the low bandwidth of the cable, equalization is needed. Pulse-width modulation turns out to be the best equalization method at the transmitter side. However, at 10Gb/s the eye-opening at the receiver side is very sensitive to the exact value of the pulse-width. This sensitivity can be significantly improved by using an on-chip parallel RC combination in series with the transmitter. A demonstrator chip in 0.13μm CMOS is designed to prove the concept.

Speaker: Dr Eisse Mensink (Bruco Integrated Circuits B.V.)

Paper http://iopscience.iop.org/1748-0221/5/11/C11025/

Poster PosterEiMe_F3.pdf

97 A 4.9-GHz Low Power, Low Jitter, LC Phase Locked Loop

An LC phase locked loop ASIC, fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology, has been characterized in lab. Random jitter and deterministic jitter are less than 2.5 ps and 10 ps, respectively. The power consumption at 4.9 GHz is 218 mW. The measured tuning range, from 4.7 to 5.0 GHz, is narrower than the simulated values of from 3.8 to 5.0 GHz. The narrow tuning range has been investigated and traced to the first stage of the divider. This will be corrected in the next submission. A test with a proton beam is scheduled in June.

Speaker: Tiankuan Liu (Department of Physics-Southern Methodist University (SMU))

Paper http://iopscience.iop.org/1748-0221/5/12/C12045/

Slides Liu_TWEPP10_LCPLL_revised.pdf Liu_TWEPP10_LCPLL_revised.ppt

98 A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will also be changed; all hit data will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that data rate off chip does not exceed 10 Gb/s. A C++ model has been created for statistical simulation and development. A VHDL implementation has been derived from this model.

Speaker: Mr Sander Heuvelmans (Bruco Integrated Circuits B.V.)

Paper http://iopscience.iop.org/1748-0221/6/01/C01093/

Slides PosterSaHe_F1.pdf

99 A Tezzaron-Chartered 3D-IC electronic for SLHC/ATLAS hybrid pixel detectors

Hybrid pixels detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness are currently used in vertex detectors for High Energy Physic experiments. As technology shrinking reaches some limitations, a way to face challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D technologies. This talk presents the design and test of the 3-D chip prototypes realized with the Tezzaron-Chartered technology, as well as the design and test of read-out chip demonstrators 2-D using the same 0.13μm Chartered technology. The 3-D variants are built by face to face, copper bonding of 2 electronics wafers. The first part includes all analog functions, and the second one is dedicated to digital. Finally, a sensor is foreseen to be connected to the read-out electronics by usual solder bumps. Design choices and test plans will be presented.

Speaker: Mr Patrick Pangaud (Centre de Physique des Particules de Marseille (CPPM))

Poster Poster_Twepp2010.pdf

100 An FPGA based back up version of the TileCal digitizer.

The ATLAS TileCalorimeter contains some 2000 digitizer boards with 2 TileDMU ASICs on each board. Although we have the agreed number of spares this paper discusses a backup version of the digitizer to be used in case more units are required. The TileDMU has been replaced with a cheap and readily available FPGA (Spartan 6) and we have replaced some components to protect against obsolescence. The focus is on achieving sufficient FPGA radiation tolerance using triple mode redundancy and scrubbing. We have also implemented in system programmability (JTAG) via the TTCrx.

Speaker: Mr Daniel Paer Erik Eriksson (Department of Physics-Stockholm University)

Paper http://iopscience.iop.org/1748-0221/5/11/C11020

Poster BackupDigitizer.pdf BackupDigitizer.ppt

101 Architecture and Instrumentation of a Silicon Strips Test Beam Telescope for the Institute for High Energy Physics, Beijing

A collaboration between Fermilab and the Institute for High Energy Physics (IHEP), Beijing has developed a test beam telescope for the IHEP test beam facility. This telescope is based on 5 stations of silicon strips detectors with a pitch of 60 microns. The total active area of the detector is about 12cm x 10cm. Readout of the strips is provided through the use of VA1' ASICs mounted on custom Hybrid printed circuit boards and interfaced to Adapter Cards via copper-over-kapton flexible circuits. The Adapter Cards are connected to the Fermilab CAPTAN data acquisition nodes for data readout and channel configuration. These nodes deliver readout and temperature data from triggered events to an analysis computer over gigabit Ethernet links.

Speaker: Mr Alan Prosser (Fermilab)

Paper http://iopscience.iop.org/1748-0221/5/12/C12039

102 Associative Memory design for the Fast TracK processor (FTK) at Atlas

We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. We propose now a new design (90 nm technology) where we introduce a full custom standard cell. This is a customized design that allows to maximize the pattern density and to minimize the power consumption. We discuss also possible future extensions based on 3-D technology. This processor has a flexible and easily configurable structure that makes it suitable for applications also in other experimental environments.

Speaker: Matteo Beretta (Istituto Nazionale Fisica Nucleare (INFN) - Laboratori Nazionali di Frascati)

103 ATLAS IBL: Integration of new hw/sw readout features for the additional layer of pixels

An additional inner layer for the existing ATLAS pixel detector, called insertable B-layer (IBL), is under design and it will be installed by LHC-PHASE1. New front-end readout ASICs have already been fabricated and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, back-of-crate (BOCs) cards and readout driver cards (RODs). The paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS DAQ system.

Speaker: Dr Alessandro Gabrielli (Dipartimento di Fisica)

Paper ATL-INDET-PROC-2010-032.pdf http://iopscience.iop.org/1748-0221/6/01/C01018

Poster TWEPP_poster.pdf

104 ATLAS Silicon Microstrip Tracker Operation and Performance

The SemiConductor Tracker (SCT), made up from silicon micro-strip detectors is the key precision tracking device in ATLAS, one of the experiments at CERN LHC. The completed SCT is in very good shape: 99.3% of the SCT strips are operational, noise occupancy and hit efficiency exceed the design specifications. In the talk the current status of the SCT will be reviewed. We will report on the operation of the detector and observed problems, with stress on the sensor and electronics performance.

Speaker: Dr Petra Haefner (MPI Munich)

Paper http://iopscience.iop.org/1748-0221/5/12/C12050

105 Charge Sensitive Amplifier (CSA) in cold gas of Liquid Argon (LAr) Time Projection Chamber (TPC)

The common channel of this 8-channel chip is made of a Low noise Charge Sensitive Amplifier (CSA) with respectively 250fF and 4MΩ feedback capacitance and resistance. The CSA is followed by a bandpass filter centred at 1µs and a buffer line driver. An ‘i2c-like’ protocol serial link allows slow control of registers, giving multiple configuration features to the circuit. The input referred noise of 1500 e- rms had been measured at -100°C with an input detector capacitance of 250pC. Thanks to those performances, the minimal signal of 18000e- (2.88fC) will be correctly measured.

Speaker: Herve Mathez (Institut de Physique Nucleaire de Lyon (IPNL)-Universite Claude)

Paper http://iopscience.iop.org/1748-0221/6/01/C01005/

106 CMS Pixel Detector with new Digital Readout Architecture

The CMS pixel detector is planned to be upgraded in 2015 to a new one with a significantly reduced material budget. The new pixel system with more layers has to operate through the existing services at double the luminosity. Therefore a new readout scheme is implemented in the new pixel read out chip (ROC). A detailed description of the ASIC modifications of the digital readout interface of the ROC is presented as well as the results and the performance of the physics based electronic simulations of a complete pixel module consisting of 16 pixel ROCs and a token bit manager chip.

Speaker: Beat Meier (PSI)

Paper http://iopscience.iop.org/1748-0221/6/01/C01011

Poster TWEPP2010_Meier_PSI.pdf

107 CO2 Cooling for the CMS Tracker at SLHC

For a new CMS tracker at SLHC cooling of the silicon sensors and their electronics is a crucial issue. An evaporative CO2 system is currently under investigation, which could provide more cooling power at a lower mass than the current mono-phase liquid system. Additionally CO2 could allow lower operating temperatures, which is beneficial for the sensor performance and lifetime. The recirculating CO2 test system at RWTH Aachen University will be presented. First results of dryout (loss of cooling capability), temperature and pressure drop measurements and comparisons with theory will be shown.

Speaker: Jennifer Merz (RWTH Aachen University)

Paper http://iopscience.iop.org/1748-0221/6/01/C01091

Poster Merz_TWEPP_poster.pdf

108 Components for the Control System of a Future Pixel Detector

Upgrades of the LHC and the ATLAS experiment will include a new pixel detector. To operate a future pixel detector a completely new detector control system (DCS) is needed, that is embedded in the pixel electronic systems. Next to high reliabilty the requirements for the detector control system are low mass, less usage of material and cable and radiation hardness to always guarantee a save operation of the experiment. To meet these requirements we propose a DCS network which consists of a DCS chip and a DCS controller. With a special focus on the communication interface, radiation hardness and robustness against single event upsets, we present the development of the first prototypes and the plans for testing.

Speaker: Ms Kathrin Becker (Bergische Universitaet Wuppertal, Germany)

Paper http://iopscience.iop.org/1748-0221/6/01/C01017/

Poster TWEPP_2010_posterA0_vfinal.pdf

109 Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs

A new SEU-robust D-flip-flop register structure was designed in 130 nm CMOS for utilization in a rad-tolerant library. The register was tested in a heavy ion beam facility and showed a cross section lower than 1e-10 cm²/bit in the LET range (1.2 – 62.0 MeVcm²/mg) representing an improvement of 1000 times over previously studied standard library cells. No errors were observed at LETs under 30 MeVcm²/mg.

Speaker: Dr Sandro Bonacini (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11019

Poster poster.pdf

110 Design and development of micro-strip stacked module prototypes for tracking at S-LHC

Experience at high luminosity hadrons collider experiments shows that tracking information enhances the trigger rejection capabilities while retaining high efficiency for interesting physics events. The design of a tracking based trigger for Super LHC (S-LHC), the already envisaged high luminosity upgrade of the LHC collider, is an extremely challenging task, and requires the identification of high-momentum particle tracks as a part of the Level 1 Trigger. Simulation studies show that this can be achieved by correlating hits on two closely spaced silicon strip sensors. The progresses on the design and development of micro-strip stacked prototype modules and the performance of few prototype detectors will be presented. The prototypes have been built with the silicon sensors and electronics used to equip the present CMS Tracker. Correlation of signals collected from sensors are processed off detector.Preliminary results in terms of signal over noise and tracking performance with cosmic rays will also be shown.

Speaker: Francesco Fiori (INFN Sezione di Pisa (INFN))

Paper http://iopscience.iop.org/1748-0221/5/11/C11018

Slides Design_and_development_of_micro-strip_stacked_module_prototypes.pdf Design_and_development_of_micro-strip_stacked_module_prototypes.pptx

111 Design and Verification of a Bit Error Rate Tester in Altera FPGA for Optical Link Developments

This paper presents a Bit Error Rate (BER) Tester implemented in an Altera Stratix II GX signal integrity development kit. Architecture of the tester is described. Experimental and simulation results are discussed. A parallel to serial PRBS generator and a bit/link status error detector are deployed to characterize serial data link performance. The auto-correlation pattern enables receiver synchronization without specifying protocol at the physical layer. An error logging FIFO records both bit error data and link operation events. An optimization scheme is established to maximize throughput with shortest dead time. The tester operates up to 6.5 Gbps in 4 duplex channels.

Speaker: annie xiang (Southern Methodist University)

Paper http://iopscience.iop.org/1748-0221/5/12/C12003/

Poster postertwepp2010.pdf

112 Design of a Small-Dimension Low-Noise Dropout Regulator Built-in Monolithic Active Pixel Sensors (MAPS) for STAR Experiment

This paper presents an on-chip low dropout (LDO) regulator which provides the clamping voltage in monolithic active pixel sensors (MAPS) for STAR experiment. By utilizing a buffer and a serial RC network, the regulator can achieve good stability, low power and low noise. Its output voltage is programmable by using a digital-controlled resistor. The proposed LDO regulator has been implemented in a 0.35 µm CMOS process. The die area is 327 µm × 119 µm. The power dissipation is 600 µW, and the output noise spectral densities at 100 Hz and 1 kHz are 222 and 74.8 nV/√Hz, respectively.

Speaker: Jia WANG (Institut Pluridisciplinaire Hubert CURIEN,France; Northwestern Polytechnical University, China)

Paper http://iopscience.iop.org/1748-0221/5/12/C12032

Poster PosterTwepp10_Jia.pdf

113 Design Studies of the ATLAS Muon Level-1 Trigger based on the MDT Detector for the LHC Upgrade

The present muon Level-1 trigger of the ATLAS is given by dedicated detectors for the trigger; RPC and TGC chambers in barrel and endcap regions, respectively. The monitored drift tube (MDT) chambers and the CSC are used for precision measurements of muon tracks. The performance of the muon Level-1 trigger is limited by the momentum resolution of the trigger chambers. In order to improve the trigger performance, the muon track finding scheme based on the MDT signals is envisaged. The studies of the algorithm and the estimation of the trigger latency will be presented.

Speaker: Osamu Sasaki (High Energy Accelerator Research Organization (KEK))

Paper http://iopscience.iop.org/1748-0221/5/12/C12021

Poster A0poster.pdf A0poster.pptx

114 Detailed Performance Study of ATLAS Endcap Muon Trigger with Beam Collision Data

In 2009 the first beam collision was occurred at LHC and the ATLAS detector has started data taking with beam collision at 7TeV since May 2010. Thanks to the eagerest commissioning works with test pulses, cosmic rays and single beams, the Level-1 endcap muon trigger system can successfully provide trigger signals on proper timing for the ATLAS detector. The phase adjustment of the gate timing, optimization of the gate width and others have been done using real muons from the beam collision in the commissioning phase. Insufficient immunity of the system against the frequency change during LHC ramping-up and beam chromaticity was found. After the detailed investigation into such unexpected feature, we could optimized data taking procedure eventually by minimizing error occurrence. We report results of detailed studies on the performance of Level-1 endcap muon trigger with beam collision data.

Speaker: Mr Takashi Hayakawa (Department of Physics-Kobe University-Unknown)

Paper http://iopscience.iop.org/1748-0221/5/11/C11010

Slides e-mail address:takashi.hayakawa@cern.ch

115 Development and Online Operation of Minimum Bias Triggers in ATLAS

The design of minimum bias triggers should allow for a highly efficient selection on pp-collisions, while minimising any possible bias in the event selection. In ATLAS two main minimum bias triggers have been developed using complementary technologies. A hardware based first level trigger, consisting of 32 plastic scintillators, has proven to efficienctly select pp-interactions. In particular during the start-up phase this trigger played a crucial role for the commissioning of the central trigger processor and detector sub-systems. A complementary selection is achieved by a multi-level minimum bias trigger, seeded off a random trigger on filled bunches. For the event selection at higher trigger levels a dedicated algorithm was developed, able to cope with around 86 millions of detector signals per bunch-crossing. We will present these trigger systems and their deployment online, highlighting their performance and trigger efficiencies. We outline as well the operation with increasing beam intensities and luminosities.

Speaker: Mr Tim Martin (University of Birmingham, UK)

Paper http://iopscience.iop.org/1748-0221/5/12/C12051

116 Development of a beam test telescope based on the Alibava readout system.

A telescope for a beam test have been developed and it is described. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment. The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test (DUT board). Both the XYT boards and the DUT boards use two Beetle ASICs to perform the XY coordinate measurements and the DUT readout, respectively. An Alibava mother board is used to read out and to control each XYT/DUT board from a common trigger signal and clock signal. The data collected by each Alibava board is sent to a master card, which is in charge of merging the data streams received. It also distributes the common trigger and clock signals and it performs the communication with the DAQ software by 100M Ethernet.

Speaker: Ricardo Marco Hernandez (Instituto de Fisica Corpuscular (IFIC)-Universitat de Valencia-U)

Paper http://iopscience.iop.org/1748-0221/6/01/C01002

Poster Poster_TWEPP2010.pdf

117 Development of an Universal ROC

Since 2007 we design and develop a ROC (read-out controller) for FAIR's data-acquisition. While our first implementation solely focused on the nXYTER, today we are also designing and implementing readout logic for the GET4 which is supposed to be part of the ToF detector and the CBM-XYTER which is supposed to be used in various other detectors like the STS or the TRD detectors. Furthermore we fully support both, Ethernet and Optical Transport, as two transparent solutions. The usage of a strict modularization of the Read Out Controller enables us to provide an Universal ROC, where front-end specific logic and transport logic can be combined as flexible as possible.

Speaker: Mr Sebastian Manz (Heidelberg University)

Paper http://iopscience.iop.org/1748-0221/5/11/C11017

Poster An_Universal_Read-Out_Controller.png

118 Developments for the upgrade of the CMS HCAL front-end electronics

We present an upgrade plan for the CMS HCAL front-end electronics. The HCAL upgrade is required for the increased luminosity of SLHC Phase I which is targeted for 2015. A key aspect of the HCAL upgrade is to add detector segmentation. The increased segmentation is achieved by replacing the hybrid photodiodes (HPDs) with silicon PMTs (SiPMs). We plan to instrument each fiber of the calorimeter with an SiPM (103,000 total). The upgrade plans include replacement of all electronic modules and a new custom ADC with matched sensitivity and timing information. The increased data volume requires higher speed transmitters. The additional power dissipation for the readout electronics requires better thermal design, since much of the on-detector infrastructure (front-end electronics crates, cooling pipes, optical fiber plant, etc.) will remain the same. We are considering to use circuits from the Cern MIC group (GBT and DC-DC converter). We will report on performance requirements and on the preliminary designs.

Speaker: Tullio Grassi (FNAL / Univ. of MD)

Paper http://iopscience.iop.org/1748-0221/5/11/C11005

Poster CMSHCAL_TWEPP2010_Poster.pdf

119 Digital part of PARISROC2: a photomultiplier array readout chip

PARISROC is the front-end ASIC designed to read 16 photomultiplier (PM) tubes for neutrino experiments. It’s able to shape, discriminate, convert and readout data in an autonomous and channel-independent mode. The tests made on PARISROC1 have shown some limitations on time measurements and on hit rate capability. In order to correct these points, the digital part of PARISROC2 has been completely modified to add new features and improvements. First, it integrates a new time to amplitude converter with less than 1 ns resolution. Secondly, conversion and readout has been speed-up by a factor of 4 to handle the PM hit rate. The chip was received in February 2010 and is now under test.

Speaker: Dr Gisèle MARTIN-CHASSARD (Laboratoire de l Accélérateur Linéaire)

Paper http://iopscience.iop.org/1748-0221/5/11/C11004/

120 Electronics and Cooling for the Silicon Vertex Detector of the Belle II Experiment

A major upgrade of the KEK-B factory (Tsukuba, Japan), aiming a peak luminosity of 8 x 10^35 / (cm^2s), which is 40 times the present value, is foreseen until 2013. Consequently an upgrade of the Belle detector and in particular its Silicon Vertex Detector (SVD) is required. We will introduce the concept and prototypes of the full readout chain of the Belle II SVD. Its APV25 based front-end utilizes the Origami chip-on-sensor concept, while the back-end VME system provides online data processing as well as hit time finding using FPGAs. Furthermore, the design of the foreseen DSSDs, the mechanics and the cooling system will be discussed.

Speaker: Mr Christian Irmler (HEPHY Vienna)

Paper http://iopscience.iop.org/1748-0221/5/12/C12043

Poster irmler_twepp_2010_a0.pdf

121 Electronics to support studies of SiPMs for High Energy Physics

This report describes a system designed to simplify the use of SiPM in small scale projects, with 1 to 100 SiPMs. The system consists of 4ch digitizer boards (called TB4), and Windows software. Each TB4 contains 4 channels of electronics with gain appropriate for use with SiPMs, and four 14bit, 250MSPS digitizers. Each TB4 also has a Cockroft Walton voltage multiplier to generate the necessary bias for SiPMs of up to 100V. There is only one bulk bias, but there is an offset for each channel, to enable the fine tuning of the bias to each SiPM. Each TB4 interfaces to the computer via USB, and can transfer the digitized waveforms of up to 4k points per channel. The TB4 also includes a moderate sized FPGA for implementing algorithms (such as digital filtering or self triggering) on board. There is also an optional motherboard which can be used with up to four TB4 boards which provides higher bandwidth readout. It can be read out via Fast Ethernet or custom LVDS protocols. Each mother board also provides for synchronization of clocks and triggers and multiple motherboards can be connected together to build a larger system. This system has been successfully used at test beam at CERN and Fermilab and numerous other test at various universities.

Speaker: Dr Paul Rubinov (Fermilab)

Poster TWEPP_2010.pdf

122 First experiences with the LHC BLM sanity checks

The reliability concerns have driven the design of the LHC BLM system from the early stage of the studies up to the present commissioning and the latest development of diagnostic tools. To protect the system against non-conformities, new ways of automatic checking have been developed and implemented. These checks are regularly and systematically executed by the LHC operation team to insure that the system status is after each test "as good as new". The sanity checks are part of this strategy. They are testing the electrical part of the detectors (ionisation chamber or secondary emission detector), their cable connections to the front-end electronics, further connections to the back-end electronics and their ability to request a beam abort. During the installation and in the early commissioning phase, these checks have shown their ability to find also non-conformities caused by unexpected failure event scenarios. After a description of the LHC BLM system and a brief overview of the different checks, the sanity checks will be described in details and the latest performances and typical non-conformities will be presented.

Speaker: Mr Jonathan Emery (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12044

Poster POSTER-TWEPP2010.pdf

123 FPGA based data-flow injection module at 10 Gbit/s reading data from network exported storage and using standard protocols

The goal of the LHCb readout upgrade is to speed up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or similar technologies and might also need new networking protocols such as a customized, light-weight TCP or more specialised protocols. A test module is being implemented, which integrates in the existing LHCb infrastructure. It is a multiple 10-Gigabit traffic generator, driven by a Stratix IV FPGA, which is flexibile enough to either generate LHCb's raw data packets internally or read them from external storage via the network. For reading the data we have implemented a light-weight industry standard protocol ATA over Ethernet (AoE) and we present an outlook of using a filesystem on these network-exported disk-drivers. We will present here first the implementation of the complete IP protocol stack (including ARP, ICMP) up to the UDP level, which allows to tie into standard utilities like for example syslog. We present studies on higher-level protocols such as TCP. We will go through the technology analysis, implementations and performance measurements.

Speaker: Mr Benjamin Lemouzy (Conseil Europeen Recherche Nucl. (CERN))

Paper http://iopscience.iop.org/1748-0221/6/02/C02003

124 FPGA-based readout for double-sided silicon strip detectors

This work presents an FPGA-based readout system for double-sided silicon strip sensors based on the APV25 Frontend-Chip. The system consists of an ADC-card and a digital readout board containing an FPGA. Data extraction algorithms implemented in the FPGA allow baseline and pedestal correction, hit detection and event-building. These algorithms provide an efficient data reduction tool and high readout rates. Details of the system, the algorithms applied and performance will be discussed using data collected in various tests experiments. The work was supported by EU Dirac FP6 and BMBF.

Speaker: Mr Robert Schnell (HISKP, University Bonn)

Paper http://iopscience.iop.org/1748-0221/6/01/C01008

Poster FPGA-based Readout for Double-Sided Silicon Strip Detectors

125 Free-Space Optical Interconnects for Cableless Readout in Particle Physics

Particle physics detectors utilize readout data links requiring a complicated network of copper wires or optical fibers. These links are both massive and costly. Upgrades to such detectors may require additional bandwidth to be provisioned with limited space available to route new cables or fibers. In contrast, free-space optical interconnects will offer cableless readout, thereby resulting in significant reductions of material and labor. A collaborative effort between Vega Wave Systems and Fermilab is pursuing the development of a unique free-space optical link design that utilizes the transparency of silicon at 1300nm and 1550nm wavelengths; such free-space links will offer significant advantages in future detector systems. Experiments have been performed to characterize the bit error rate performance of a prototype link through bulk silicon and detector samples at multi-gigabit rates. Further experiments will explore the use of wavelength division multiplexing to combine data, control, and trigger information on the same physical link.

Speaker: Mr Alan Prosser (Fermilab)

Paper http://iopscience.iop.org/1748-0221/5/12/C12038

126 Front end electronics for Hybrid Avalanche Photo Diode

For the upgrade of the Belle detector (Belle-II) at the KEK collider, we are developing a proximity focusing ring imaging Cherenkov detector using aerogel as radiator, which will allow efficient separation of kaons from pions in the wide range of particle momenta up to 4Gev/c. One of the photon detector candidates (which has to operate in a strong magnetic field of 1.5T) is a HAPD of proximity focusing type with 144 channels. The present work discusses the design and implementation of the special front end electronics for this device. The analog signals from HAPDs will be first fed into Asic chips having amplification, shaping and comparator capabilities for 36 channel per chip. The HAPD readout will consist of 4 readout chips and an FPGA which will allow efficient data compression and transfer. The design has to take into account very limited space available and very harsh environment. We will present the bench test measurements of the HAPD prototype front end electronics.

Speaker: Mr Andrej Seljak (Jožef Stefan institute, Ljubljana Slovenia)

Poster twepp2010_Seljak.pdf

127 Global noise studies for the CMS Tracker system upgrage

The characterization of the noise emissions of DC-DC converters and their impact at the system level is critical to optimize the design of the detector and define rules for the integration strategy. This paper presents the effects of the circuitry impedance of the tracker power distribution network on the noise emissions of DC-DC converters. It allows to quantify the real noise emitted by the power converters and its impact in the overall noise of the tracker system. Conducted and radiated noise emissions at the input / output terminals of the DC-DC converters has been simulated and measured for different power network and FEE impedances. System aspects as granularity, stray capacitances of the system and different working conditions of the DC-DC converters are presented too. This study has been carried out using simulation models and real measurements of noise emissions present in DC-DC converters operating in the real scenario. The results of these studies show important recommendations and criteria to be applied to integrate the DC-DC converters to minimize the system noise level.

Speaker: Dr Fernando Arteche (Instituto Tecnologico de Aragon)

Paper http://iopscience.iop.org/1748-0221/5/12/C12029

128 High speed data transfer with FPGAs and QSFP+ modules

We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ module. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We implemented a complete testbench based on a commercial development card mounting an Altera Stratix IV FPGA with 24 serdes at 8.5 Gbps, together with a custom mezzanine hosting three QSFP+ modules. We characterize all parts of this tranmission system with signal integrity, bit error rate and jitter measurements at different data rates and cables lenghts.

Speaker: Dr Andrea Salamon (INFN Sezione di Roma Tor Vergata)

Paper http://iopscience.iop.org/1748-0221/5/12/C12019/

Poster TWEPP-10.salamon.pdf

129 Low Voltage Power Supply Using Step-Down Piezoelectric Transformer

A low voltage power supply was developed with a step-down piezoelectric transformer (PT), capable of supplying up to 4 A at an output voltage of 2 V, where the efficiency was estimated to be better than 80 %. The PT was 15 by 15 by 5 mm in size and composed of two layers at the primary and of 40 layers at the secondary. A new PT is manufactured with an improved process to have a reduced internal-loss and a higher Q value to deliver more than 5 A. The power supply has been studied extensively without an inductance in the driving circuitry and identified the issues to overcome.

Speaker: Yoshinobu Unno (KEK)

Poster poster_TWEPP.pdf

130 LVDS tester: A systematic test of cable signal transmission at the ALICE experiment

In the ALICE experiment, the Low-Voltage Differential Signalling (LVDS) format is used for the transmission of trigger inputs from the detectors to the Central Trigger Processor (CTP), the L0 trigger outputs from Local Trigger Units (LTU) boards back to the detectors and the BUSY inputs from the sub-detectors to the CTP. ALICE has designed a developed set-up, called the LVDS transmission tester, that aims to measure various transmission quality parameters for long period runs in an automatic way. These tests are normally carried out by measuring the bit-error rate (BER). In this talk, the key features of how the synchronisation of trigger inputs is handled in ALICE will be discussed. Furthermore, the uncertainties on the BER measurements will also be discussed. Results and conclusions from these tests will be presented in this conference.

Speaker: Dr Daniel Tapia Takaki (University of Birmingham / at CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12041

131 MAROC, a generic photomultiplier readout chip

The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe (~1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ~5 pC) and trigger (discrimination from 10fC). This third version showed very good performances that are presented here.

Speaker: Ms Sylvie BLIN (LAL Orsay - IN2P3)

Paper http://iopscience.iop.org/1748-0221/5/12/C12007/

132 Measurement of the thermal resistance of VCSEL devices

Future high energy physics experiments will operate at energies much higher than the present ones. To read out even the innermost detectors electronics and optical components must be developed to survive the harsh conditions during the lifetime of the experiments. It has been found that for VCSEL the irradiation hardness is connected to the temperature behavior of the device and that an increase of temperature above a certain value causes a loss of light power. A test stand to qualify the effect of heat in the device and the adoption of the heat sink has been realized. Measurements to show the effect of heat and measure the thermal resistance of laser devices are presented.

Speaker: Dr Tobias Flick (Bergische Universitaet Wuppertal)

Paper http://iopscience.iop.org/1748-0221/6/01/C01021/

Slides Flick_Poster_TWEPP2010.pdf

133 Mechanics and detector integration in the PANDA Micro-Vertex-Detector

The Micro-Vertex-Detector is the innermost detector of the PANDA experiment using silicon pixel detectors in the inner and double-sided microstrip detectors in the outer parts. The ongoing hardware development, the implementation of the cooling system and the detector integration will be highlighted. This includes a summary of measurements with test systems, the machining of support components and the description of the cooling, cabling and support concept. All information is collected in a detailed detector model which is implemented into the detector simulation package to check the physics performance of the MVD during the detector development. Supported by EU and BMBF

Speaker: Thomas Würschig (HISKP, Uni Bonn)

Paper http://iopscience.iop.org/1748-0221/5/12/C12024

Poster TWEPP-ID25.pdf

134 MICROROC: MICROMEsh GAseous Structure Read-Out Chip

MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active part of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). To validate the concept of digital hadronic calorimetry, a cubic meter technological prototype, made of 40 planes of one squared meter each, is compulsory. Such a technological prototype involves not less than 400 000 electronic channels, thus requiring the development of ASIC. Based on the experience of previous ASICs (DIRAC and HARDROC) and on multiple testbeam results, a new ASIC, called MICROROC (MICRO mesh gaseous structure Read-Out Chip), is currently beeing jointly developped at IN2P3 by OMEGA/LAL and LAPP microelectronics goups. It should be submitted to foundry in june 2010, and prototypes are expected to be delivred at the beginning of september. MICROROC is a 64 channel mixed-signal integrated circuit based on HARDROC manufactured in AMS 350 nm SiGe technology. Analog blocks and the whole digital part are reused from HARDROC, but the very front-end part, ie the preamplifier and shapers, has been especially re-designed for one square meter MICROMEGAS detectors, which require HV sparks robustness for the electronics and also very low noise performance to detect signals down to 2fC with an anode capacitance of. Each channel of the MICROROC chip is made of a fixed gain charge preamplifier, two different adjustable shapers, three comparators and a random access memory used as a digital buffer. Other blocks, like 12-bit DAC, configuration registers, bandgap voltage reference and LVDS receiver are included. All these blocks are power-pulsed, thus reaching a power consumption equal to zero in standby mode. After characterisation of the MPW prototypes, a low volume production will be packaged in TQFP160 with the same pinout as the HARDROC chip. Therefore bulk MICROMEGAS detectors with embedded MICROROC will be straightforward built, using HARDROC previously designed PCBs and the same data acquisition system.

Speaker: Gisèle Martin-Chassard (OMEGA, Laboratoire de l'Accélérateur Linéaire, LAL, Université Paris-Sud, CNRS/IN2P3)

135 Modelling radiation-effects in semiconductor lasers for use in SLHC experiments

Optical link components will typically be exposed to intense radiation fields during operation in the SLHC inner detectors and their qualification in terms of radiation tolerance is thus required. We have created a model that describes a semiconductor laser undergoing irradiation to enable the extrapolation to full lifetime total fluences from lower fluence radiation tests. This model uses a rate-equation approach with modified gain calculation that takes thermal rollover into account. The model is used to fit experimental data obtained during high-fluence (in excess of 10^15 n/cm^2) neutron irradiation testing in 2009 and its prediction capability is evaluated.

Speaker: Mr Pavel Stejskal (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12033

Poster PosterTWEPP10.pdf

136 Overview of High Level Synthesis tools

High Level Synthesis takes an abstract behavioural or algorithmic description of a digital system and creates a register transfer level structure that realises the described behaviour. Various methodologies have been developed to perform such synthesis tasks. Much research has lead to the development of electronic design automation tools capable of HLS that are now being accepted by industry. This paper presents the current leading tools and the different concepts of HLS used in each. It makes a comparison between the different approaches and highlights their advantages and limitations. We also present examples of high level synthesis using these techniques.

Speaker: Mr Spyridon Georgakakis (CERN)

Poster Twepp2010.png

137 Parallel Optics Technology Assessment for the Versatile Link Project

This paper describes the assessment of commercially available and prototype parallel optics modules for possible use as back end components for the Versatile Link common project. The assessment covers SNAP12 transmitter and receiver modules as well as optical engine technologies in dense packaging options. Tests were performed using vendor evaluation boards (SNAP12) as well as custom evaluation boards (optical engines). The measurements obtained were used to compare the performance of these components with single channel SFP+ components operating at 850 nm over multimode fibers. In addition to the test results for these components, the design of custom hardware to serve as evaluation platforms for optical engine products will be described. This hardware is being designed to operate in stand-alone bench tests as well as serving as a mezzanine card for a uTCA carrier board.

Speaker: Mr Alan Prosser (Fermilab)

Paper http://iopscience.iop.org/1748-0221/6/01/C01009

138 Performance Evaluation of Zero- Biased VCSEL for High Speed Data Transmission

In an optical transceiver, the power consumption related to the operation of the laser device takes a significant parcel of the total consumed power. The reduction of it is an important issue when a large number of transceiver devices are interconnected in an optical network, such as the one that supports the data transmission in particle physics experiments. An analysis and simulation results will be presented regarding the operation of a bias-free VCSEL device based on a previously developed model. The impact on BER of the increased turn-on jitter due to the bit-pattern and spontaneous emission will be considered.

Speaker: Mr Sergio Silva (INESC Porto, Faculdade de Engenharia, Universidade do Porto)

Paper http://iopscience.iop.org/1748-0221/5/11/C11012/

Poster twepp2010_ssilva_poster_20100913.pdf twepp2010_ssilva_poster_20100913.ppt

139 Performance of a new Preamplifier-Shaper-Discriminator chip for the ATLAS MDT Chambers in 130 nm IBM technology

We present the performance of a newly developed analogue chip for readout of the ATLAS muon drift-tube (MDT) chambers, using the IBM 130 nm CMOS 8RF-DM technology. The 4-channel Amplifier-Shaper-Discriminator (ASD) chip of 2.1 * 2.1 mm2 size was designed to match the analogue performance of the presently used device in 0.5 um Agilent technology, which is now obsolete. The aim of this first design cycle was to see how well the measured chip performance corresponds to the simulation results, in particular with respect to the crucial parameters pulse shape, crosstalk, gain uniformity and noise. First results from a neutron irradiation test will also be discussed.

Speaker: Mr Brad Weber (Max Planck Institute For Physics - Munich)

Poster TWEPP10_HECPAS_Poster_v3.pdf

140 Performance of the Fast Beam Conditions Monitor BCM1F of CMS in the first running periods of LHC

The Beam Conditions and Radiation Monitoring System, BRM, is implemented in CMS to protect the detector and provide an interface to the LHC. Seven sub-systems monitor beam conditions and the radiation level on different time scales. They detect adverse beam conditions, facilitate beam tuning close to CMS, and measure the doses accumulated in different detector components. Data are taken and analysed independently of the CMS data acquisition, displayed in the control room, and provide inputs to the trigger system and the LHC operators. The Fast Beam Conditions Monitor, BCM1F, is a flux counter close to the beam pipe inside the tracker volume. It uses single crystal CVD diamond sensors, radiation hard FE electronics, and optical signal transmission to measure the beam halo as well as collision products bunch by bunch. The system has been operational during the initiatory runs of LHC in September 2008, and works reliably since the restart in 2009 and is invaluable to CMS for everyday LHC operation. A characterisation of the system on the basis of data collected during LHC operation is presented.

Speaker: Mr Ringo Schmidt (Deutsches Elektronen-Synchrotron (DESY))

Paper http://iopscience.iop.org/1748-0221/6/01/C01004

Poster TWEPP_Poster.pdf

141 PMm2: A R&D on a triggerless acquisition for next generation neutrino experiments

The next generation of proton decay and neutrino experiments, the post-SuperKamiokande detectors as those that will take place in megaton size water tanks, will require very large surfaces of photodetection and a large volume of data. Even with large hemispherical photomultiplier tubes (PMT), the expected number of channels should reach hundreds of thousands. An french ANR funded R&D program to implement a solution is presented here. The very large surface of photodetection is segmented in macro pixels made of 16 hemispherical (12 inches) PMT connected to an autonomous underwater front-end electronics working on a triggerless data acquisition mode. The data transmission rate towards the surface DAQ is 10 Mb/s per cable. This architecture allows to reduce considerably the cost and facilitate the industrialization. The poster presents the complete architecture of the prototype, from the 16 PMT to the surface DAQ, and tests results with 16 (1 inch) PMT, validating the whole electronics, the built-in gain adjustment and the calibration principle.

Speaker: Mr Eric Wanlin (Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11)

Paper http://iopscience.iop.org/1748-0221/6/01/C01081

Poster poster_EW_twepp2010.pdf poster_EW_twepp2010.ppt

142 Power Supply Distribution System for Calorimeters at the LHC beyond the nominal luminosity

This paper investigates the use of switching converters for the power supply distribution network in the ATLAS experiment when the Large Hadron Collider (LHC) will be upgraded beyond the nominal luminosity. Due to the highly hostile environment the converters must operate in, all the main aspects are considered in the investigation, from the selection of the switching converter topologies to the thermal analysis of components and PCBs, with attention to reliability issues of power devices subject to ionizing radiations. The analysis focuses on the particular, but crucial, case of the power supplies for calorimeters, though several outcomes of research can profitably be applied to other detectors like muons

Speaker: Mr G. Spiazzi (Universita di Padova, Italy)

143 R&D Towards Cryogenic Optical Links

A number of critical active and passive components of optical links are successfully tested at 77 K or lower, demonstrating a potential to develop optical links operating inside the Liquid Argon Time Projection Chamber (LArTPC) detector cryostat. Ring oscillators, individual MOSFETs, and a 16:1 5-Gbs serializer fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS technology continue to function throughout the temperature cycling from room temperature to 4.2 K, 15 K, and 77 K respectively. One type of vertical-cavity surface-emitting laser diodes have been observed to lase from room temperature to 77 K. Optical fibers and optical connectors exhibit small insertion loss change from room temperature to 77 K.

Speaker: Mr Chonghan Liu (Southern Methodist University)

Paper http://iopscience.iop.org/1748-0221/5/12/C12030/

Poster TWEPP10_coldlink_poster.pptx

144 R&D towards the Module and Service Structure design for the ATLAS Inner Tracker at the Super LHC (SLHC)

The main goal of this R&D program is to prove to the community that a modular silicon strip tracker concept is a reasonable design that can satisfy the required material, mechanical, electrical and thermal performance specifications throughout the SLHC period. The R&D program places considerable emphasis on design aspects that minimize the development and construction effort and cost, while maintaining an optimal material budget. The University of Geneva and KEK have built four modules respectively with common components and similar procedures. Each site has performed single module tests and 4-module combined tests with local DC-DC converter power supplies and compared them for cross checking. Details of the module design and electrical performance are presented. The status of the 8-module installation in a realistic support structure is also reported.

Speaker: Yoichi Ikegami (KEK)

Paper http://iopscience.iop.org/1748-0221/5/12/C12056

Poster poster_ID135.pdf poster_ID135.ppt

145 Radiated Electromagnetic Emissions of DC-DC Converters - Measurements and Simulations

A new powering scheme is considered to be mandatory for the CMS tracker at SLHC. The baseline solution of CMS foresees the use of DC-DC converters, allowing to provide larger currents while reducing losses. An important component of most converters are inductors, which, however, tend to radiate the switching noise generated by the converter. The radiated emissions of several converters have been measured and simulated. In addition noise susceptibility measurements with radiated noise and present CMS hardware have been performed. A summary of the results will be presented.

Speaker: Mr Jan Sammet (RWTH Aachen University)

Paper http://iopscience.iop.org/1748-0221/5/12/C12055

Poster tweppPoster_final.pdf

146 Reliability and Performance Studies of DC-DC Conversion Powering Scheme for the CMS Pixel Tracker at SLHC

The upgrades of the Large Hadron Collider (LHC) introduce a significant challenge to the power distribution of the detectors. DC-DC conversion is the preferred powering scheme proposed to be integrated for the CMS tracker to deliver high input voltage levels and performing a step-down conversion nearby the detector modules. In this work, we investigate the integrity of power distribution and perform pixel performance analysis using the DC-DC conversion powering scheme. Tests are performed using the PSI46 pixel readout chips on a forward tracker panel module and the AMIS2 DC-DC converters developed at CERN. Reliability studies include the voltage drop measurements on the readout chips and the power supply noise generated from the converter. Performance studies include pixel noise and threshold dispersion results. Additionally, we describe SPICE-level converter and readout chip models for simulation that quantify the voltage drop and power supply noise on the system.

Speaker: Mr Alan Prosser (Fermilab)

Paper http://iopscience.iop.org/1748-0221/5/12/C12010

147 Response of a commercial 0.25 μm Thin-Film Silicon-on-Sapphire CMOS Technology to Total Ionizing Dose

The radiation response of a commercial 0.25 μm silicon-on-sapphire CMOS technology was characterized at the transistor and circuit levels utilizing standard or enclosed layout devices. Device-level characterization showed ΔVT of less than 170 mV and ΔILEAKAGE of less than 1 nA for nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit level was less than 5%, consistent with the small change in off-state transistor leakage current. The technology exhibits good characteristics for use in the electronics of the ATLAS experiment at the Large Hadron Collider.

Speaker: Michael King (Vanderbilt University)

Paper http://iopscience.iop.org/1748-0221/5/11/C11021

148 SPACIROC: Rad-Hard Front-End Readout chip for the JEM-EUSO telescope

SPACIROC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). This 64 channels readout ASIC offers photon counting capability and includes a charge to time (Q-to-T) converter. The main requirement for the photon counting is to obtain a 100% trigger efficiency starting from 1/3 p.e. with a 10 ns double pulse resolution. As for the Q-to-T converter, the chip needs to deliver a linear measurement for the input charges ranging from 10 p.e. to 300 p.e. Moreover, the ASIC was designed to achieve low power consumption (1mW/channel) and radiation tolerance, in compliance with the operating constraints imposed by the ISS. The current design of the ASIC was done in collaboration with RIKEN, Japan on behalf of the JEM-EUSO consortium. A prototype chip has been submitted for fabrication in March 2010 using AMS SiGe 0.35µm process.

Speaker: Mr Salleh Ahmad (LAL,Orsay - IN2P3)

Paper http://iopscience.iop.org/1748-0221/5/12/C12012/

Poster poster_spaciroc.pdf

149 Status of the Medipix MCP-HPD development

This paper describes the design of a high-speed, single-photon counting, hybrid photon detector. The detector consists of a vacuum tube, containing a micro channel plate and 4 CMOS pixel read out chips, sealed with a transparent optical input window with a photocathode. The described design utilizes currently available technologies, specifically the Timepix read out chips, and the Photonis Planacon MCP-PMT vacuum tubes. The aim of the project is to demonstrate the feasibility of 4-side buttable square hybrid photon tube with high fractional sensitive area. Presented here is the mechanical and thermal design of the prototype detector.

Speaker: Dr Timo Tick (CERN – PH department, 1211 Geneva 23 Switzerland, On behalf of all the members of the Medipix HPD team)

Paper http://iopscience.iop.org/1748-0221/5/12/C12020/

Poster Timo_Tick_TWEPP10_-poster.pdf

150 Study of the electronics architecture for the mechanical stabilization of the quadrupoles of the CLIC linear accelerator

To reach a sufficient luminosity, the transverse beam sizes and emittances in future linear particle accelerators should be reduced to the nanometer level. Mechanical stabilization of the quadrupole magnets is of the utmost importance for this. The piezo actuators used for this purpose can also be used to make fast incremental orientation adjustments with a nanometer resolution. The main requirements for the CLIC stabilization electronics is a robust, low noise, low delay, high accuracy and resolution, low band and radiation resistant feedback control loop. Due to the high number of controllers (about 4000) a cost optimization should also be made. Different architectures are evaluated for a magnet stabilization prototype, including the sensors type and configuration, partition between software and hardware for control algorithms, and optimization of the ADC/DAC converters. The controllers will be distributed along the 50 km long accelerator and a communication bus should allow external control. Furthermore, one might allow for an adaptive method to increase the S/N ratio of vibration measurements by combining seismometer measurements of adjacent magnets. Finally a list of open topics, the current limitations and the plans to overcome them will be presented.

Speaker: Mr Pablo Fernandez Carmona (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11014

Poster Poster_v2.pdf

151 Subnano Time to Digital Converter implemented in PARISROC_V2 for PMm² R&D program

PARISROC_V2 is a complete read out chip, in AMS SiGe 0.35µm technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and its belongs to an R&D program funded by the French national agency for research (ANR) called PMm²: “Innovative Electronics for photodetectors array used in High Energy Physics and Astroparticles”. The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a 10-bit Wilkinson ADC and a 24-bit counter. The time measurement is made by 2 complementary systems: a 24-bit gray counter (coarse time) with a step of 100ns, and a double ramp TDC (fine time) with a 10-bit resolution and a precision less than 1 ns. It is interesting to underline the fact that the double ramp generator is common to all channels. The poster presents the TDC architecture and the first fine time measurements.

Speaker: Mr Sebastien Drouet (Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11)

Paper http://iopscience.iop.org/1748-0221/6/01/C01014/

Poster Poster_TDC_ParisRoc_TWEPP10.pdf Poster_TDC_ParisRoc_TWEPP10.pptx

152 The electro-mechanical integration of the NA62 Giga Tracker time tagging pixel detector

The NA62 Giga Tracker is a low mass time tagging hybrid pixel detector operating in a particle rate of 800 MHz. It consists of three stations with a sensor size of 60 x 27 mm^2 containing 18000 pixels of the size 300 x 300 µm^2 each. The active area is connected to a matrix of 2 x 5 pixel ASICs, which time tags the arrival of the particles with a binning of 100 ps. The detector operates in vacuum at -20 to 0 degree C and the material budget per station is below 0.5% X0. Due to the high radiation environment of 2 x 10**14 1 MeV neutron equivalent cm-2/yr it is planned to exchange the detector modules regularly. The low material budget, cooling requirements and the request of an easy module access has driven the electro-mechanical integration of the Giga Tracker, which will be presented in this paper.

Speaker: Michel Morel (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12023/

Poster TWEPPMichelPoster.pdf

153 The Gigabit Link interface Board (GLIB), a flexible system for the evaluation and use of GBT-based optical links

The Gigabit Link Interface Board (GLIB) is an evaluation platform and an easy entry point for users of high speed optical links in high energy physics experiments. Its intended use ranges from optical link evaluation in the laboratory, to control triggering and data acquisition from remote modules in beam or irradiation tests. The GLIB is a double width Advanced Mezzanine Card (AMC) conceived to serve a small and simple system residing either inside a μTCA crate, or on a bench with an optional link to a PC. Each GLIB card can process data to/from four SFP+ transceiver modules, each operating at bi-directional data rates of up to 6.5Gbps since it is based on on a high-performance Virtex-6 FPGA with twenty 6.5Gbps transceivers. This performance matches comfortably the specifications of the GBT/Versatile Link project with its targeted data rate of 4.8Gbps. In its simplest form, one GLIB board thus interfaces with up to four GBT channels. When in a μTCA environment, it provides a Gigabit Ethernet link for the controller of the module as well as PCI Express 4x GEN2 for data readout. Alternatively, instead of PCI Express, it can provide low and fixed latency custom 1.6/3.2/6.4Gbps DAQ links based on the LHC clock frequency. When in stand-alone operation, the system can interface with a PC through a Gigabit Ethernet RJ45 socket and/or a PCIe 4x GEN2 adapter board. The GLIB I/O capability can be further enhanced with two FPGA Mezzanine Cards (FMC). Each FMC can carry up to 160 user-specific I/Os (that can be configured both as single-ended or differential pairs) as well as 2 differential clock inputs and 2 differential clock outputs. This gives users the flexibility to adapt the GLIB interface to their system, by for instance adding connectivity to the TTC network at the backend, or connecting to e-links at the frontend. Additionally, one of the two FMCs also provides four optional 6.5Gbps transceiver lines. This paper presents the architecture of the GLIB, its features as well as examples of its use in different setups. The variety of optical and electrical interfaces on the board coupled with its flexible firmware, mean that this board can be easily adapted for use on non-LHC applications. A first prototype of the GLIB is expected to be available in early 2011.

Speaker: Sophie Baron (CERN)

Paper http://iopscience.iop.org/1748-0221/5/11/C11007/

Poster poster.rev4.pdf

154 The Phase 1 Upgrade of the CMS Pixel Front-End Driver

The pixel detector of the CMS experiment at the LHC is read out by analog optical links, sending the data to 9U VME Front-End Driver (FED) boards located in the electronics cavern. There are plans for the phase 1 upgrade of the pixel detector (~2015) to add one more layer, while significantly cutting down the overall material budget. At the same time, the optical data transmission will be replaced by a serialized digital scheme. A plug-in board solution with a high-speed digital optical receiver has been developed for the Pixel FED readout boards and will be presented along with first tests of the future optical link.

Speaker: Markus Friedl (HEPHY Vienna)

Paper http://iopscience.iop.org/1748-0221/5/12/C12054/

Poster friedl_a0.pdf

155 The TOTEM T1 ReadOutCard motherboard

The TOTEM Read-Out Card (ROC) is the main component of the T1 forward telescope front-end electronic system. It is mounted in the “Local Detector region” of the T1 detector structure between the “On Detector Region” represented by the front-end hybrids and the “Counting Room”. The ROC main objectives are to acquire tracking data and trigger information from the T1 Cathode Strip Chamber (CSC) detectors. It handles up to 16 front-end hybrids for a total of 2048 detector signals. The ROC performs data conversion from electrical to optical format and transfer the data streams to the next level of the system over a fiber through a 0.8 Gbit/s Ethernet 8B/10B parallel-to-serial encoder. The trigger bits are transferred at a rate of LHC 40 MHz clock and synchronized with the global TOTEM trigger system through the LHC Bunch Crossing 0 (BC0) fast command. The ROC implements Slow Control modules which are able to receive, decode and distribute the LHC machine low jitter clock and fast commands. The ROC manages the control information to/from the front-end hybrids through 16 individual I2C channels. Slow control skip fault architecture for additional redundancy is also implemented. The ROC provides a spy mezzanine based on programmable FPGA and USB2.0 for laboratory and portable DAQ debugging system. The TOTEM Read-Out Card motherboard, its components and connectivity are presented in this paper.

Speaker: Dr Saverio Minutoli (INFN - Genova)

Paper http://iopscience.iop.org/1748-0221/5/12/C12052

Poster SM_PosterAachen2010.pdf

156 Upgrade of the CSC Muon Port Card at the CMS Experiment

The present Muon Port Card (MPC) provides sorting of incoming Level 1 Trigger primitives and optical transmission of three best ones to the Track Finder within the Cathode Strip Chamber CSC)sub-detector at the CMS experiment at CERN. The transmission system comprises 180 1.6Gbps links; it has been in operation since 2008. The proposed Super-LHC upgrade implies higher data volume to be transmitted through the trigger chain and more sophisticated trigger algorithms. We plan to upgrade the MPC boards within the next few years to accommodate these requirements. The paper presents the first results of simulation and prototyping with the focus on an enhancing the sorting algorithms and using of parallel 12-channel optical links and more powerful Virtex-5 FPGA.

Speaker: Mr Mikhail Matveev (Rice University)

Paper http://iopscience.iop.org/1748-0221/5/11/C11013/

Poster LECC2010_poster.pdf

157 Upgrade of the PreProcessor System for the ATLAS Level-1 Calorimeter Trigger

The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM)consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serializers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

Speaker: Andrei Khomich (Kirchhoff-Institut fuer Physik, Heidelberg University)

Paper http://iopscience.iop.org/1748-0221/5/12/C12047

Poster nmcm_poster.pdf

158 Use of Triple Modular Redundancy (TMR) technology in FPGAs for the reduction of faults due to radiation in the readout of the ATLAS Monitored Drift Tube (MDT) chambers

The Triple Modular Redundancy (TMR) technology allows protection of the functionality of FPGAs against single event upsets (SEUs). Each logic block is implemented three times with a 2-out-of-3 voter at the output. Thus, the correct logical value is available even if there is an upset bit in one location. We applied TMR to the configuration code of a Virtex-II-2000 FPGA, which serves as the on-chamber readout processor of the ATLAS MDTs. We describe the code implementation, results of performance measurements and discuss several limitations of the method. Finally, we present a supplementary technology called “scrubbing”. It permanently re-writes the configuration memory while the FPGA is operating, correcting upset configuration bits.

Speaker: Mr Markus Fras (Max-Planck-Institut fuer Physik)

Paper http://iopscience.iop.org/1748-0221/5/11/C11009

Poster TWEPP2010_XTMR_Poster_OO.pdf

18:30 Social Event : City tour and Conference dinner

Friday, 24 September

TOPICAL DAY: Performance of LHC detector and electronics under first beam conditions

Convener: Livio Mapelli (CERN)

159 Performance of ALICE detector and electronics under first beam conditions

ALICE (A Large Ion Collider Experiment) is a general purpose heavy-ion detector at the CERN LHC, addressing the physics of strongly interacting matter and the quark-gluon plasma in nucleus-nucleus collisions. ALICE has been recording physics data since the first proton-proton collisions at LHC as reference for the heavy-ion programme and to address physics topics for which it is complementary to the other LHC detectors. This talk will provide a description of the ALICE experiment as it is running to date. Global readout performance, subsystems performance, stability and reliability of instrumentation will be addressed. Selected topics related to tuning and calibration of the ALICE subsystems to ensure reliable triggering and data taking will be discussed

Speaker: Dr Gianluca Aglieri Rinella (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12008

Slides ALICE-Aglieri.pdf ALICE-Aglieri.pptx

160 Performance of ATLAS detector and electronics under first beam conditions

Since spring 2010 the LHC delivers proton-proton collisions at 3.5 TeV marking the start of its high-energy physics program. In this presentation we give an overview of the ATLAS detector during this period, with emphasis on the performance of the sub-detectors and their electronics. We cover operational aspects necessary for smooth, safe, and stable data taking, as well as discuss resolved and pending electronics issues.

Speaker: Thilo Pauly (CERN)

Paper http://iopscience.iop.org/1748-0221/5/12/C12011

Slides 2010.09.24.TP-TWEPP.pdf 2010.09.24.TP-TWEPP.ppt

161 Performance of the CMS Detector and Electronics During First LHC Beam Operation

The performance of the CMS detector during the first operation with beam from the LHC is reviewed. The talk will discuss the overall performance of the CMS detector with some emphasis on operational aspects related to electronics

Speaker: Prof. Anders Ryd (Cornell University)

Paper http://iopscience.iop.org/1748-0221/6/01/C01097

Slides 100924_TWEPP.pdf

162 Early Running Experience with the LHCb detector

The LHC 7TeV Physics programme started at the end of March 2010. This talk highlights the experiences of running the LHCb detector with early pp-collisions from the LHC. An overview of the operation of the detector with the first 100nb^-1 will be given, and the challenge of running the detector smoothly in the initial data taking stages. Focus will be given to the performance of the hardware and the interplay between LHCb and the machine. We highlight our successes, and report on the progress made in solving outstanding subdetector issues.

Speaker: Karol Hennessy (Department of Physics-Oliver Lodge Laboratory-University of Live)

Paper http://iopscience.iop.org/1748-0221/5/12/C12022

Slides karol-twepp.zip

10:20 Break

TOPICAL DAY: Performance of LHC detector and electronics under first beam conditions

Convener: Livio Mapelli (CERN)

163 The ATLAS Level-1 Central Trigger

The ATLAS Level-1 trigger system is responsible for reducing the anticipated LHC collision rate from 40 MHz to less than 100 kHz. This Level-1 selection identifies jets, electrons/photons and muons, with additional triggers for missing and total energy. These inputs are used by the Level-1 Central Trigger to form a Level-1 Accept decision. This decision, along with clock and summary information, is then passed into the higher levels of the trigger system and sub-detectors. Results from commissioning the Central Trigger with cosmic rays and its performance during the first collisions will be shown.

Speaker: Mark Stockton (CERN)

Paper http://iopscience.iop.org/1748-0221/6/01/C01075

Slides MarkStockton_AtlasLevel1CentralTrigger.pdf

164 CMS Regional Calorimeter Trigger performance in 7 TeV data taking

We report on the first operations of the CMS Regional Calorimeter Trigger (RCT) with collisions. Many first physics analyses at CMS have used calorimeter triggers. The RCT receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the Global Calorimeter Trigger (GCT) after processing. The RCT hardware consists of 1 clock distribution crate and 18 double-sided crates containing custom boards, ASICs, and backplanes. Details will be presented on the physics performance, operational response to beam conditions, data quality monitoring, response to input detector problems, synchronization with beam collisions and overall control during operations from the initial data period for CMS

Speaker: Dr Jonathan Z Efron (University of Wisconsin)

Slides Twepp2010.pdf Twepp2010.pptx

165 Performance of the ATLAS Transition Radiation Tracker read-out with cosmic rays and first high energy collisions at the LHC

The ATLAS Transition Radiation Tracker (TRT) is the outermost of the three sub-systems of the ATLAS Inner Detector containing close to 350,000 thin-wall drift tubes (straws) operated with a Xenon-based gas mixture. The characteristics of the TRT data acquisition are exemplified by the front end electronics. These consist of separate analog and digital ASICS, the ASDBLR and DTMROC. The eight-channel ASDBLR (Amplifier, Shaper, Discriminator and BaseLine Restorer) provides a three-level differential digital output for each channel for as long as the signal stays above programmable "low" and "high" thresholds (which are used primarily for tracking and particle identification, respectively). Two ASDBLR chips input into a single, sixteen-channel DTMROC (Digital Time Measurement and ReadOut Chip), which encodes the time over low (high) threshold in 3.125 ns (25 ns) time steps in a programmable depth pipeline awaiting a level 1 trigger. When a level 1 trigger is received, three bunch crossings worth of data (75 ns) are read out. The DTMROC also provides a "Fast-OR" signal of its inputs, which has been utilized to build a level 1 trigger for cosmic rays traversing the ATLAS Inner Detector. This has been extremely useful during the commissioning of ATLAS. With a jitter of less than 1 bunch crossing cycle (25 ns), it allowed to time-in other ATLAS sub-detectors and level 1 triggers. This talk will describe the TRT readout electronics and data acquisition, with emphasis on the experience gained during commissioning. The performance will be illustrated with the excellent results obtained with the TRT for cosmic rays as well as for the first high energy proton-proton collisions provided by the LHC.

Speaker: Mr Dominick Olivito (University of Pennsylvania)

Paper http://iopscience.iop.org/1748-0221/5/11/C11006

Slides olivito_TRT_TWEPP10.pdf

166 An LHCb general-purpose acquisition board for beam and background monitoring at the LHC

The acquisition board is used as a readout board for the LHCb beam pickups in order to continuously monitor the bunch intensities and the phase of the bunches of protons with respect to the LHC bunch clock, and as a high-speed and high-sensitivity readout system for a scintillator background monitor which records fast beam losses with time information. In this paper we will describe its conceptual design, the many fundamental functions and its performance. We will also show results from the beam commissioning during which the board provided important information to the LHC, and during the first period with collisions.

Speaker: Mr Federico Alessio (CERN)

Paper http://iopscience.iop.org/1748-0221/6/01/C01001

Slides 100924_TWEPP10_Alessio.pdf 100924_TWEPP10_Alessio.pptx

CLOSE OUT

Conveners: Prof. Lutz Feld (RWTH Aachen University), Philippe Farthouat (CERN)

167 CLOSE OUT

Slides Twepp-10-closing.pdf Twepp-10-closing.pptx

13:00 Lunch

Tutorial: Modern Methods and Languages for High Level Design and Verification (1)

Convener: Jorgen Christiansen (CERN)

168 Modern Methods and Languages for High Level Design and Verification (1)

15:30 Break

Tutorial: Modern Methods and Languages for High Level Design and Verification (2)

Convener: Jorgen Christiansen (CERN)

169 Modern Methods and Languages for High Level Design and Verification (2)