# 12th Workshop on Electronics for LHC and future Experiments

Europe/Zurich
Valencia, Spain

#### Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN
Description
The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users. The LHC experiments will remain a primary focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained.
Support
• Monday, September 25
• 2:00 PM 6:00 PM
Plenary session P1-Opening plenary
• 2:00 PM
Introduction by the Director of IFIC 30m
Speaker: Juan Antonio Fuster Verdú
• 2:30 PM
Particle and Astroparticle Physics in Spain 45m
Speaker: Antonio FERRER
• 3:15 PM
The LHC machine status, calibration run and commissioning plans 45m
The status of the ongoing LHC installation is described with attention given to the long straight sections around the experiments. An overview of the proposed commissioning schedule for 2007 and 2008 presented. This schedule includes a calibration run at the end of 2007 which aims to deliver collisions at 450 GeV beam energy. The details of this run and planned beam conditions are summarised. The full commissioning to 7 TeV will be a challenging exerecise and an overview of the plans for 2008 is also given. Finally, the beam related issues associated with the LHC upgrade are introduced.
Speaker: Mike LAMONT
• 4:00 PM
break 30m
• 4:30 PM
CMOS directions in industry 45m
The seminar addresses recent advances in CMOS technologies. Technological limits, device-related limits and fundamental physical limits linked to the diminished feature sizes and their impact on analog performance and digital integration potential are discussed. Progress is made in new semiconductor/dielectric materials and in band-gap engineering to overcome some of the unfavorable effects at the microscopic/quantum level. Overall system cost pressures call for improved fabrication yields, forcing new tightly-coupled system- architecture-circuit-device design techniques in a context of ever increasing parameter variability. A detailed account of current device architectures beyond 45nm including performance boosters will be presented together with their associated advantages and risk factors. New paradigms will be necessary to reduce the analog-digital divide. One possible approach is the use of long-time known sampling techniques for Analog and RF circuits, opening the way to fully integrated reconfigurable systems, a concept that has been around for many years, but that is regaining interest.
Speaker: Ernesto PEREA
• 5:15 PM
3D electronics 45m
Traditional integrated circuits consist of a single layer of transistors interconnected with multiple layers of metal wiring. Three-dimensional integrated circuits (3D-ICs) consist of two or more active circuit layers that are vertically stacked and interconnected at high density. In addition to reducing the wire length, 3-D interconnection of active devices offers the potential for radically new computer architectures, extremely dense memories, and advanced focal planes that utilize the inherent parallelism inherent in the 3D technology. In this talk we will present work at MIT Lincoln Laboratory over the last several years which targets new classes of focal planes which exploit the parallelism of dense vertical interconnection reaching to small pixel sizes.
Speaker: Vyshnavi SUNTHARALINGAM
• Tuesday, September 26
• 9:00 AM 10:55 AM
Plenary session P2-Plenary ILC & high reliability
• 9:00 AM
Detector and readout systems for the ILC 45m
The challenges of experimentation at the International Linear Collider are discussed and the different detector concepts designed to cope with those challenges presented. The differing concepts lead to various alternative technologies for the major ILC detector components. These are briefly presented and discussed.
Speaker: Tim Greenshaw (Liverpool)
• 9:45 AM
High Availability Electronics standards 45m
Availability modeling of the proposed International Linear Collider predicts unacceptably low uptime with current electronics systems designs. High Availability (HA) analysis is being used as a guideline for all major machine systems including sources, utilities, cryogenics, magnets, power supplies, instrumentation and controls. R&D teams are seeking to achieve total machine high availability with nominal impact on system cost. The focus of this paper is the investigation of commercial standard HA architectures and packaging for Accelerator Controls and Instrumentation. Application of HA design principles to power systems and detector instrumentation will also be discussed.
Speaker: RAY LARSEN (Stanford Linear Accelerator Center For the ILC High Availability Electronics R&D Effort)
• 10:30 AM
break 25m
• 10:55 AM 1:00 PM
Parallel Session A1-Readout, commissioning and integration 1
• 10:55 AM
Overview of LHCb electronics installation aspects 25m
The infrastructure for the electronics, such as cabling, mains power distribution, low and high voltage power supplies, detector safety system, grounding and its installation in the LHCb experimental cavern will be presented. In particular, choices and compromises that have been made for power distribution, racks, cables and cable ducts installation, grounding (EMC) and optical fiber link tests will be described.
Speaker: Vincent Bobillier (CERN)
• 11:20 AM
Testing, time alignment, calibration and monitoring features in the LHCb front-end electronics 25m
An overview of testing, time alignment, calibration and monitoring features in the front-end electronics of LHCb is given. General features for this are defined and examples are given of how this has been implemented in sub-detector specific front- end electronics.
Speaker: Jorgen Christiansen (CERN)
• 11:45 AM
The readout system for the LHCb Outer Tracker 25m
The LHCb Outer Tracker is composed of 55000 straw drift tubes. The requirements for the OT electronics is the precise (1ns) drift time measurement at 6% occupancy and 1MHz readout. Charge signals form the straw detector are amplified, shaped and discriminated by ATLAS ASDBLR chips. Drift-times are determined and stored in the OTIS TDC and output to a GOL serializer at L0 accept. Optical fibers carry the data 120m to the TELL1 acquisition board. The full readout chain performed well in an e- test beam.
Speaker: Dirk Wiedner (Physikalisches Institut Uni Heidelberg)
• 12:10 PM
The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter 25m
In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged particles and neutrals for the first level trigger. The complete system design is presented, describing its different functionalities implemented through three different cards and two ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such cabling, grounding, shielding and power distribution.
Speaker: David Gascon (D. ECM, Universitat de Barcelona)
• 12:35 PM
Front-end Electronics Test for the LHCb Muon Wire Chambers 25m
The document to be presented will describe the electronic scheme and procedures of a system implemented to test the Multi-Wired Proportional Chambers after front-end dressing for the LHCb Muon Detector and its results. Given a dressed chamber, this system is able to diagnose every channel based on front-end output drivers’ response and noise rate versus threshold analysis, in addition it evaluates if the noise rate at the experiment threshold region is within appropriate limits. The project has foreseen as well an electronic identification of every chamber and front-end board, and results archiving in a way to make it available to the Experiment Control System (ECS).
Speaker: Rafael Antunes Nobrega (INFN - Sez. Roma)
• 10:55 AM 1:00 PM
Parallel Session B1-Trigger session 1
• 10:55 AM
Integration of the CMS regional calorimeter Trigger hardware into the CMS level-1 Trigger 25m
The electronics for the Regional Calorimeter Trigger (RCT) of the Compact Muon Solenoid Experiment (CMS) have been produced and tested. The RCT hardware consists of 18 double-sided crates containing custom boards, ASICs, and backplanes. The RCT receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the CMS Global Calorimeter Trigger after processing. Before installation, integration tests were performed. Data was successfully received from the TPG electronics and read out with a RCT Jet Capture Card. These tests, other tests involving more trigger subsystems, their results, and the RCT installation will be described.
Speaker: Pamela Klabbers (University of Wisconsin)
• 11:20 AM
Revised CMS Global Calorimeter Trigger Hardware Design 25m
An alternative design for the CMS Global Calorimeter Trigger (GCT) is being implemented. The new design adheres to all the CMS specifications regarding interfaces and functional requirements of the trigger systems. The design is modular, compact, and utilizes proven components. Functionality has been partitioned to allow commissioning in stages corresponding to the different capabilities being made operational. The functional breakdown and hardware platform is presented and discussed. A related paper discusses the firmware required to implement the GCT functionality.
Speaker: Matt Stettler (CERN)
• 11:45 AM
The Drift Tube Track Finder Muon Trigger at the CMS Experiment 25m
The Compact Muon Solenoid (CMS) is a general purpose experiment designed to study proton-proton collisions at the Large Hadron Collider (LHC). At the LHC, proton beams will cross each other at a rate of 40 MHz, producing in average 20 p-p interactions. The CMS L1 Trigger must select interesting collisions at a rate smaller than 100 kHz. The Drift Tube Track Finder (DTTF) implements the CMS DT L1 Regional Muon Trigger. The DTTF motivation and design, its electronic implementation and the production status will be presented. Tools for configuration, data acquisition, and monitoring will be described. Performance at Beam Tests and at the 2006 Cosmic Challenge will be discussed. Finally, recent results on expected rates for single muon and dimuon triggers, and prospects for operation at the first year of the LHC will be reviewed.
Speaker: Jorge Fernandez De Troconiz (Universidad Autonoma de Madrid)
• 12:10 PM
An RPC-based Technical Trigger for the CMS Experiment 25m
In the CMS experiment, sub-detectors may send special trigger signals, called “Technical Triggers”, for special purposes like test and calibration during the off-beam periods. The Resistive Plate Chambers are part of the Muon Trigger System of the experiment, but might also be used to produce a cosmic muon trigger as Technical Trigger to be used during the Cosmic Challenge and the later running of CMS. The proposed implementation is based on the development of a new board, the RBC; the test results on prototypes and their performance during the Cosmic Challenge will be presented.
Speaker: Flavio Loddo (INFN Bari)
• 12:35 PM
Design and Test of the Off-Detector Electronics for the CMS Barrel Muon Trigger 25m
Drift Tubes chambers are used in the CMS barrel for tagging the passage of high Pt muons generated in a LHC event and for triggering the CMS data read out. The Sector Collector system synchronizes the track segments built by trigger modules on the chambers and deliver them to reconstruction processors (Track Finder, TF) that assemble full muon tracks. Then, the Muon Sorter has to select the best four candidates in the barrel and to filter fake muons generated by the TF system redundancy. The hardware implementations of the Sector Collector and Muon Sorter systems satisfy radiation, I/O and fast timing constraints using several FPGA technologies. The hardware was tested with custom facilities, integrated with other trigger subsystems, and operated in a beam test. Constraints, design, test and operation of the modules will be presented.
Speaker: Luigi Guiducci (Istituto Nazionale di Fisica Nucleare (INFN))
• 1:00 PM 2:15 PM
break and POSTER SESSION 1h 15m
• 2:15 PM 3:55 PM
Parallel Session A2-Readout, commissioning and integration 2
• 2:15 PM
Integration and Installation of the CMS Electronics system 25m
The electronics systems used to control, trigger, and acquire data from the four experiments at LHC are, for the field of High Energy Physics, of unprecedented level of complexity and sophistication. In the case of CMS, users are gaining access to the counting room (USC55) at a late stage with respect to the official LHC start-up date. Measures taken to reduce the time required between when the access is granted for installation and the experiment is ready for physics are presented along with the current status and plans.
Speaker: Magnus Hansen (CERN)
• 2:40 PM
Installation and Commissioning of the On-Detector Electronics for the CMS Electromagnetic Crystal Calorimeter 25m
The CMS electromagnetic calorimeter is composed of 76,000 PbWO_4 scintillating crystals. The scintillating light is captured by photo-detectors, amplified and digitized. The conversion is performed inside the detector volume and data are transported through optical fibers to the off-detector electronics. About 25,000 Printed Circuit Boards of 5 different types and 5,500 Gigabit-Optical-Links and fibers should be installed and tested. The integration of electronics, cooling system, mechanical supports, low and high voltage distribution, synchronization and controls are discussed. Each step of the assembly sequence is followed by extensive test and quality control. Installation, commissioning strategy and the achieved system performance results are presented.
Speaker: Cristina Biino (INFN - sezione di Torino)
• 3:05 PM
Performance of CMS ECAL Very Front End Electronics 25m
We report the results of tests of 12800 Very Front End (VFE) readout cards for the barrel of the CMS electromagnetic calorimeter. A thorough test sequence was applied to each card including power-on test, burn-in and final detailed calibration. The results show excellent uniformity of the VFE cards. For instance the analogue, digital and buffer currents have average values of 1.59, 0.43 and 0.144 A with RMS values of 0.01, 0.01 and 0.008 A, respectively. The relative gains vary about 1%. Only a few per mille of the cards were failing the power-on test. The results prove the very high quality of the VFE cards.
Speaker: Alessandro Nardulli (Eidgenössische Technische Hochschule, ETH, Zurich, Switzerland)
• 3:30 PM
FEC-CCS: A common Front-End Controller card for the CMS detector electronics. 25m
The FEC-CCS is a custom made 9U VME64x card for the Off-Detector electronics of the CMS detectors. Special effort has been invested in the design of the card in order to make it compatible with the operational requirements of multiple CMS sub- detectors namely the Tracker, the ECAL Crystals and ECAL Preshower, the PIXELs, the RPCs and the TOTEM. This paper describes the design architecture of the FEC-CCS card focusing on the special design features that enables the common usage by the CMS subsystems. Results from the integration period in the sub-systems and performance measurements will also be reported. The design of a custom made testbench for the production testing of the 150 cards produced will be presented and the attained yield will be reported.
Speaker: Kostas Kloukinas (CERN)
• 2:15 PM 3:55 PM
Parallel Session B2-Trigger session 2
• 2:15 PM
The Level-0 Decision Unit of LHCb experiment 25m
The Level-0 Decision Unit (L0DU) is the central part of the first trigger level of the LHCb detector. The L0DU receives information from the Calorimeter, Muon and Pile- Up sub-triggers at 40 MHz via 24 high speed optical fiber links running at 1.6 Gb/s. The L0DU performs simple physical algorithm to compute the decision in order to reduce the data flow down to 1 MHz for the next trigger level. The processing is implemented in FPGAs using a 40 MHz synchronous pipelined architecture. The algorithm can be easily configured with the Experiment Control System (ECS) without FPGA reprogramming. The L0DU is a 16 layer custom board.
Speaker: Julien Laubser (Laboratoire de physique Corpusculaire (LPC) de Clermont-Ferrand)
• 2:40 PM
The Level-0 muon trigger for the LHCb experiment 25m
The Level-0 muon trigger looks for straight tracks crossing the five muon stations of the muon detector and measures their transverse momentum. The tracking uses a road algorithm relying on the projectivity of the muon detector. The Level-0 muon trigger analyzes every LHC bunch crossing. It handles about 130 GBytes per second. It finds muon tracks for a bunch crossing in about one microsecond. The architecture is pipeline and massively parallel. The processor is based on high speed optical and copper links, custom backplane as well as on the Stratix GX family of FPGA.
Speaker: Jean-Pierre Cachemiche (CPPM IN2P3/CNRS)
• 3:05 PM
LHCb Calorimeter Trigger : Validation Board 25m
The Validation board participates in the electronic for triggering system of LHCb calorimeter detector. The board, designed in Annecy-le-vieux Laboratory (LAPP-France), has logic radiation tolerant components: programmable logic, LVDS deserializer, 1.6Gbits optic transmitter. The inputs come from Front-end board of 4 different detectors (Electromagnetic, Hadronic, PreShower, Scintillator-Pad) by backplane board or shielded twisted pair long cable. All inputs transmit serial data in LVDS level at 280MHz. The treatment is implemented in 2 large Actel FPGAs cadenced at 40MHz. The outputs go through an optic mezzanine driven a 12 Channels fibber ribbon.
Speaker: Cyril Drancourt (Laboratoire d'Annecy-le-Vieux de Physique des Particules (LAPP))
• 3:30 PM
Installation and Test of the ATLAS Muon Endcap Trigger Chamber Electronics 25m
For the detector commissioning planned in 2007, a sector assembly of the ATLAS muon endcap trigger chambers is progressed in CERN intensively. Final technical test for the electronics mounted on a sector must be accomplished at this stage. For systematic test of the electronics, we have developed a DAQ system on top of the ATLAS online software framework. The system is not dedicated only for this test, but can be used also as the front-end detector part of the overall ATLAS DAQ system. We presume the extension to the ATLAS final one from the presently developed DAQ system must not be hard if it is built up in the common software framework. In this presentation, we report installation of the electronics on the sector, development of the DAQ system and its validity check performed through the electronics test at the chamber assembly stage.
Speaker: Hiroshi Nomoto (ICEPP,Tokyo)
• 3:55 PM 4:20 PM
break and POSTER SESSION 25m
• 4:20 PM 6:25 PM
Parallel Session A3-Readout, commissioning and integration 3
• 4:20 PM
Recent Results on the Performance of the CMS Tracker Readout System 25m
The CMS Silicon Tracker is comprised of a complicated set of hardware and software components that have been thoroughly tested at CERN before final integration of the Tracker. A vertical slice of the full readout chain has been operated under near-final conditions. In the absence of the tracker front-end modules, simulated events have been created within the FED and used to test the readout reliability and efficiency of the final DAQ. The data are sent over the final SLink 64 bit links to the final FRL modules at rates in excess of 200 MBytes/s per FED depending on setup and conditions. The current tracker DAQ is fully based on the CMS communication and acquisition tool called XDAQ. This paper discusses setup and results of a vertical slice of the full Tracker final readout system. Simulated data is created with varying hit occupancy (1-20%) and trigger rates (<200KHz) and the resulting behaviour of the system is recorded. Data illustrating the performance of the system and data readout is presented.
Speaker: Jonathan Fulcher (Imperial College)
• 4:45 PM
Readout Electronics Tests and Integration of the ATLAS Semiconductor Tracker 25m
The SemiConductor Tracker (SCT) together with the pixel detector and the Transition Radiation Tracker (TRT) form the central tracking system of the ATLAS experiment at the LHC. It consists of single-sided microstrip silicon sensors, which are read out via binary ASICs based on the DMILL technology and the data are transmitted via optical fibres. After an overview of the SCT detector layout and tracking performance, the final-stage assembly in large-scale structures and the integration with the TRT is presented. The focus is on the electrical performance of the overall SCT detector system through the different integration stages, including the detector control and data acquisition system.
Speaker: Vasiliki Mitsou (Instituto de Fisica Corpuscular (IFIC) UV-CSIC)
• 5:10 PM
A Read-out Driver for Silicon Detectors in ATLAS 25m
I present an overview of a read-out driver (ROD) for silicon detectors in the ATLAS experiment at the Large Hadron Collider (LHC). Two silicon-based ATLAS tracking systems, referred to as the Pixel Detector and the Semiconductor Tracker (SCT), are controlled and read-out using a common 9U VME board. A hybrid design of Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs) has allowed the Silicon ROD to meet the challenges of format error-counting and event trapping without interfering in the construction and transmission of event fragments to the next level in the read-out system. Performance of the ROD during detector assembly, calibrations and cosmic-ray data-taking are also discussed.
Speaker: Trevor Vickey (Univ. of Wisconsin, Madison, Department of Physics)
• 5:35 PM
Long Term Testing of VeLo detector modules in Vacuum 25m
LHCb is the only dedicated $B$ physics experiment on the Large Hadron Collider (LHC) ring. It is an spectrometer whose vertex detector(VeLo) has been optimise for the reconstruction of vertices near the beam. This is achieved by placing the silicon strip detector modules inside the primary beam pipe. Hence they are expected to operate in vacuum (10$^{-6}$mbar) and withstand high levels of radiation. Long term testing under vacuum was performed on these modules as part of their quality assurance during the VeLo production. These included thermal cycling and monitoring its electronic performance. Results will be presented of the modules tested so far and the unique challenges of vacuum operation.
Speaker: Aldo Saavedra (Glasgow)
• 6:00 PM
Design and test of the final ALICE SDD CARLOS end ladder board 25m
The paper presents the design and test of the final prototype of the CARLOS end ladder board. This board is able to compress data coming from one Silicon Drift Detector (SDD) front-end electronics and to send them towards the data concentrator card CARLOSrx in counting room via a 800 MBit/s optical link. The board design faces several constraints, mainly size (54x49 mm) and radiation tolerance: for this reason the board contains several CERN developed ASICs. A test setup has been realized for selecting the good devices among the 500 cards already produced.
Speaker: Samuele Antinori (Department of Physics & INFN Bologna)
• 4:20 PM 6:25 PM
Parallel Session B3-Trigger session 3
• 4:20 PM
Commissioning of the ATLAS Level-1 Central Trigger 25m
The ATLAS Level-1 Central Trigger consists of the Central Trigger Processor (CTP) and the Muon to Central Trigger Processor Interface (MuCTPI). The CTP receives trigger information from the Level-1 Calorimeter Trigger system directly, and from the Level-1 Muon Trigger systems through the MuCTPI. It also receives timing signals from the LHC machine, and fans out the Level-1 Accept signal, together with additional timing and control signals, to all sub-detector systems. From them, it collects BUSY signals in order to throttle the Level-1 Accept generation. Upon Level-1 Accept, the trigger systems send Region-of-Interest information to the Level-2 Trigger system. The systems are in part already installed in the ATLAS underground counting rooms. We present their current status, both in hardware and software, and the different commissioning steps that have led to it. Particular emphasis is put on the integration of the Central Trigger with the Muon and Calorimeter Trigger systems, the Level-2 trigger, and the read-out part of the different sub-detectors. We describe what has already been achieved, what we have learnt, and the future steps we will take in order to arrive at a fully functioning system.
Speaker: Thilo Pauly (European Organization for Nuclear Research (CERN))
• 4:45 PM
The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface 25m
The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS Level-1 trigger receives data from the sector logic modules of the muon trigger at every bunch crossing and calculates the total multiplicity of muon candidates, which is then sent to the Central Trigger Processor (CTP) where the final Level-1 decision is taken. The MUCTPI system consists of a 9U VME crate with a special backplane and 18 custom designed modules. We focus on the design and implementation of the octant module (MIOCT). Each of the 16 MIOCT modules processes the muon candidates from 13 sectors of the muon trigger and forms the local muon candidate multiplicities for the trigger decision. It also resolves the overlaps between chambers in order to avoid double-counting of muon candidates that are detected in more than one sector. The handling of overlapping sectors is based on Look-Up-Tables (LUT) for maximum flexibility. The MIOCT also sends the information on the muon candidates over the custom backplane via the Readout Driver module to the Level-2 trigger and the DAQ systems when a level 1 accept is received. The design is based on state-of-the-art FPGA devices and special attention was paid to low-latency in the data transmission and processing.
Speaker: Stefan Haas (CERN)
• 5:10 PM
The ATLAS Barrel Level-1 Muon Trigger Calibration 25m
The ATLAS experiment uses a system of three concentric Resistive Plate Chambers detectors layers for the level-1 muon trigger in the air-core barrel toroid region. The trigger classifies muons within different programmable transverse momentum ranges, and tags the identified tracks with the corresponding bunch crossing number. The algorithm looks for hit coincidences within different detector layers inside the programmed geometrical road which defines the transverse momentum cut. The on-detector electronics providing the trigger and detector readout functionalities collects input signals coming from the RPC front-end. Because of the different time-of-flights and cables and optical fibers lengths, signals have to be adjusted in time in order to be correctly aligned before being processed. Programmable delay logics are provided in the trigger and readout system to allow for time adjustment, for hit signals as well as for LHC Timing, Trigger and Control signals. The trigger calibration provides the set of numbers used during electronics initialization for correctly aligning signals inside the trigger and readout system. The functionality scheme and the algorithm of the calibration are presented.
Speaker: Riccardo Vari (Istituto Nazionale di Fisica Nucleare (INFN))
• 5:35 PM
ATLAS TDAQ RoI Builder and the Level 2 Supervisor system 25m
The ATLAS High Level Trigger (HLT) uses information from the hardware based Level 1 Trigger system to guide the retrieval of information from the readout system. The Level 1 Trigger elements (jet, electromagnetic, muon candidate, etc.) determine Regions of Interest (RoIs) that seed further trigger decisions. This paper describes the device - the RoI Builder - that collects these data from the Level 1 Trigger and the Level 2 Supervisors (L2SV) Farm that makes these data available to the HLT. The status of the system design and the results of the tests and integration into ATLAS TDAQ system are presented.
Speaker: Yuri ERMOLINE (MSU)
• 6:00 PM
Setup, tests and results for the ATLAS TileCal Read Out Driver production 25m
The setup used in the production of the 38 TileCal Read Out Drivers (RODs) and the results are described. Firstly we will explain all the hardware and firmware changes done to the RODs in order to adapt them to the TileCal requirements. Then, we will describe the procedure to test the RODs and the obtained results.
Speaker: Alberto Valero (Instituto de Fisica Corpuscular (IFIC) UV-CSIC)
• Wednesday, September 27
• 9:00 AM 10:10 AM
Plenary Session P3-Optoelectronics
• 9:00 AM
Optoelectronic developments for remote-handled maintenance tasks in ITER 45m
Periodic maintenance operations during shut down of the future International Thermonuclear Experimental Reactor (ITER) will have to be performed in a severe nuclear environment, exposing operating tools inside the reactor vessel to temperatures ranging from 50°C to 200°C, with total doses that can reach MGy levels. Radiation tolerant remote-handling technology will therefore play a major role during these maintenance tasks. Connecting remotely operated actuators and sensors with the control room requires bulky and shielded umbilicals. Their management could be eased by applying radiation tolerant communication links with multiplexing capabilities, for which fibre-optic technology is considered as a potential EMI-free solution. We present the main results obtained at SCK•CEN over the past years towards the development of radiation tolerant fibre-optic communication links, including the individual optical components such as optical fibres and power couplers, laser diodes and photodetectors, as well as their associated electronic driver circuits.
Speaker: Marco VAN UFFELEN (SCK)
• 9:45 AM
State of the art technologies for front-end hybrids 25m
The front-end hybrids for solid state and gas detectors will be crucial components of the next generation detectors. Requirements such as high-density and high-speed interconnects, low mass, radiation resistance and high- current and high-power dissipation capabilities are examples of the challenges to be solved concurrently. Over the past ten years we have been working on these problems for a variety of projects. The technologies for front-end hybrids developed at CERN are presented and future possibilities such as embedding active and passive circuits are described. Comments are made concerning the ability to access these technologies for large scale production by industry.
Speaker: Rui de Oliveira (CERN)
• 10:10 AM 10:35 AM
break and POSTER SESSION 25m
• 10:35 AM 11:20 AM
Poster Sessions 45m
• 11:20 AM 1:00 PM
Parallel Session A4-Optical links
• 11:20 AM
Potential Upgrade of the CMS Tracker Analogue Readout Optical Links using Bandwidth Efficient Digital Modulation 25m
The potential application of advanced digital communication schemes in a future upgrade of the CMS Tracker readout optical links is currently being investigated at CERN. We show experimentally that multi-Gbit/s data rates are possible over the current 40 MSamples/s analogue optical links by employing techniques similar to those used in ADSL. The concept involves using digitally-modulated radio frequency (RF) sinusoidal carriers in order to make efficient use of the available bandwidth.
Speaker: Stefanos Dris (Imperial College and CERN)
• 11:45 AM
Integration of the CMS Tracker Optical Links 25m
Analogue and digital optical links developed at CERN are currently being integrated into the CMS Tracker in the magnet-test/cosmic challenge (MTCC), Tracker Integration Facility (TIF) and at the experiment site in Point 5. Similar activities with the same or very similar optical links are also underway for CMS ECAL as well as other CMS detector systems. Recent hardware developments include the dense, in-line optical patch-panels as well as back-end patch-panels. Quality assurance and quality control procedures have been developed and practiced, including the cabling and connection procedure, acceptance tests for the cabling and connections, and tests of final system performance, in particular the analogue optical link gain and dynamic range. A summary of the progress of the integration is given along with the results to date from the various acceptance and performance tests in the MTCC and TIF.
Speaker: Karl Aaron Gill (CERN)
• 12:10 PM
Radiation Tests of the ATLAS Inner Detector Opto-Electronic Readout System for SLHC 25m
The readout system of the ATLAS inner detector for SLHC will need to cope with ten time’s higher radiation doses than the current ATLAS inner detector readout system. It is an open question of whether the current opto-electronic readout system could be used at SLHC. We irradiated VCSEL and Si-Pin arrays at a 20 MeV neutron beam up to the levels expected at SLHC and monitored their performance during irradiation and annealing. We performed very low dose irradiations of SIMM fibres at a gamma source. The results of these irradiations are summarized.
Speaker: Cigdem Issever (University of Oxford)
• 12:35 PM
Bandwidth of Micro-Twisted Cables and Spliced SIMM/GRIN Fibers and Radiation Hardness of PIN/VCSEL Arrays 25m
We study the feasibility of fabricating an optical link for the SLHC ATLAS silicon tracker based on the curret pixel optical link architecture. The electrical signal between the current pixel modules and the optical modules is transmitted via micro-twisted cables. The optical signal between the optical modules and the data acquisition system is transmitted via rad-hard SIMM fibers spliced to rad-tolerant GRIN fibers. The link has several nice features. We will present the result of a study of the bandwidth of the link and an irradiation of PIN/VCSEL arrays with 24 GeV protons at CERN to SLHC dosages.
Speaker: Kock Kiam Gan (The Ohio State University)
• 11:20 AM 1:00 PM
Parallel Session B4-Trigger & DAQ session 1
• 11:20 AM
Recent developments on th ALICE central Trigger processor 20m
The ALICE Central Trigger Processor is designed to process signals from triggering detectors and send appropriate trigger signals and data to participating detectors. The ALICE system allows dynamic partitioning of the detector, past-future protection appropriate to each detector's electronics, and a number of different monitoring and diagnostic functions. The system has now been built, and consists of 6 6U VME boards with logic implemented on ALTERA CYCLONE FPGAs. In this paper the characteristics of the system are described and its performance in tests described. Tests related to the system integration will also be presented.
Speaker: Orlando Villalobos Baillie (University of Birmingham)
• 11:40 AM
Timing in the ALICE trigger system 20m
In this paper we discuss trigger signals synchronisation and trigger input alignment in the ALICE trigger system. The synchronisation procedure adjusts the phase of the input signals with respect to the local Bunch Crossing (BC) clock and, indirectly, with respect to the LHC bunch crossing time. Alignment assures that the trigger signals originating from the same bunch crossing reach the processor logic in the same clock cycle. It is achieved by delaying signals by an appropriate number of full clock periods. We discuss the procedure which will allow us to find alignment delays during the system configuration, and to monitor them during the data taking.
Speaker: Roman Lietava (University of Birmingham)
• 12:00 PM
The ALICE silicon pixel detector read-out electronics 20m
The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the ALICE inner tracker system. The SPD contains 10 million pixels organized in 120 detector modules (half staves) connected to the off-detector electronics via bidirectional optical links. The front-end data streams are processed in 20 readout modules (Router), based on FPGAs, each carrying three 2-channel link-receiver daughter cards. The processed data are sent to the ALICE-DAQ system on the ALICE detector link (DDL) for permanent storage. The SPD control, configuration and data monitoring are performed using the VME interface of the routers. This paper describes the detector readout, control and off-detector electronics.
Speaker: Marian Krivda (Institute of Experimental Physics, Kosice, Slovakia)
• 12:20 PM
The ALICE Silicon Pixel Detector Control system and online calibration tools 20m
The ALICE Silicon Pixel Detector (SPD) contains nearly 10^7 hybrid pixel cells. About 2000 parameters and ~50000 DACs must be controlled in real-time during the detector integration, commissioning and operation. Information on each channel is stored in a configuration database. Timing and data management are critical issues. An overview of the SPD detector control system is presented, focusing on front-end controls and the SPD calibration strategy. An outlook of future implementations is presented.
Speaker: Ivan Amos Cali (Universita degli Studi di Bari / CERN)
• 12:40 PM
The Level 0 Pixel Trigger System for the ALICE Silicon Pixel Detector 20m
The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted together with data on 120 optical links using the G-Link protocol. The Level 0 Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor within a latency of 800 ns. The system is modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms.
Speaker: Gianluca Aglieri Rinella (CERN European Organization for Nuclear Research, Geneva)
• 1:00 PM 2:15 PM
break 1h 15m
• 2:15 PM 3:55 PM
Parallel Session A5-DAQ and Optical technology
• 2:15 PM
A multi-channel optical plug-in module for gigabit data reception 25m
A plug-in module has been built for reception of optically transmitted data by gigabit applications. The optical receiving module is based on a 12-channel optical receiver and an FPGA with embedded deserializers. It is compatible with the G-Link and Gigabit Ethernet compliant serializer ASIC (GOL) used by many LHC systems. Due to its compact design, several of these modules could be plugged into VME readout systems. This module will be the principle element for both the CMS Preshower data concentrator card and the TOTEM front-end driver. The possible use of this module for the readout of the ALICE silicon pixel detector is also under examination.
Speaker: Paschalis Vichoudis (CERN)
• 2:40 PM
PCI Express Over Optical Links for Data Acquisition and Control 25m
PCI Express is a new I/O technology for desktop, mobile, server and communications platforms designed to allow increasing levels of computer system performance. The serial nature of its links and the packet based protocols allows an easy geographical decoupling of a peripheral device. We have investigated the possibility of using an optical physical layer for the PCI Express, and we have built a bus adapter which can bridge, through such a link, remote busses (> 100m) to a single host computer without even the need of a specialized driver, given the legacy PCI compatibility of the PCI Express hardware. This adapter has been made tolerant to harsh environmental conditions, like strong magnetic fields or radiation fluxes, as the data acquisition needs of high energy physics experiments often require.
Speaker: Andrea Triossi (Sez. INFN di Padova Italy)
• 3:05 PM
Status of the TTC upgrade 25m
The TTC (Timing, Trigger and Control) system broadcasts the timing signals from the LHC machine to the experiments. Once at the detector level, it integrates the trigger information and local synchronous commands with these signals, for transmission to several thousands of destinations. The equipment for this second part of the system is fully produced, but the main network between the machine and the experiments required to be upgraded to ensure its easy maintenance. The design work began at the end of 2005 The new modules will be tested during the summer 2006 and the structured test beam in September 2006. A status of this design work will be done, including the description of the main modules, the results of the tests done on the prototype and the plans for production and support of this system.
Speaker: Sophie BARON (CERN)
• 3:30 PM
On the development of the final optical multiplexer board prototype for the TileCal experiment 25m
This presentation aims to describe the architecture of the final optical multiplexer board (also known as preROD) for the TileCal experiment. The results of the first VME 6U prototype have led to the definition of the final block diagram and functionality of this prototype. Functional description of constituent blocks and the state of the work currently undergoing at the Departament of Electronic Engineering is presented. As no board is still produced, no results are presented but, nevertheless, design issues that has been taking into account as component placement and signal integrity issues will be detailed.
Speaker: Vicente Gonzalez Millan (Dep. Ingeniería Electrónica - Univ. Valencia)
• 2:15 PM 3:55 PM
Parallel Session B5-Power systems
• 2:15 PM
The CMS Tracker Power Supply System: the Quality Assurance test work results over 2000 power units. 25m
The CMS tracker Power Supply System is made out of 2000 power supply modules where LV and HV channels are grouped together. A dedicated quality assurance plan, using a complex, remoted controlled Test Fixture, has been developped in collaboration between INFN-Torino and CAEN spa to test each single channel during and after production. Details on the test procedure and results that have been obtained are given with emphasis on the expected performances during CMS operation.
Speaker: Marco Costa (University of Torino)
• 2:40 PM
Evaluation and testing of advanced low-voltage power supplies 25m
Following a process of proof-of-concept on the requirements for radiation and magnetic filed tolerant low-voltage power supplies to be used to power silicon detectors in LHC experiments, a common procurement action was undertaken by the experiments and PH-ESS group. The evaluation and testing of advanced COTS radiation and magnetic field tolerant low-voltage power supplies is described. An overview of the design principles of the power supplies is given together with the test methods used and results obtained.
Speaker: Bruno Allongue (CERN)
• 3:05 PM
: Distributed low voltage power supply system for front end electronics of the TRT detector in ATLAS experiment 25m
We present a low voltage power supply system which has to deliver to the front end electronics of the ATLAS TRT detector ca. 24 kW of electrical power over the distance of 40-50 m (which adds another 24 kW). The system has to operate in magnetic field and under radiation environment of the LHC experimental cavern. The system has ~ 3000 individual channels which are all monitored and controlled (voltage and current measurement). The hardware solutions are described as well as the system control software.
Speaker: Zbigniew Hajduk (Institute of Nuclear Physics PAN - Cracow, Poland and CERN Geneva)
• 3:30 PM
Electromagnetic Compatibility of a Low Voltage Power Supply for the ATLAS Tile Calorimeter Front-End Electronics 25m
The front end electronics of the ATLAS Tile Calorimeter is powered by DC/DC conveters that sit close it. The performance of the detector electronics is constrained by the conducted noise emissions of its power supply. A compatibility limit is defined for the system. The noise susceptibility of the front end electronics is evaluated, and different solutions to reduce the front end electronics noise are discussed and tested.
Speaker: Georges Blanchot (CERN)
• 3:55 PM 4:20 PM
break and POSTER SESSION 25m
• 4:20 PM 6:00 PM
Parallel Session A6-Optoelectronics Working Group
• 4:20 PM
SLHC Working Group 25m
• 4:20 PM 6:00 PM
Poster sessions
• 4:20 PM
"CMAD", a Full Custom ASIC, for the Upgrade of COMPASS RICH-1 25m
In this paper we present an 8 channel full-custom ASIC prototype, named "CMAD", designed for the readout of the RICH-I detector system of the COMPASS experiment at CERN. The task of the chip is amplifying the signals coming from fast multi-anode photomultipliers and comparing them against a threshold adjustable on-chip on a channel by channel basis. CMAD was developed using a 350nm commercial CMOS technology.
Speaker: Ozgur Cobanoglu (Univ. + INFN)
• 4:20 PM
A compact plug-in module for LHC-like trigger emulation 25m
A programmable random trigger emulation system has been built for use in high energy physics, nuclear physics or radiology experiments. The emulator is based on the generation of trigger time intervals using a true random bit generator. The system is able to work either as a stand alone trigger emulator or as a plug-in module for a trigger/readout system.
Speaker: Georgios Sidiropoulos (University of Ioannina)
• 4:20 PM
A high level modelling approach to design and manage 18 electronics configurations used for the ECAL’s endcaps hardware design 25m
The ECAL sub detector of the CMS experiment is composed of one barrel and two endcaps. The crystals of the endcaps are arranged on an X-Y grid. Mapping signal clusters on to the eta-phi coordinate system required for the trigger therefore presents a problem. The 48 channels Trigger Concentrator Card (TCC48) is designed to compute the trigger primitives of the different parts of each endcap sector. Each card has to support 18 electronics configurations. Based on FPGA devices, an architecture supporting all possible configurations in one design will be presented. An automated approach to extract all configurations for each trigger tower will be described in this contribution. It will also be shown how a high level model based on SystemC language is used to cover all modelling and simulation aspects.
Speakers: Emmanuel Vaumorin (PROSILOG), Thierry Romanteau (LLR Polytechnique)
• 4:20 PM
A Test Stand System for High-Energy Physics Applications 25m
The Front-End R&D group at Fermilab has been developing pixel hybridized modules and silicon strip detectors for the past decade for high-energy physics experiments. To accomplish this goal, one of the activities the group has been working on includes the development of a high-speed and high-bandwidth data acquisition and test system to characterize front-end electronics. In this paper, we present a general purpose PCI-based test stand system developed by the Front-End group at Fermilab to meet the stringent requirements of testing silicon strip and pixel detectors. The test stand is based on a platform that is flexible enough to be adapted to different types of front-end electronics. This system has been used to test the electrical performance of the electronics for different experiments such as BTeV, CDF, CMS, and Phenix. The paper presents the capabilities of the system and how it can be adapted to meet the testing requirements of different applications.
Speaker: Guilherme Cardoso (Fermi National Accelerator Laboratory)
• 4:20 PM
ATLAS Pixel Detector Timing Optimisation with the Back of Crate Card of the Optical Pixel Read out System 25m
The ATLAS detector is one of the LHC experiments going to start data taking in 2007. The innermost subdetector of ATLAS will be a pixel detector. It consists of 1744 pixel modules which are controlled and read out via optical signals. The off detector end of the optical link is the Back of Crate card which is performing the optical-electrical conversion and adopting the timing for the detector and the readout hardware. Studies to test the timing capabilities have been done during a combined test beam which will be presented. Additionally information about the production of this card and the optical link are given.
Speaker: Tobias Flick (Bergische Universitaet Wuppertal)
• 4:20 PM
Background for High Energy Space Instrumentation at ISS 25m
The aim of this paper is to present the preliminary background modelling results of the Miniature X-and Gamma-ray Sensor (MXGS) instrument in the Atmospheric-Space Interaction Monitor (ASIM). ASIM is an atmosphere event observatory with a wide energy range (from optical to gamma-ray) foreseen to be located at the external facility of the Columbus Module at the ISS in 2009. The model takes into account the most important background sources: cosmic protons and trapped particles in the Earth Geomagnetic Field. The preliminary results shown that MXGS will be able to distinguish between RHESSI TGF’s for at least 75% of observing time.
Speaker: Andres Russu (Astronomy and Space Science Group - ICMUV - University of Valencia)
• 4:20 PM
CMS ECAL Low Voltage system 25m
The final design of the low voltage power system of the CMS ECAL detector will be presented. The particular requirements of the ECAL on-detector electronics powering will be discussed and details of the W-IE-NE-R MARATON system design related to these features will be pointed out. All tests performed with the ECAL-specific version of the MARATON power supply units will be summarized. The units acceptance and burning-in procedure will be presented.
Speaker: Alexander Singovski (University of Minnesota & CERN)
• 4:20 PM
CMS ECAL optical cables testing 25m
CMS ECAL detector will require more than 400 dense multi-ribbon optical cables, made of single mode 9 micron quartz fibers, for the data, control and trigger data transfer between on-detector and off-detector electronics. Although all cables will be tested before installation, one cannot guarantee no single fiber damage during the mass cable pooling campaign at the underground area. Hence, all optical lines have to be tested after installation. The available industrial test systems will be reviewed and motivation for the special system design will be discussed. The two portable optical components testers designed for the CMS ECAL application will be presented.
Speaker: Alexander Singovski (University of Minnesota & CERN)
• 4:20 PM
Commissioning and calibration of the CMS micro-strip tracker 25m
The CMS micro-strip tracker data acquisition system is based on an analogue front-end ASIC, optical readout and an off-detector VME board that performs digitization, zero-suppression and data formatting before forwarding event fragments to the online event-building farm. Sophisticated “commissioning” procedures are required to optimally configure, calibrate and synchronize the 10M readout channels. The procedures are defined by data acquisition loops that configure and control the readout and local trigger systems, perform event building and data analysis. We present an overview of the commissioning procedures and results from the CMS Cosmic Challenge and large-scale system tests at the Tracker Integration Facility.
Speaker: Robert Bainbridge (Imperial College London)
• 4:20 PM
Data Acquisition and Management in the Calibration Processes of the CMS Barrel Muon Alignment System 25m
The CMS Barrel Muon Alignment System is composed of a series of elements - each of large quantity - to be calibrated individually and together after assembly. This requires an approach based on modular control and data acquisition hardware and software including data validation features during data taking. The measured data of all calibration steps (including full images) are stored in a database together with the final results obtained after the processing and evaluation of raw data. A dynamic WEB-based reporting tool makes it possible to follow the status of calibration and assembly, and provides an easy search for any data. In the paper this approach is shown on the example of the two main element groups.
Speaker: Géza Székely (Institue of Nuclear Research, ATOMKI, Debrecen, Hungary)
• 4:20 PM
Design and performance of a PASA for the FAST-TRD Detector of the CBM experiment at FAIR 25m
The Compressed Baryonic Matter (CBM) experiment is a dedicated heavy-ion experiment at the future accelerator Facility for Antiproton and Ion Research (FAIR), in Darmstadt. A Fast Transition Radiation detector will be part of this experiment. The high reaction rates up to 10^7 event s^-1 require electronics with fast shaping time. A preamplifier for the FAST-TRD detector has been developed in AMS 0.35 micron technology. The ASIC has an FWHM of 70ns and noise equivalent of 445 e for a detector capacitance of 10 pF with a noise slope of 12e/ pF, fulfilling all requirements. The chip has been produced in a MPW run and it has been tested. Simulation and measurement results agree very well. This prototype has been successfully used in a physic test beam at GSI (Darmstadt) in February 2006. A comparison of simulated and measured performance will be presented. In addition I will report on the status of the R&D project, namely a preamplifier-shaper in IBM 0. 13 micron technology that could be used for several detectors.
Speaker: Hans Kristian Soltveit (University Heidelberg Physikalisches institut)
• 4:20 PM
Development and Setup of a Prototype System of Distributed Analysis for ATLAS Tier-2 25m
The ATLAS experiment currently under construction at CERN's Large Hadron Collider presents data processing requirements of an unprecedented scale. ATLAS will accrue tens of petabytes of data per year, distributed around the world: the collaboration comprises more than 1800 physicists from 150 institutions in 34 countries. The Distributed Analysis (DA) system has the goal of enabling ATLAS physicists to perform analysis on distributed data using distributed computing resources. Both data and resources are widely distributed throughout the world at CERN and at ATLAS Tier-1 and Tier-2 centers. Since DA system is of strategic importance there is a large development activity going on in this area: the ATLAS production system has being evolving to support the analysis jobs which will have a seamless access to all ATLAS resource, as well as another activities that aim to support user analysis by submitting directly to the separate grid infrastructures (Panda at OSG, direct submission to LCG and Nordugrid). The test of DA functionality will be addressed in the final Service Challenge 4 (SC4), in which the system will exposed to the expected large number of final analysis users. The Spanish ATLAS Tier-2 facility formed by IFIC, IFAE and UAM groups, is participating in several aspects of the Distributed Analysis System. In support of the ATLAS DA activities the IFIC Tier-2 center has developed and deployed a local computational facility which comprises many service nodes, computational clusters and large scale disk and tape storage services. The resources contribute to a variety of activities such as the analysis center facility for the next SC4 in which the technical aspects of DA will be tested and evaluted. In this paper we describe the ATLAS DA as well as we present our experience with the deployment, maintenance and operation of the mencioned DA prototype from the whole ATLAS collaboration and from the framework of the Spanish Tier-2 users point of view.
Speaker: Farida Fassi (IFIC- Instituto de Fisica Corpuscular)
• 4:20 PM
Development and test results of a readout chip for the GERDA experiment 25m
The F-CSA104 is a low noise, fully integrated, four channel preamplifier produced in the CMOS 0.6um XFAB XC06 process, which has been developed for the GERDA experiment. Each channel contains a charge sensitive preamplifier (CSA) followed by a fast differential line driver for driving a 100 Ohm twisted pair cable over 10m. It has a measuring sensitivity of 5.8 mV/fC with an expected ENC of 220e- after 20us CR-(RC)4 filtering when connected to a 30pF load and operating at room temperature. Depending on pulse rate and noise requirements the preamplifier's feedback resistor may be adjusted in fine steps from 1 MOhm to 2.2 GOhm. F-CSA104 has been particularly designed to operate in liquid nitrogen (T = 77K/-196°C).
Speaker: Nigel Smale (Nuclear Physics Laboratory)
• 4:20 PM
Electronic Devices for Controlling the Very High Voltage in the ALICE TPC Detector 25m
The Time Projection Chamber (TPC) is the core of the ALICE experiment at CERN. The ALICE TPC is an 88m3 cylinder filled with gas and divided in two drift regions by the central electrode located at its axial centre. The drift field is generated by a 100kV power supply. The TPC Very High Voltage project covers the development of the control system for the power supply. This paper reports the project progress, introducing the control system architecture from the electronics up to the control level. All the electronic devices will be described, highlighting their communication issues, and the challenges in integrating these devices in a PLC-based control system.
Speaker: Marco Boccioli (European Organization for Nuclear Research (CERN))
• 4:20 PM
Evaluation of Data Transmission at 80MHz and 160MHz Over Backplane, Copper and Optical Links 25m
The results of data transmission tests over custom backplane, copper and optical links at a multiples of the LHC bunch clock frequency are presented. We have evaluated a parallel data transmission at 80MHz and 160MHz using the GTLP and LVDS standards as well as serial copper and optical links operating at 3.2Gbps.
Speaker: Mikhail Matveev (Rice University)
• 4:20 PM
Functional and linearity tester system for the LHC beam loss monitoring data acquisition card 25m
In the frame of the design and development of the beam loss monitoring (BLM) system for the Large Hadron Collider (LHC) a flexible tester has been developed to qualify and verify during design and production a data acquisition card. It permits to test completely the functionalities of the board as well as realizing analog input signal generation to the acquisition card. The system utilize two optical receivers, a Field Programmable Gate Array (FPGA), eights flexible current sources and a Universal Serial Bus (USB) to link it to a PC where a software written in LabWindows (National Instruments) runs. It includes an important part of the measurement processing developed for the BLM in the future LHC accelerator.
Speaker: Jonathan Emery (CERN)
• 4:20 PM
High-density backplanes – problems and solutions 20m
The challenges of producing high-performance and low-latency realtime systems for LHC have led many groups to design systems with higher channel density and greater interconnectivity between modules. Custom backplanes with 2mm Hard Metric connectors provide the high pin counts necessary for these systems, but also present new problems, including increased insertion and extraction forces, vulnerable and easily damaged pins, and other long-term maintenance issues. The ATLAS Level-1 calorimeter trigger processor presents a near “worst-case” example of such a system. The Jet/Et and em/hadron subsystems use a full-custom 21-slot 9U backplane fully populated with 2mm HM connectors with a total of 1148 signal and ground pins per module. In this paper we present our solutions for reducing insertion/extraction force, providing strain relief for hundreds of connected cables while maintaining accessibility, and maintaining and repairing the backplane over the lifetime of LHC.
Speaker: Sam Silverstein (Stockholm University)
• 4:20 PM
Ideas on DC-DC Converters for Delivery of Low Voltage and High Currents for the SLHC / ILC Detector Electronics in Magnetic field and Radiation environments. 25m
We are exploring various way of employing 48 volt DC-DC converters capable of running in high magnetic fields and /or radiation environments of the SLHC and ILC detectors. Tradeoffs with respect to voltage conversion ratios, currents deliverable, radiation, and magnetic field are explored.
Speaker: Satish Dhawan (Yale University)
• 4:20 PM
Implementation of the Control System for the LHCb Muon Detector 25m
The Muon Detector of LHCb will be equipped with about 1380 Multi-Wire Proportional Chambers. Within the Framework of the CERN Control System Project, using PVSS as the main tool, we are developing an instrument to manage such a system. Adjustment and monitoring of High and Low Voltage power supplies, on-line diagnostics and fine tuning of the Front-End read-out devices, data acquisition from the gas system and the monitoring of pressure and temperature of the experimental hall are being implemented. The system will also look after long term data archiving and alert handling. The Control System performance is currently under evaluation in a cosmic ray station. Built as a final quality control of the LHCb Multi-Wire Proportional Chambers, allowing acquisition of data from as many as 600 Front-End readout channels, the cosmic ray station is fully managed by means of a Control System prototype.
Speaker: Rafael Antunes Nobrega (Universita di Roma I "La Sapienza")
• 4:20 PM
Large scale production of the Multi-Chip Module of the ATLAS Level-1 Calorimeter Trigger 25m
The Pre-Processor Multi-Chip Module (PPrMCM) is the main processing block of the Pre-Processor System in the ATLAS Level-1 Calorimeter Trigger. The PPrMCM holds a dedicated signal-processing ASIC and a Phos4 timing-chip together with seven commercial dice mounted on the substrate. Those are four FADCs and three LVDS-serialisers. The PPrMCM holds the main functionality of the Pre-Proccessor System, namely the digitization, calibration and Bunch-Crossing-Identification of calorimeter signals. The production phases of the PPrMCMs (more than 3200) and test procedures for quality control at different stages of the production are presented.
Speaker: Pavel Weber (Kirchhoff-Institut fur Physik (KIP))
• 4:20 PM
Local Trigger Processor Interface Module 25m
The interface between the ATLAS Central Trigger Processor (CTP) and the sub- detectors read-out systems is done through the Local Trigger Processor modules. These modules allow each sub-system to either run in global mode when it gets the timing and trigger signals from the CTP or in local mode when it handles locally its trigger and timing signals. During the commissioning phase of the detector and for test purposes, it may be necessary to have several sub-detectors able to run locally with the same timing and trigger signals (e.g the calorimeters and the level-1 calorimeter). Although feasible with the current LTP modules, an extra interface module (LTPIM) has been designed in order to void the need for adhoc cabling. The LTPIM is a 6U VME64x module housing two Altera Cyclone FPGAs for VME interfacing and control. All inputs and outputs are configurable through VME accesses. Special care has been taken for handling possible long distance LVDS transmission using active equalizers. The timing of all signals can be adjusted by means of individually programmable delay circuits. The delay circuits, as well as the active equalizers, use an I2C comunication bus controlled by the control FPGA. A description of the module as well as test results will be presented.
Speaker: Diogo Nunes Caracinha (Faculdade de Ciencias)
• 4:20 PM
Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies 25m
Deep sub-micron CMOS technologies are widely used for the implementation of front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of signal and noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.
Speaker: Massimo Manghisoni (Università degli Studi di Bergamo)
• 4:20 PM
n-XYTER - A CMOS read-out ASIC for a new generation of high rate multichannel counting mode neutron detectors 25m
For a new generation of 2-D neutron detectors developed in the framework of the EU NMI3 project DETNI [8], the 128-channel frontend chip n-XYTER has been developed. To facilitate the reconstruction of single neutron incidence points, the chip has to provide a spatial coordinate (represented by the channel number), as well as time stamp and amplitude information to match the data of x- and y-coordinates. While the random nature of the input signals call for self-triggered operation of the chip, on-chip derandomisation and sparsification is required to exploit the enormous rate capability of these detectors (up to 10^5/s/channel). The chosen architecture implements a preamplifier driving two shapers with different time constants per channel. The faster shaper drives a single-pulse discriminator with subsequent time-walk compensation. The output of this circuit is used to latch a 14-bit time stamp with a 2ns resolution and to enable a peak detector circuit fed by the slower shaper branch. The analogue output of the peak detector as well as the time stamp are fed to a 4-stage FIFO for derandomisation. The readout of these FIFOs is accomplished by a token-ring based multiplexer working at 32MHz, which accounts for further derandomisation, sparsification and dynamic bandwidth distribution. The chip will be submitted for manufacturing in AMS's C35B4M3 0.35um CMOS technology in June 2006.
Speaker: Ulrich Trunk (Max-Planck-Institut f. Kernfphysik)
• 4:20 PM
Optical pattern generator board 25m
The GPL board is an optical pattern generator for the L0 Decision Unit (L0DU). Its design is based on three FPGAs in BGA package which can send 24*16bits @ 80 MHz via 24 optical fiber link running at 1.6 Gb/s. One FPGA is used for the control of the board, via USB or through L0DU, and two processing FPGAs are used to control the optical channel. Each processing FPGA controls twelve deserializers which send the data to an optical transceiver. The GPL board is a 16 layer custom board.
Speaker: Magali Magne (Laboratoire de Physique Corpusculaire de Clermont-Ferrand (LPC))
• 4:20 PM
Radiation Testing of electronic components and systems for the LHC experiments and machine : summary and future 25m
A statistical summary on 6 years radiation testing for the LHC machine and experiments will be presented. The data shows that radiation tolerance assurance to cumulative damage effects was taken into account as an engineering constraint in a rather early stage in the project. The issue of Single Event Errors was only recognized as major issue at a much later stage in the project and this resulted in a sharp increase in proton beam testing in dedicated facilities at Université Catholique de Louvain and the Paul Scherrer Institute. Presently, the requests for dedicated radiation testing are reducing because series produced electronic equipment is being installed in the LHC. However, the requests may well rise again when the R&D for radiation hard semiconductor devices for the LHC upgrade gets to full swing. The suitability of the presently used radiation facilities for this task will be assessed.
Speaker: Thijs Wijnands (CERN)
• 4:20 PM
Radiation tests for Slow Control ALICE TOF systems 25m
The read-out modules of the ALICE Time-of-flight (TOF) system will be hosted in custom VME crates near the apparatus in a moderately hostile environment. Commercially available options to provide remote VME connection to the crate have been considered to provide slow control functionalities. The main slow control channel will be implemented through an optical link based on the commercial cards A2818/V2718 from CAEN for front-end electronics configuration and monitoring purposes. An additional ethernet link to an ARM CPU running Linux will be available. Radiation tolerance test results for the critical components corresponding to the abovementioned choices will be presented, as well as estimates of the minimum time between failure while taking data. The results presented here can be used to estimate upset rates for specific applications of commercially available VME controller cards and Single Board Computer like the CAEN V2718 and A1500.
Speaker: Pietro Antonioli (INFN - sezione di Bologna)
• 4:20 PM
Radiation Tolerance Qualification Tests of the Final Source Interface Unit for the ALICE Experiment 25m
The ALICE Detector Data Link (DDL) is a high-speed optical link designed to interface the readout electronics of ALICE sub-detectors to the DAQ computers. The Source Interface Unit (SIU) of the DDL will operate in radiation environment. Tests showed that configuration loss of SRAM-based FPGA devices used on the prototype of DDL SIU card was not acceptable. We developed a new version of the SIU card using ACTEL ProASIC3 device based on flash memory technology. In order to detect bit errors that occur in the embedded user memory, we implemented a parity check logic in the FPGA device. The new SIU card has been extensively tested using neutron and proton irradiation to verify its radiation tolerance. In this paper we describe the methods and the results of these irradiation measurements.
Speaker: Ervin Denes (KFKI Research Institute for Particle and Nuclear Physics)
• 4:20 PM
Revised CMS Global Calorimeter Trigger Functionality & Algorithms 25m
A revised design of Global Calorimeter Trigger (GCT) has been implemented. The primary function of the GCT is to process the Regional Calorimeter Trigger (RCT) data and transmit a summary to the Global Trigger (GT) which computes the First Level Trigger Accept (L1A) decision. The GCT must also transmit a copy of the RCT and GCT data to the CMS DAQ. This paper presents an overview of the revised design, concentrating on the firmware structure and algorithms. A separate paper presented in this conference details the hardware design.
Speaker: Gregory Michiel Iles (European Organization for Nuclear Research (CERN))
• 4:20 PM
Setup for testing LHCb Inner Tracker ladders 25m
The Inner Tracker of the LHCb experiment is a silicon microstrip detector consisting of 336 detector modules with either one or two sensors. The module production is now underway and we present here the setup employed for module testing during the production. The setup is based in the same electronics that will e used in the final experiment. We perform burning and ageing tests with the help of a custom made Temperature Cycling Box controlled with LabVIEW under Windows. The DAQ is done in another pc running Linux. Here we integrate the different C/C++ libraries used to communicate to the LHCb Time and Fast Control system, Esperiment Control System, and Data Acquisition.
Speaker: Pablo Vazquez Regueiro (Universidad de Santiago de Compostela)
• 4:20 PM
Signal integrity analysis for the electronic design of printed circuit boards 25m
LHC detectors and future experiments will produce very large amount of data that will be transferred at multi-Gigabit speeds. At such PCB data rates, signal- integrity effects become important and traditional rules of thumb are no longer enough for the design and layout of the traces. Simulations for signal-integrity effects at board level provide a way to study and validate several scenarios before arriving at a set of optimized design rules prior to building the actual PCB. This article describes some of the available tools at CERN. Two case studies will be used to highlight the capabilities of these programs.
Speaker: Alexandra Dana Oltean Karlsson (Polytechnic Institute of Bucharest/CERN)
• 4:20 PM
Signal Integrity Studies at Optical Multiplexer Board for TileCal System 25m
The Optical Multiplexer Board is a card included in the TileCal Data Acquisition System; it is designed to receive two optical fibers with same data from front-end boards and decided which has correct data. Inside this card we have different transmission lines that need to be studied; signal integrity problems such as signal delay, reflection, distortion and coupling should be analyzed. This paper presents the results of the signal integrity studies at the Optical Multiplexer Board for TileCal System.
Speaker: Jose Torres Pais (Dept. Ingenieria Electronica-Universidad de Valencia)
• 4:20 PM
System tests and debugging using Python 25m
The CMS Global Calorimeter Trigger (GCT) control and test software is described. An object-oriented model of the GCT hardware, based on the CMS Hardware Access Library (HAL), was written in C++. The SWIG software interface generator was then used to produce a python interface to the model. This allows the hardware to be controlled from a python script or shell, providing a flexible environment for rapid development of hardware and firmware tests without requiring detailed knowledge of software.
Speaker: Jim Brooke (H.H. Wills Physics Laboratory)
• 4:20 PM
The CDF Run II Silicon Detector 25m
The CDF Run II Silicon detector is one of the largest operating Silicon detectors in high energy physics. It has 6m2 of Silicon sensors with 722,432 channels read out by 5456 chips. The Silicon detector allows precision tracking, vertexing and is used in the hardware displaced vertex trigger. The CDF silicon detector had a very challenging commissioning period of 18 months. However the detector has been operating reliably over the last 3 years and it has recorded more than 1fb-1 of data. There will be a brief review of detector commissioning, the effects of radiation damage and its impact on the CDF physics programme.
Speaker: Ankush Mitra (Institute of Physics, Academia Sinica, Taipei, Taiwan)
• 4:20 PM
The Gigabit Optical Transmitters for the LHCb Calorimeters 25m
This report presents the boards developed for the optical data transmission of the calorimeter system of the LHCb experiment and test results. We developed two types of transmission boards: the single-channel and the multi-channel ones. Multi- channel boards can be equipped with a variable number of transmitters, depending on the need, with a maximum allowed of 12 channels. Each optical channel allows transmitting 32 bit data at 40.08 MHz. The boards have been designed and built using radiation hard devices produced at CERN. The optical links have been qualified using the eye diagram and the BERT at 1.6Gbps.
Speaker: Lax Ignazio (INFN Bologna-LHCb)
• 4:20 PM
The high voltage distribution system for the RICH photon detectors at LHCb 25m
We present the High Voltage, HV, distribution system for the Hybrid Photon Detectors (HPDs) of RICH1 and RICH2, at LHCb (484 HPDs in total). The HVs ( -20 kV, -19.7 kV and -16.4 kV) are supplied by printed circuit boards specially developed to prevent electrostatic discharges and/or corona effects using the limited available volume of the HPD arrays. The circuits that will be presented allow for the splitting, distribution, protection and monitoring of the high voltages. Each board is covered with silicone rubber, which prevents electrostatic breakdown. The complete characterization of the boards will be shown against the main important parameters.
Speaker: Claudio Arnaboldi (Sezione di Milano dell'INFN and Dipartimento di Fisica dell'Università di Milano-Bicocca, P.za della Scienza 3, Milano I-20126, Italy)
• 4:20 PM
The Level-1 Global Trigger for the CMS Experiment at LHC 25m
The trigger of the CMS experiment consists of two stages: the first stage, or Level-1 Trigger is implemented in hardware processors while the second stage, or High-level Trigger is implemented in software running on a computer farm. The Level-1 Trigger has to deliver a trigger decision for each LHC bunch crossing, i.e. at a rate of 40 MHz. The Level-1 Global Trigger uses objects supplied by the calorimeter and muon trigger systems. Its decision is based not only on energy and momentum thresholds but also on complex event topology, making use of space, charge and quality information calculated by the Global Calorimeter and Global Muon Trigger electronics.
Speakers: Anton Taurok (Institut fuer Hochenergiephysik (HEPHY)), Manfred Jeitler (Institut fuer Hochenergiephysik (HEPHY))
• 4:20 PM
The LHC Beam Loss Monitoring System's Surface Building Instalation. 25m
The strategy for machine protection and quench prevention of the Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is presently based on the Beam Loss Monitoring (BLM) system. At each turn, there will be several thousands of data to record and process in order to decide if the beams should be permitted to continue circulating or their safe extraction is necessary. The BLM system can be sub-divided geographically to the tunnel and the surface building installations. In this paper the surface installation is explored, focusing not only to the parts used for the processing of the BLM data and the generation of the beam abort triggers, but also to the interconnections made with various other systems in order to provide the needed functionality.
Speaker: Christos Zamantzas (CERN)
• 4:20 PM
Time Resolution of a Few Nanoseconds in Silicon Strip Detectors Using the APV25 Chip 25m
The APV25 front-end chip for the CMS Silicon Tracker has a peaking time of 50ns, but confines the signal to a single clock period (=bunch crossing) with its internal deconvolution filter. This method requires a beam-synchronous clock and thus cannot be applied to a (quasi-) continuous beam. Nevertheless, using the multi-peak mode of the APV25, where 3 (or 6,9,12,...) consecutive shaper output samples are read out, the peak time can be reconstructed externally with high precision. Thus, off-time hits can be discarded which results in significant occupancy reduction. We will describe this method, results from beam tests and the intended implementation in an upgrade of the BELLE Silicon Vertex Detector.
Speaker: Markus Friedl (HEPHY Vienna)
• 4:20 PM
Total Dose and Single Event Effects in a 0.25 m Silicon-On-Sapphire CMOS Technology 25m
Silicon-On-Sapphire (SOS) CMOS technology has been attractive to radiation tolerant applications. The Sapphire substrate eliminates single-event latch-up (SEL) and reduces the possibility of single event upset (SEE), but the back-channel leakage current could cause problems to circuitry made in this technology. To better understand the radiation effects in this technology and evaluate its feasibility in applications such as Large Hadron Collider (LHC) experiments, we have developed a custom test chip containing various test structures of MOSFET devices and circuits using Peregrine Semiconductor’s 0.25m SOS CMOS technology. This paper presents the total ionization doze (TID) and SEE measurement result and characterization obtained through the chip.
Speaker: Ping Gui (Southern Methodist University)
• 4:20 PM
Unified C/VHDL Model Generation of FPGA-based LHCb VELO algorithms 25m
We show an alternative design approach for signal processing algorithms implemented on FPGAs. Instead of writing VHDL code for implementation, and maintaining a C-model for algorithm evaluation, we derive both models from one common source allowing generation of synthesizeable VHDL and cycle- and bit-accurate C-Code. We have tested our approach on the LHCb VELO pre-processing algorithms and demonstrate comparison of data processed both off-line and on-line using the two derived models.
Speaker: Manfred Muecke (CERN)
• 4:20 PM
Wafer test of the LHCb Outer Tracker TDC-Chip 25m
The OTIS-TDC is a 32 channel time to digital converter chip developed in Heidelberg for the LHCb Outer Tracker experiment. Designed in a 0,25 $\mu m$ CMOS process, it can measure times with a resolution better than 1\,ns. As the chip is directly mounted to its board, the test have to be performed on the wafer itself. As the testing period for 7\,000 chips was only three weeks, many test routines have been implemented on a FPGA. The tests are described and results presented on overall yield and performance.
Speaker: Jan Knopf (Ruprecht-Karls-Universitat Heidelberg)
• Thursday, September 28
• 9:00 AM 10:30 AM
Plenary Session P4-HEP electronic and ASIC trends
• 9:00 AM
3D Circuit Integration for High Energy Physics 45m
Industry is pursuing 3D integrated circuits to enhance circuit performance. The techniques and technologies being employed can be of benefit to the High Energy Physics community. There are two general approaches that can be followed: die to wafer bonding, and wafer to wafer bonding. Each has its own benefits. Both of these approaches are being investigated at Fermilab. The die to wafer bonding approach is being studied through the services of two different vendors using devices produced at Fermilab for a previous experiment. The wafer to wafer bonding approach is being pursued with one vendor using their 0.18 um SOI process. The capabilities of these two different approaches are presented through a brief description of devices that have been fabricated. Critical processes for 3D integration are described. Design of a 3D circuit in an SOI process for High Energy Physics is presented
Speaker: Ray YAREMA
• 9:45 AM
Technology Scaling and CMOS Analog Design 45m
Modern and future ultra-deep-submicron technologies make challenging the analog design especially when power consumption must match digital counterparts. The decrease of the supply voltage reduces the voltage headroom in analog circuits, the gate leakage current increases, the voltage gain decreases in planar bulk transistors, 1/f noise deteriorate when using new high- k gate dielectrics. The transistor and passive components mismatches give rise to large inaccuracies. Only some of these problems can be solved at the technology level; others require new circuit topologies and design techniques. The increased digital processing capability not only pushes the analog-digital interface toward more and more digital, thus limiting the analog design to very first interfaces and data converters, but also enables to use digital methods for the correction and digital assisted analog design. Several of the solutions currently proposed for analog pre-processing and data converter design are discussed in this paper.
Speaker: Franco MALOBERTI (University of Pavia)
• 10:30 AM 10:55 AM
break and POSTER SESSION 25m
• 10:55 AM 1:00 PM
Parallel Session A7-ASIC developments
• 10:55 AM
Silicon strip readout using Deep-Submicron Technologies 25m
For the years to come, Silicon strips detectors will be read using the smallest available integrated technologies for room, transparency, and power considerations. CMOS, Bipolar-CMOS and Silicon-Germanium are presently offered in deep-submicron (250 down to 90nm) at affordable cost through worldwide integrated circuits multiproject centers. As an example, a 180nm CMOS readout prototype chip has been designed and tested, and gave satisfactory results in terms of noise and power. Beam tests are under work, and prospectives in 130nm will be presented.
Speaker: Jean-Francois Genat (CNRS/IN2P3/LPNHE)
• 11:20 AM
Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13um CMOS technology. 25m
Abstract. Owing to a novel concept of the detection of the single electrons in gas, the GOSSIP chip will hold certain advantages over an ordinary silicon pixel readout chip. Of these, no need for silicon sensor at all, low detector parasitic capacitance and none of the bias current at the pixel are the attractive features to design a compact low-noise and low-power integrated front-end circuit. A prototype of the integrated circuit has been developed in the 0.13um CMOS technology. The prototype includes a few channels equipped with the preamplifier, the discriminator and the digital circuit to study the feasibility of the TDC-per-pixel concept. The measurements demonstrate very low input referred noise (70e RMS) in combination with a fast peaking time (≈40ns) and low analog power dissipation (2uW per channel for 1.2V supply). High frequency switching activity on the clock bus (up to 100MHz) in the close vicinity of the sensitive analog inputs does not cause noticeable extra noise.
Speaker: Vladimir Gromov (NIKHEF)
• 11:45 AM
Irradiation of 0.13um ATLAS pixel test chip 25m
We present the results of irradiation tests of a 0.13um test chip containing ATLAS pixel analog front end circuits and various types of memory cells. The irradiations were carried out at the LBNL 88” cyclotron with 50 MeV/c protons and 16 MeV/c light ions for SEU studies. The front end circuits perform well up to the highest dose achieved at the moment, which is 1E15 p/cm^2. The linear energy transfer (LET) thresholds have been measured for SEU in five different latch structures. We plan to increase the radiation dose to 1E16 p/cm^2.
Speakers: Maurice Garcia-Sciveres (Lawrence Berkeley National Lab), Robert Ely (Lawrence Berkeley National Lab)
• 12:10 PM
An Error-Correcting Line Code for a HEP Rad-Hard Multi-GigaBit Optical Link 25m
This paper presents an ASIC implementing the line encoding scheme to be used in the GBT system, a multi-gigabit optical link designed for use in future luminosity improvements of the LHC. A general overview of issues specific to optical links placed in radiation environments is given, and the required properties of the line encoding discussed. A scheme that preserves the DC- balance of the line and allows forward error correction is proposed. It is implemented through the concatenation of scrambling, Reed-Solomon error-correction and addition of an 8-bit DC-balanced header. The proposed scheme has been implemented in a fully digital chip fabricated in a 0.13um CMOS technology. Implementation details and test and simulation results are given.
Speaker: Giulia Papotti (CERN (PH-MIC) and Universita degli Studi di Parma)
• 12:35 PM
Development of a CMOS SOI pixel detector 25m
We are developing a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15um fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. Nine types of SOI TEG chips with a size of 2.5 x 2.5 mm^2 consisting of 20um pixels have been designed and manufactured. The I-V measurement, a laser light detection test and a circuit test prove that the TEG chips function properly. We present basic performance of the detector as well as the comparison with simulation results. We also report the radiation effects on the TEG chips.
Speaker: Hirokazu Ishino (Tokyo Institute of Technology)
• 10:55 AM 1:00 PM
Parallel Session B7-DAQ session
• 10:55 AM
Production Test Rig for the ATLAS Level-1 Calorimeter Trigger Digital Processors 25m
The Level-1 Calorimeter Trigger is a digital pipelined system, reducing the 40 MHz bunch-crossing rate down to 75 kHz. It consists of a Preprocessor , a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce electron/photon, tau, and jet trigger multiplicities, total and missing transverse energies, and Region-of-Interest (RoI) information. Data are read out to the data acquisition (DAQ) system to monitor the trigger by using readout driver modules (ROD). A dedicated backplane has been designed to cope with the demanding requirements of the system. A number of pre-production boards were manufactured in order to fully populate a crate and test the robustness of the design on a large scale. Dedicated test modules to emulate digitised calorimeter signals have been used. All modules, cables and backplanes on test are final versions for use at the LHC. This test rig represents up to one third of the Level-1 digital processor system. Real-time data between modules were processed and time-slice readout data was transferred to the ROD at a trigger rate up to 100 kHz. Intensive testing consisted of checking the readout data by comparing to hardware simulations of the trigger. Domains of validity of the boards were also measured and dedicated stressful data patterns were used to check the reliability of the system. Tests results have been successful and the Level-1 calorimeter trigger system is proceeding to full production.
Speaker: Gilles Mahout (The University of Birmingham)
• 11:20 AM
The Hardware of the ATLAS Pixel Detector Control System 20m
The innermost part of the ATLAS experiment will be a pixel detector, built around 1750 individual detector modules. To operate the modules, readout electronics and other detector components, a complex power supply and control system is necessary. The unique power, grounding and control requirements are described, along with the custom made components of our power and control systems. These include remotely programmable regulator stations, the power supply system for the optical transceivers, several monitoring units and the interlock system.
Speaker: Tobias Henss (Univerity of Wuppertal)
• 11:40 AM
Algorithms in the ROD DSP of the ATLAS hadronic Tile Calorimeter 20m
The hadronic Tile Calorimeter of ATLAS generates ~10000 digitized pulses of 10-bit samples spaced in time 25 ns. In order to read-out and process these data the Read Out Driver boards (RODs) are equipped with real time fixed-point Digital Signal Processors. The processed information is sent to the second level trigger. This paper explains the performance of an algorithm to reconstruct the amplitude of the pulse, which is proportional to the energy deposited in the calorimeter, and an algorithm to identify muons of low transverse momentum. Comparisons of simulated processing time and time measured in the laboratory are shown for both algorithms. We also compare the precision on the energy calculation with the precision obtained with other algorithms executed in floating-point processors. Efficiencies and fake rates of muon identifications are also shown in this paper.
Speaker: Belen Salvachua (IFIC (UV - CSIC))
• 12:00 PM
Low-power front-end for a Neutrino Underwater Telescope 20m
The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and designing a front-end electronics for the Optical Modules, which contain the telescope optical sensors, as a full-custom Very Large Scale Integration ASIC. The solution has a multitude of advantages. The most important are low power consumption and the preanalysis and suitable reduction of data to be transferred to the shore station for acquisition. A detailed description of the chosen architecture and the design principles of the blocks, that carry out the specialized function required by this architecture, will be given.
Speaker: Domenico Lo Presti (CATANIA UNIVERSITY - PHYSICS DEPARTMENT)
• 12:20 PM
New RPC front-end electronics for hades 20m
Time of flight detectors are used for both particle identification and triggering. RPC detectors are becoming widely used because their excellent TOF capabilities and reduced cost. The new ESTRELA Resistive Plate Chamber (RPC) detector, which is currently being installed in the HADES detector at Darmstadt GSI, will contain 1000 RPC modules, covering a total active area of 8 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8 layer Motherboard (MB) providing impedance matched paths for the output signals of each of the eight 4-channel Daughterboards (DB) to the TDC.
Speaker: Alejandro Gil (IFIC)
• 12:40 PM
Alibava : A portable readout system for silicon microstrip sensors 20m
A portable readout system for silicon microstrip sensors is currently being developed. This system uses a front-end readout chip, which was developed for the LHC experiments. The system will be used to investigate the main properties of this type of sensors and their future applications. The system is divided in two parts: a daughter board and a mother board. The first one is a small board which contains two readout chips and has fan-ins and sensor support to interface the sensors. The last one is intended to process the analogue data that comes from the readout chips and from external trigger signals, to control the whole system and to communicate with a PC via USB. The core of this board is a FPGA that controls the readout chips, a 10 bit ADC, an integrated TDC and an USB controller. This board also contains the analogue electronics to process the data that comes from the readout chips. There is also provision for an external trigger input (e.g. scintillator trigger) and a 'synchronised' trigger output for pulsing an external excitation source (e.g. laser system).
Speakers: Ricardo Marco-Hernández (Instituto de Física Corpuscular (IFIC), Universidad de Valencia-CSIC, Valencia, Spain.), Salvador Martí i García (Instituto de Física Corpuscular (IFIC), Universidad de Valencia-CSIC,Valencia, Spain.)
• 1:00 PM 2:00 PM
break and POSTER SESSION 1h
• 2:00 PM 5:30 PM
Plenary Session P5-LHC experiment electronic upgrades
• 2:00 PM
Speaker: Geoff HALL (Imperial College of London)
• 2:15 PM
Informal comments on SLHC machine issues 20m
Speaker: Andy BUTTERWORTH
• 2:35 PM
Charge pump DC to DC converter Inner Tracker Applications 25m
We present results from a capacitor charge pump DC- DC converter prototype using 0.35um HV-CMOS technology fabricated in April 2006. The purpose of this prototype is to test the switch technology both for achievable efficiency and for radiation tolerance. The IC of this test device contains only switches, with all clocks being externally supplied and driven and the capacitors also external. The configuration used is a 4 capacitor stack producing a nominal x4 input current multiplication factor. The goal for this type of device is to be of low enough mass and high enough radiation tolerance to be placed on individual modules in the innermost layers of the ATLAS detector. Irradiation results will be presented if available. A prototype test card for use with a silicon strip stave prototype is under development.
Speakers: Mauricio Garcia-Sciveres (Lawrence Berkeley National Lab), Robert Ely (Lawrence Berkeley National Lab)
• 3:00 PM
Power issues questions and discussion 30m
• 3:30 PM
break 25m
• 3:55 PM
The GBT Bi-directional Link and Data system 30m
Speaker: Paulo MOREIRA
• 4:25 PM
TTC upgrade questions and discussion 20m
• 4:45 PM
Future options for optical links 25m
Speaker: Francois VASEY (CERN)
• 5:30 PM 6:00 PM
Parallel Session A8-MicroElectronics Working Group
• Friday, September 29
• 9:00 AM 10:35 AM
Plenary Session P6- LHC Machine
• 9:00 AM
LHC machine RF issues and developments 45m
The main RF system of the LHC, which uses 400MHz superconducting cavities, will be used to capture, accelerate and store the injected beam. A separate transverse damper system using electrostatic deflectors will be used to damp transverse oscillations. The associated low-level RF (LLRF) equipment is responsible for fast control of the accelerating voltage and phase in the cavities, the phase and radial position of the beam, and the synchronization of beam transfers between SPS and LHC. The LLRF system combines high- frequency analogue components with digital signal processing using FPGAs and DSPs. The extensive use of digital technology allows not only to achieve the required performance and stability but also to provide full remote control and diagnostics facilities needed in a machine where most of the RF system is inaccessible during operation.
Speaker: Andy BUTTERWORTH
• 9:45 AM
The LHC beam loss monitoring system's data acquisition card 25m
The beam loss monitoring (BLM) system is one of the most important elements for the protection of the Large Hadron Collider (LHC). It aims to protect the superconducting magnets from quenches and the machine components from damages, caused by beam losses. The losses are measured with ionization chambers and secondary emission monitors at likely loss locations. About 4000 monitors will be placed along the LHC mounted at the outside of the cryostats. The detectors produce a current proportional to the impacting secondary particle flux. The acquisition cards are placed near the detectors and are exposed to particle irradiation. During the design process of the acquisition cards several irradiation tests have been carried out to verify the radiation tolerance of the chosen components. The large variations of the quench levels with the beam energy and the particle loss duration, require the acquisition and digitalisation of the detector currents over eight orders of magnitude. The high dynamic range is covered by a current to frequency converter (CFC), which measures currents between 10 pA and 1 mA. An additional ADC measures the output voltage of the CFC to improve the data acquisition cards resolution. The signals of eight detectors are digitalised on one acquisition card. The data, together with card status information, are transferred to the processing card via two optical links.
Speaker: Ewald Effinger (CERN)
• 10:10 AM
An on line radiation monitoring system for the LHC machine and experimental caverns 25m
Speaker: Thijs Wijnands (CERN)
• 10:35 AM 11:00 AM
break 25m
• 11:00 AM 12:55 PM
Plenary Session P7-Beam, SLHC & closeout
• 11:00 AM
Beam Phase and Intensity Monitor for the LHCb experiment 25m
The LHC RF clock is transmitted over kilometres of fibre to the experiments where it is distributed to thousands of front-end electronics boards. In order to ensure that the detector signals are sampled properly, its long-term stability with respect to the bunch arrival times must be monitored with a precision of <100ps. In addition it is important to monitor the LHC bunch structure and the trigger conditions by measuring the intensity of each bunch locally in the experiment. For this purpose a beam phase and intensity acquisition board (BPIM) is being developed for the Button Electrode Beam Pickups which will be installed on both sides of all the LHC interaction points. The board measures the two quantities per bunch, and processes and histograms the information in an onboard FPGA. The information is read-out by the Experiment Control System and directly fed to the LHCb Timing and Fast Control system.
Speaker: Richard Jacobsson (CERN)
• 11:25 AM
Proposal for a First Level Trigger using pixel detector for CMS at Super-LHC 25m
A proposal for a pixel based Level-1 trigger for the Super-LHC is presented. The trigger is based on fast track reconstruction using the full pixel granularity exploiting a readout which connects different layers in specific trigger towers. The trigger will implement the current CMS High Level Trigger functionality using dedicated ASIC and FPGA, in a novel concept of intelligent detector. A possible layout is discussed and implications on data links are evaluated. Finally the performances are shown.
Speaker: Fabrizio Palla (INFN)
• 11:50 AM
Stacked Tracking for CMS at Super-LHC 25m
We report on recent work on the design of a pixel detector for CMS at the Super-LHC. This work builds on previous studies on a tracking detector capable of providing track stubs to be used in the Level-1. We now focus on the use of two layers of tracking, each comprising stacks of pixel sensors with 20x50x10μm3 pitch (θxφxr) and separated by a few millimetres. Preliminary work on track reconstruction in Field Programmable Gate Arrays (FPGAs) is also presented.
Speaker: John Jones (Imperial College London)
• 12:15 PM
Close OUT 40m