TWEPP 2016 - Topical Workshop on Electronics for Particle Physics

26 Sept 2016, 09:00 → 30 Sept 2016, 19:00 Europe/Zurich

Tulla Lecture Hall (Building 11.40) (Karlsruhe Institute of Technology (KIT))

Alessandro (CERN) Marchioro (CERN), Jorgen (CERN) Christiansen (CERN), Marc (KIT) Weber (KIT - Karlsruhe Institute of Technology (DE)), Matthias (KIT) Balzer (KIT - Karlsruhe Institute of Technology (DE))

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

Official Web site for local information and registration

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

Organised by the Institute for Data Processing and Electronics (IPE) at Karlsruhe Institute of Technology (KIT) with support from CERN.

conference_venue.pdf

Monday, 26 September

Tutorial: Micro TCA.4

Convener: Matthias (KIT) Balzer (KIT - Karlsruhe Institute of Technology (DE))

1 MTCA.4 Basics - Introduction in xTCA

Speaker: Rüdiger Coelln (Pentair)

Schroff MTCA Tutorial KIT Karlsruhe.pdf

2 MTCA.4 Tutorial and Life Demo

Speakers: Heiko Körte (N.A.T.), Vollrath Dirksen (N.A.T.)

Vollrath_Dirksen.pdf

10:30 Coffee Break

3 PCIe and PCIe Hot Swap under Linux in MTCA systems

Speaker: Ludwig Petrosyan

L_Petrosyan.pdf

L_Petrosyan.pptx

4 High Performance Measurement Application in MTCA.4

Speaker: Frank Ludwig (DESY)

Frank_Ludwig.pdf

12:30 Registration / Lunch

Opening and Local Talks

Convener: Jorgen (CERN) Christiansen (CERN)

5 Opening

Speaker: Jorgen Christiansen (CERN)

TWEPP16-Opening.pdf

TWEPP16-Opening.pptx

6 Welcome from Local Organizers

Speakers: Marc Weber (KIT - Karlsruhe Institute of Technology (DE)), Matthias Balzer (KIT - Karlsruhe Institute of Technology (DE))

Matthias.pdf

Matthias.ppt

7 Welcome from KIT

Speaker: Oliver Kraft (KIT)

MrKraft.pdf

MrKraft.pptx

8 Particle Physics in Germany

In Germany nearly 30 universities and several research laboratories perform research in particle physics. This includes a strong theory community and the participation in a wide range of experiments, R&D projects, accelerator physics and computing. A strong focus is on the LHC physics programme. The talk will give an overview of the activities as well as the structure and perspective in this field in Germany.

Speaker: Christian Zeitniz (University of Wuppertal)

Zeitnitz.pdf

9 Highlights and Trends of Detector Instrumentation and Technology Development in Germany

Detector instrumentation and the development of the underlying technologies in Germany take place in a rather diverse landscape of institutions. This includes university groups, Helmholtz centres, Max Planck institutes, Fraunhofer institutes and others. With the creation of the Helmholtz programme "Matter and Technologies" the field of detector instrumentation in Germany has been strengthened further. The talk will summarize selected highlights of detector instrumentation in the broadest sense. Trends and future opportunities will be covered, and again the focus will be on less well-known examples

Speaker: Marc Weber (KIT - Karlsruhe Institute of Technology (DE))

Marc.pdf

Marc.pptx

16:05 Coffee Break

Local Talks

Convener: Marc (KIT) Weber (KIT - Karlsruhe Institute of Technology (DE))

10 Invisibility Cloaking of Metal Contacts on Solar Cells and LEDs

Within the last decade, the idea of invisibility cloaking has turned from Science Fiction to scientific reality. Here, we review the underlying principle based on coordinate transformations and demonstrate application in terms of making metallic contacts on solar cells, detectors, and light-emitting diodes invisible.

Speaker: Martin Wegener (KIT)

Wegener Vortrag KIT 26.9.2016.pdf

Wegener Vortrag KIT 26.9.2016.pptx

11 The KATRIN experiment - the most precise scale for neutrinos

The Karlsruhe Tritium (KATRIN) experiment is large-scale international project at KIT comprising about 120 scientists, engineers and students from 6 countries. Its scientific goal is to improve the sensitivity of current direct neutrino mass experiments by one order of magnitude down to neutrino masses of 0.2 eV, which is of key importance for astroparticle physics. This is achieved by combining a high-intensity molecular gaseous tritium source with a high-resolution electrostatic retarding spectrometer, which is read out by a segemented Si-Pin diode array. As only electrons close to the ß-decay endpoint energy of 18.6 keV carry information on the neutrino mass, KATRIN scans the spectral shape of decay electrons in a narrow region of a few eV below the endpoint.

The talk gives an overview of the measuring principle of KATRIN and the status of its central components, which are in the final stages of commissioning, and closes with an outlook to the upcoming first light measurements.

Speaker: Guido Drexlin (KIT)

Drexlin.pdf

12 The Accelerators of the FAIR Project

The FAIR Project at GSI Helmholtzzentrum für Schwerionenforschung in Darmstadt (GSI) will offer unique research capabilities with heavy ion and antiproton beams. The ambitious goals of the scientific communities require to extend the capabilities of the present accelerators at GSI which will be the injectors of the future facility and push the future accelerators to the technical limits. We will report on the status of the upgrade program of the present accelerators and the project status of the future FAIR facility

Speaker: Jens Stadlmann (GSI)

Jens_Stadlmann.pdf

Jens_Stadlmann.pptx

18:30 Welcome Reception

Tuesday, 27 September

Invited Talk: U-M Gomez, Bosch Sensortec GmbH

Convener: Marc (KIT) Weber (KIT - Karlsruhe Institute of Technology (DE))

13 MEMS Sensors: Enabler for the IoT

Consumer electronics focus on low cost, small size, low power consumption and overall system performance. This lead to combined multi-axis sensing structures, integrated power management schemes and sensor data fusion. Bosch is actively driving this evolution further with novel multiple sensors on one single chip which will become the key element for new IoT applications.

Speaker: Udo-Martin Gomez (Bosch Sensortec GmbH)

ASIC

Convener: Christophe De La Taille (OMEGA (FR))

14 Development of the ABCStar front-end chip for the ATLAS Silicon Strip Upgrade

The ATLAS experiment will use an all-silicon tracker in the Phase II upgrade for the HL-LHC collider at CERN. For the Silicon Strip detector of the ITk, a new readout chip ABCStar is under design to meet the new requirements of higher trigger rates and lower latency. We summarize the status of this work and present the new features of the chip.

Speaker: Weiguo Lu (Chinese Academy of Sciences (CN))

TWEPP2016_ABCStar.pdf

15 SALT Readout ASIC for Upstream Tracker in the Upgraded LHCb Experiment

SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. An 8-channel prototype were already tested and the full 128-channel version was submitted. The design and first tests of 128-channel version will be presented.

Speaker: Krzysztof Piotr Swientek (AGH University of Science and Technology (PL))

swientek_TWEEP_2016.pdf

Programmable Logic, design tools and methods

Convener: Magnus Hansen (CERN)

16 Using MaxCompiler for High Level Synthesis of Trigger Algorithms

Firmware for FPGA trigger applications at the CMS experiment is conventionally written using hardware description languages such as Verilog and VHDL. MaxCompiler is an alternative, Java based, tool for writing FPGA applications and removes some of the need for electronics expertise. This provides potential to lower the barrier for contribution to firmware design. An implementation of the jet and energy sum algorithms for the CMS Level 1 Trigger upgrade has been written using MaxCompiler to benchmark against the production VHDL implementation in terms of accuracy, latency, resource usage, and code size.

Speaker: Sioni Paris Summers (Imperial College Sci., Tech. & Med. (GB))

Sioni_Summers.pdf

17 Software and Firmware co-development using High-level Synthesis

Accelerating trigger applications on FPGAs (using VHDL/Verilog) in CMS experiments at LHC-CERN warrants consistency between each trigger firmware and its corresponding C++ model. This tedious and time consuming process of convergence is exacerbated during each upgrade study. High-level synthesis, with its promise of increased productivity and C++ design entry bridges this gap exceptionally well. This paper explores the “single source code” approach using Vivado-HLS tool for redeveloping the upgraded CMS Endcap Muon Level-1 Track finder (EMTF). Guidelines for tight latency control, optimal resource usage and compatibility with CMSSW are outlined in this paper.

Speaker: Nikhil Pratap Ghanathe (University of Florida (US))

TWEPP_Presentation_PRATAP.pdf

TWEPP_Presentation_PRATAP.pptx

10:40 Coffee Break

ASIC

Convener: Christophe De La Taille (OMEGA (FR))

18 First results of the front-end ASIC for the strip detector of the PANDA MVD

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. It will be composed of four barrels and six disks, instrumented with silicon hybrid pixel detectors and double-sided microstrip detectors.
PASTA (PAnda STrip ASIC) is the readout chip for strip sensors.
An overview of the chip, of its readout system and of the first results of its characterization will be presented.
Supported by BMBF, HIC4FAIR and JCHP.

Speaker: Tommaso Quagli (Justus-Liebig-Universitaet Giessen (DE))

talk-TWEPP-finalv1.pdf

19 A Prototype of a New Generation Readout ASIC in 65nm CMOS for Pixel Detectors at HL-LHC

This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64x64 matrix of 50x50$\mu m^2$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5 % at 3GHz/cm$^2$ pixel rate, 1MHz trigger with 12.5$\mu$sec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit, analog dead-time below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600Mrad.

Speaker: Andrea Paterno (Universita e INFN Torino (IT))

CHIPIX_TWEPP16.pdf

20 A synchronous analog very front-end in 65nm CMOS with local fast ToT encoding for pixel detectors at HL-LHC

This work describes the design, in 65nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC. Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to few hundreds MHz. Two small prototypes have been submitted and tested; a X-ray irradiation up to 600 Mrad has been performed. Detailed results in terms of gain, noise, ToT and threshold dispersion are presented. This design will be part of the CHIPIX65 demonstrator and of the RD53A chip.

Speaker: Ennio Monteil (Universita e INFN Torino (IT))

TWEPP_synchronous_FE_65nm_with_Fast_ToT_encoding.pdf

Power, grounding and shielding

Convener: Magnus Hansen (CERN)

21 Serial Powering Pixel Stave Prototype for the ATLAS ITk upgrade

A Serial Powering Stave Prototype has been developed using FE-I4 Quad Pixel Modules in order to investigate a Serial Powering scheme for ATLAS ITk Phase II Pixel upgrade.

The talk will explain the need for a new powering scheme which is different from the currently used parallel (direct) powering in order to power detector modules for the ATLAS ITk Phase II Pixel upgrade. The Serial Powering building blocks will be introduced and the full scale prototype will be described. Detailed investigations of the electrical performance including robustness against noise and power failures will be shown.

Speaker: Viacheslav Filimonov (Universitaet Bonn (DE))

TWEPP_Serial_power_stave_prototype_27-09-2016.pdf

22 Fabrication of the first 3D Vertical JFET at the IMB-CNM

A new vertical JFET technology, based on a 3D trenched design, has been developed at the IMB-CNM. Conceptually introduced in TWEPP 2015, these transistors are conceived to work as radhard switches in the HV powering scheme of the ATLAS ITk strip detectors. The first fabricated wafers have been fully characterized and the results are presented here. Device performance is very close to specifications and shows excellent agreement with simulations. Radiation tolerance is currently under study. No noticeable effect has been seen from gamma irradiations; the impact of neutron and proton irradiation will be discussed in the final contribution.

Speaker: Dr Pablo Fernández-Martínez (IMB-CNM, CSIC)

Pablo_Fernandez-Martinez.pdf

Pablo_Fernandez-Martinez.pptx

12:25 Lunch

Invited Talk: (L. Cattaneo, Microsemi)

Convener: Alex Kluge (CERN)

23 Microsemi radiation tolerant FPGAs

This presentation will provide an overview of key enabling technologies addressing the increasing demands for reduced size, weight, power consumption and enhanced signal processing throughput in next generation radiation tolerant systems, without sacrificing reliability.
RTG4 is Microsemi’s next generation FPGA family for radiation environments using a 65nm low-power
flash process, which is immune to changes in configuration due to radiation effects.
An overview of the features and performances of RTG4 FPGAs will be provided, as well as development software, EcoSystem solutions, devices and systems for prototyping.

Speaker: Luca Cattaneo (Microsemi)

InvitedSpeaker_Luca_Cattaneo.pdf

InvitedSpeaker_Luca_Cattaneo.pptx

ASIC

Convener: Alex Grillo (University of California,Santa Cruz (US))

24 IC-PIX28: Pixel Detectors Read-Out in Bulk-CMOS 28nm

ICPIX28 is the first 28nm bulk-CMOS readout frontend for High Energy Physics pixel detectors. It performs the conversion of the input charge into a voltage signal, hence detect the charge arrival time and amount of charge information through Time-over-Threshold signal. The front-end is composed by the cascade of a Charge Sensitive Preamplifier and a low-power switched-capacitor logic-inverter-based comparator. A single channel area occupancy is 0.07mm2. It operates at0.9V supply voltage and consumes 4.3µW at 46dB@SNR. 10mV/fC sensitivity at 0.05fC Equivalent Noise Charge demonstrates design efficiency.

Speaker: Federica Resta (University and INFN Milano Bicocca)

Federica_Resta.pdf

25 HEPS-BPIX, the hybrid pixel detector system for High Energy Photon Source in China

HEPS-BPIX is a dedicated hybrid pixel detector for the High Energy Photon Source in China. It works in the single photon counting mode, and each pixel chip contains an array of 10472 pixels with a pixel size of 150um150um. Based on the successful design of the chip, the detector module was assembled by bump bonding with 24 pixel chips and a single large sensor. Six detector modules were then mounted as the final prototype system, covering an area of 9cm10cm with 360k pixels. Experiment and calibration results are discussed in this paper.

Speaker: Wei Wei (IHEP, CAS, China)

HEPS-BPIX_WeiWei.ppt

26 Development of a monolithic pixel detector with SOI technology for ILC vertex detector

We have been developing a monolithic type pixel detector for the ILC vertex detector with 0.2 um fully depleted SOI CMOS process. We are aiming to achieve 3 um of a single point resolution that is required for the ILC with a 20 um x 20 um pixel. Beam test result of the first prototype sensor that an amplifier and an analog memory are implemented in each pixel is presented. Design of second prototype with the time stamp function to recognize the bunch crossing information is also reported.

Speaker: Miho Yamada (KEK, High Energy Accelerator Research Organization)

TWEPP_myamada_2016-0927_v2.pdf

Systems, Planning, installation, commissioning and running experience

Convener: Ferdinand Hahn (CERN)

27 KAPTURE-2 – A picosecond sampling system for individual THz pulses with high repetition rate

Coherent synchrotron radiation requires DAQ systems with picosecond resolution. The Karlsruhe Pulse Taking Ultra-fast Readout Electronics (KAPTURE) is a novel system for a continuous investigation of THz synchrotron radiation. It is capable to sample single THz pulses with sampling times down to 3 ps. To improve performance and flexibility a second version of KAPTURE has been developed. The new system reduces the sampling time to a picosecond and operates with pulse rates of up to 3.6 GHz. The design of KAPTURE - 2 and the first measurements will be presented.

Speaker: Michele Caselle (KIT - Karlsruhe Institute of Technology (DE))

TWEPP_2016_Caselle.pdf

28 Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16bit dynamic range, and the development of low-noise, low-power and high-bandwidth electronic components will be presentet, including ASIC developments towards radiation-tolerant low-noise pre-amplifiers, up to 14bit ADCs and low-power optical links with up to 10GB/s.

Speaker: Tiankuan Liu (Southern Methodist University (US))

LIU_TWEPP16.pdf

29 A flexible FPGA based QDC and TDC for the HADES and the CBM calorimeters

In this presentation the read-out scheme will be introduced. Laboratory measurements have been done to characterize and optimize the analog electronic scheme and the FPGA VHDL code. The adaption process to different detector pulse shapes will be also shown. The results obtained at beam tests at the MAMI accelerator in Mainz and the SPS at CERN will be presented.

Speaker: Adrian Rost (Technische Universität Darmstadt (DE))

Adrian_Rost.pdf

16:05 Coffee Break

POSTER: Session 1

Convener: Ken Wyllie (CERN)

30 Development of Clock-Data Recovery circuit, Serializer and CML Driver in 65nm CMOS for HL-LHC pixel readout chip

ATLAS and CMS are presently collaborating on a design of a pixel readout chip in 65nm CMOS technology to be used for the LHC Phase-II upgrade. This work presents a prototype containing part of the I/O interface of this readout chip. The clock-data recovery circuit recovers clock from 160 Mbps incoming data and produces 1.6 GHz clock to be used by serializer. Double data rate serializer combines 20 data streams into 3.2Gbps stream, which is send off-chip by a Current Mode Logic driver. Prototype description together with first measurement results will be presented.

Speaker: Piotr Rymaszewski (Universitaet Bonn (DE))

cdr_poster_twepp_2016.pdf

31 6-Bit Low Power Area Efficient SAR ADC for CBM MUCH ASIC

The paper describes a SAR ADC, elaborated for digitization the shaper signal of the read-out CBM MUCH ASIC. The MUCH ASIC was designed and prototyped by means of the 0.18 um CMOS process of UMC (Taiwan). Each channel of ASIC consist of a CSA, fast and slow shapers, discriminator, ADC and a digital peak detector. ADC has a power consumption of 1.5 mW at 50 Ms/s and an occupied area of 0.0162 mm$^2$ for using an ADC in a multichannel structure.

Speaker: Vitaly Shumikhin (NRNU MEPhI)

poster_twepp2016_ADC.pdf

32 Design of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

CMOS pixel sensors with notable depletion have been demonstrated to be feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, replacing the current passive sensors. A further step to exploit the potential of CMOS sensors is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. In this work, a monolithic CMOS pixel sensor, named MONOPIX-01, has been designed in the LFoundry 150 nm CMOS technology. The submission is foreseen in the middle of May 2016. Design and simulation results will be presented.

Speaker: Tianyang Wang (Universitaet Bonn (DE))

TWEPP 2016 LF-Monopix.pdf

33 Characterization of ALICE SAMPA ASIC Using Prototype GEM Detector for LHC Run3 and Beyond

The ALICE experiment at the LHC plans upgrade of its TPC, due to expected high Pb-Pb collision-rate after the shutdown of LHC in 2018. In the upgraded TPC, Gas Electron Multiplier (GEM) chambers and continuous readout system will replace MWPC chambers and conventional triggered readout. In the continuous readout, GEM signals will be processed using 32 channels of SAMPA ASIC (preamplifier and ADC). The first version of the SAMPA was delivered in 2014 and the production of final version is in progress. During the presentation, test results of the SAMPA coupled with GEM detector prototype will be reported.

Speaker: Ganesh Jagannath Tambave (University of Bergen (NO))

Poster_GT.pdf

34 Performance of CATIROC: ASIC for Smart Readout of Large Photomultiplier Arrays

CATIROC is an upgraded version of PARISROC2 designed to read huge photodetection areas for neutrinos experiments. This “System-on-Chip” is a very innovative concept as it sends out only relevant data by network to the central data storage turning the detector into a smart one. The ASIC integrates a self-triggering mode down to 50 fC which provides time measurement better than 1 ns and charge measurement up to 100 pC. Data are converted internally over 10 bits @160 MHz and read-out at 80 MHz.
The chip was produced in 2015; architecture and testbench measurements will be presented.

Speaker: Selma Conforti Di Lorenzo (OMEGA/IN2P3/CNRS/Ecole Polytechnique)

CATIROC_poster_TWEPP2016.pdf

35 Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications

This work presents the design and characterization of a SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications.
The prototype chip was designed and fabricated in the framework of the CHIPIX65 project and was completely characterized in the first quarter of 2016. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal integrity.
The full characterization of the driver and receiver will be discussed in the conference paper.

Speaker: Francesco De Canio (Universita e INFN, Pavia (IT))

36 Development of Radiation-Hard Bandgap Reference Circuit in CMOS 130 nm Technology

In particle physics experiments a stable sub-1-V reference voltage is needed in spite of harsh ionizing radiation conditions. After such radiation load the bandgap using standard p-n junction of bipolar transistor does not work properly. This is why several sub-1V voltage references based on DTMOS (dynamic threshold MOS) and ELTMOS (enclosed layout transistor MOS), using CMOS 130nm process were proposed. We present and compare post-layout simulations and the preliminary measurements of the developed devices, which show correct operation (<1mV bandgap stability, linear PTAT) in temperature range -20 to 100 degree.

Speaker: Marika Kuczynska (AGH University of Science and Technology (PL))

37 HVCMOS Sensors for the High Luminosity Upgrade of ATLAS Experiment: The Second Generation of Prototypes and their Electronic Blocks

HVCMOS sensors and capacitive coupled pixel detectors (CCPD) are seen as an option to the standard sensor technologies such as hybrid- or strip-detectors for several particle physics experiments, among others ATLAS. The latest important achievement of this development is the production of first reticle size HVCMOS sensor – H35DEMO - that can be readout either as a monolithic detector, with the readout electronics on the chip, or attached to an external readout chip in form of a CCPD. H35DEMO is currently being tested and the first results are very good.

Speaker: Mr Roberto Blanco (-)

TWEPP_2016_Poster_Blanco_Roberto.pdf

38 LDQ10P: A Compact Low-Power 4x10 Gb/s VCSEL Driver Array IC

Low-power and high-data-rate laser array driver is an important on-detector component of the Versatile Link for the high-luminosity LHC experiments. We report the design and implementation of a low-power and radiation-tolerant 4x10 Gb/s VCSEL Driver array IC (LDQ10P). The entire four-channel VCSEL driver consumes 130 mW and occupies a silicon area of 1900 µm × 1700 µm. By integrating four driver channels into a single chip, LDQ10P can be directly wire-bonded to the VCSEL array and is a suitable candidate for the Versatile Link.

Speaker: Mr Zhiyao ZENG (SOUTHERN METHODIST UNIVERSITY)

39 Readout Electronics for Silicon Micro-Strip Sensors

In the future ILC (International Large Detector), Silicon strip detectors will be used in the tracker to measure position and energy of the particles. A specific readout chip must be designed targeted to the accelerator operation and expected performance. A multichannel readout ASIC for Silicon microstrips in AMS 180nm technology has been fabricated. The main intended goals for this readout ASIC are low power, wide dynamic range, low noise and adaptability to different variety of silicon sensors. The details of the design to fulfil the requirements and the experimental results will be presented at the conference.

Speaker: Oscar Alonso Casanovas

oalonso_TWEPP2016.pdf

40 A New Readout Electronics for the LHCb Muon Detector Upgrade.

The 2018/2019 upgrade of LHCb Muon System foresees a 40 MHz readout scheme and requires the development of a new Off Detector Electronics (nODE) board that will be based on the nSYNC, a radiation tolerant custom ASIC developed in UMC 130 nm technology.
Each nODE board has 192 input channels processed by 4 nSYNCs. The nSYNC is equipped with fully digital TDCs and it implements all the required functionalities for the readout: bunch crossing alignment, data zero suppression, time measurements.
Optical interfaces, based on GBT and Versatile link components, are used to communicate with DAQ, TFC and ECS systems.

Speakers: Luigi Casu (Universita e INFN (IT)), Sandro Cadeddu (Universita e INFN (IT))

32_Poster.pdf

41 65nm Receiver with Decision Feedback Equalization for Radiation Hard Data Link at 5Gbps

We present work to develop a radiation-hard receiver ASIC in 65nm CMOS with Decision Feedback Equalization (DFE), which is a very efficient technique for compensating the distortions caused by cable losses. Achieving the best possible compensation is particularly important for HL-LHC tracking detectors because the readout cable mass is inversely related to the tolerated amount of distortion. This work makes use of link design tools from Berkeley Wireless Research Center to determine the DFE architecture and generate the receiver circuit. Results presented include S-parameter measurements for ATLAS prototype cables, comparative eye-diagrams and plans for receiver layouts.

Speaker: Veronica Wallangen (Stockholm University (SE))

42 A Fully Monolithic HV-CMOS Pixel Detector with a Time-to-Digital Converter for Nanosecond Time Measurements

The Time Over Threshold (TOT) is usually measured by counting the number of clock cycles that the output of the preamp is over the threshold but the time resolution obtained is limited by the clock frequency and power consumption. Future HEP experiments will require a time resolution of few nanoseconds so that new approaches are needed. This paper presents a circuit to measure the TOT with a Time-to-Digital Converter (TDC). The circuit is very compact, low power and used to readout a matrix of HV-CMOS pixels. The chip is designed with a 150nm process from LFoundry.

Speaker: Raimon Casanova Mohr (Universitat Autònoma de Barcelona (ES))

HVCMOS_TDC_CASANOVA.pdf

43 Development of 32-Channel System for Processing Asynchronous Data from the CBM GEM Detectors

The 32-channel system for processing asynchronous data from the GEM detectors is presented. It has been developed as part of ASIC intended for the muon chamber of the CBM experiment and allows to run up to 10 MHz channel rate.
The system provides the generation of data packages, consisting of the digital codes of signal amplitude, arrival time and channel number. Control and data exchange with host are provided by 2 serial interfaces: the slow I2C one and the high-speed (320 MHz) one.
The results of testing the main blocks, prototyped in UMC CMOS 180nm process are given.

Speaker: Eduard Atkin (NRNU MEPHI)

poster_twepp2016_DIGITAL.pdf

44 Simulation Environment Based on the Universal Verification Methodology

This talk presents Universal Verification Methodology (UVM) simulation environments of three recent ASIC and FPGA projects, which have successfully implemented a new Coverage-Driven Verification (CDV) work-flow in System Verilog: (1) the CLICpix2 65 nm CMOS hybrid pixel readout ASIC design; (2) the C3PD 180 nm High-Voltage-CMOS active sensor ASIC design; (3) the FPGA-based DAQ system of the CLICpix chip. Different interfaces (Ethernet, trigger and timing interface, I2C, SPI) which stimulate the devices under test are handled by complex and versatile testbenches enabling an exhaustive system verification and identification of difficult-to-track design flaws.

Speaker: Adrian Fiergolski (CERN)

Fiergolski_poster.pdf

45 SPIDR, a General-Purpose Readout System for Pixel ASICs

The SPIDR system is a flexible general-purpose readout platform for new and existing R&D ASIC projects, like Medipix3 and Timepix3. The system consists of an FPGA board, which reads out the ASIC and communicates via 1 and 10 Gigabit Ethernet to the back-end DAQ. It can be easily adapted and used as test-bed for other ASICs . The SPIDR system is currently used in various hybrid pixel detector projects such as the LHCb VeloPix. In this presentation we will highlight the architecture of the system and show a few successful applications of the SPIDR system.

Speaker: Bas Van Der Heijden (Nikhef National institute for subatomic physics (NL))

SPIDR_poster_TWEPP2016_FINAL.pdf

46 The ARAGORN Front-End - FPGA Based Implementation of a Time-to-Digital Converter

We present the ARAGORN front-end, a cost optimized, high-density Time-to-Digital Converter (TDC) platform. Four Xilinx Artix-7 FPGAs implement 384 TDC channels with a time resolution smaller than 200 ps on a single module. A fifth FPGA acts as data concentrator and master of an onboard SFP+ and a multi-channel optical transceiver slot to interconnect with up to seven boards though a star topology. This novel approach makes it possible to read out in total eight boards yielding 3072 input channels via a single optical fiber at a bandwidth of 6.6 Gb/s.

Speaker: Carl Schaffer (Albert-Ludwigs-Universitaet Freiburg (DE))

ARAGORN_Front-End_FPGA Based TDC.pdf

47 Single Event Effects Mitigation with TMRG Tool

Single Event Effects (SEE) are a major concern for integrated circuits exposed
to radiation. There have been several techniques proposed in order to protect
the circuits against radiation induced upsets (e.g. Triple Modular Redundancy).
The purpose of the TMRG tool is to automatize the process of triplicating
digital circuits freeing the designer from introducing manually the TMR code at
the implementation stage. It helps to ensure that triplicated logic is
maintained through the design process. Finally, the tool streamlines the process
of introducing SEU and SET in gate level simulations for final verification.

Speaker: Szymon Kulis (CERN)

tmrg_kulis.pdf

48 Versatile ASIC and Protocol Tester for STS/MUCH-XYTER2 in CBM Experiment

The STS/MUCH-XYTER2 is the new front-end ASIC for the STS and MUCH detectors in the CBM experiment. It uses an innovative protocol ensuring reliable synchronization of the communication link between the controller and the ASIC, transmission of time deterministic commands to the ASIC and efficient readout within a GBT-based data acquisition structure. The paper describes the FPGA-based tester platform for in-hardware functional verification of the digital part of the chip and the protocol before the ASIC is taped-out. The applied methodology may be useful for verification of other ASIC-based designs.

Speaker: Dr Wojciech Marek Zabolotny (Warsaw University of Technology, Institute of Electronic Systems (PL))

poster_CBM_tester.pdf

49 Flex Based Data and Power Transmission for the ATLAS Pixel Upgrade

The replacement of the whole ATLAS inner detector is foreseen for 2023/2024. The requirements of the data transmission rates for the upgraded pixel detector will be particularly difficult to meet as the projected transmission rates per chip are 5 GBit per second for each readout chip at the inner-most radius. Results from a first prototype (intended for the Alpine layout) of a flex based solution where data, power and bias voltages are transmitted through a common stave flex will be presented.

Speaker: Andre Rummler (Centre National de la Recherche Scientifique (FR))

50 A System-Level Model for High-Speed, Radiation-Hard Optical Links in HEP Experiments Based on Silicon Mach-Zehnder Modulators

Silicon Mach-Zehnder modulators that are resistant to a total ionizing dose of 1MGy have recently been demonstrated. Such devices could potentially be installed close to the interaction points in future LHC experiments. Because they require an external continuous wave light source, radiation-hard optical links based on Mach-Zehnder modulators will need to have a different system design when compared to existing VCSEL-based optical links. A first model for such a system is presented, including estimates for the optical power budget, the electrical power dissipation and the architecture of the proposed system.

Speaker: Marcel Zeiler (CERN)

TWEPP2016-Poster-V7.pdf

51 Development of a Rest Gas Ionisation Profile Monitor for the CERN Proton Synchrotron Based on a Timepix3 Pixel Detector

A fast non-destructive transverse profile monitor, named PS Beam Gas Ionization monitor (PS- BGI), is under development at CERN for the Proton Synchrotron (PS). This monitor infers the beam profile from the transverse distribution of electrons created by the ionisation of rest gas molecules by the high energy beam particles. The distribution is measured by accelerating the electrons onto a Timepix3 based imaging detector. This detector consist of hybrid pixel detector assemblies mounted on a ceramic printed circuit board and flexible printed cable which have been developed specifically for operation in an ultra high vacuum environment.

Speaker: Swann Levasseur (University of London (GB))

TWEPP_POSTER.pdf

52 HDI Flexible Front-End Hybrid Prototype for the PS Module of the CMS Tracker Upgrade

The CMS tracker upgrade for the HL-LHC relies on different module types, depending on the position of the respective module. They are built with HDI flexible circuits that are wire bonded to silicon strip sensors. The front-end hybrids will contain several flip-chip bonded readout ASICs that are still under development. Mock-up prototypes are used to qualify the advanced flexible circuit technology and the parameters of the hybrids. This paper presents the PS mock-up hybrid in terms of testing, interconnection, fold-over, thermal properties and layout feasibility. Plans for connectivity testing and simulation results are described.

Speaker: Mark Istvan Kovacs (CERN)

PS-MCK_A_hdi_flexible_prototype_for_the_PS_module_V1_6.pdf

53 Properties of Thin Polyurethane Wire Bond Coatings after Irradiation

Thin polyurethane (PU) coatings for aluminum wedge wire bonds are proposed to protect the ATLAS Inner Tracker upgrade from condensation-induced corrosion and oscillations from periodic Lorentz forces. Coating robustness after exposure to an HL-LHC lifetime dose is being evaluated. Mechanical properties of irradiated samples are tested at room temperature and -20C. Irradiated samples are thermal-cycled to test for radiation-induced intolerance to thermal expansion.

Speaker: Joseph Michael Izen (University of Texas at Dallas (US))

TWEPP 2016 PU Wire Bond A0 Poster.pdf

54 Characterization of Radiation Effects in 65nm Digital Circuits with the DRAD Digital Radiation Test Chip

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (< 1GRad) and Single Event Upset (SEU) on digital logic gates in a 65nm CMOS technology. Nine different versions of standard cell libraries are explored in this chip, basically differing in the device dimensions, Vt flavor and layout of the device.
Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated structure based on a shift register is designed for each library.
First irradiation results will be presented.

Speaker: Luis Miguel Jara Casas (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)

DRAD_TWEPP2016_poster_V2.0_finalVersion.pdf

55 Component Qualification for the Mu2E Calorimeter Wafeform Digitizer

The Mu2e experiment at Fermilab searches for the muon conversion to electron in the Coulomb field of a nucleus. The detector is composed of a straw tube tracker and an CsI crystals electromagnetic calorimeter housed in a superconducting solenoid.
The digitizing electronics will be located inside the magnet cryostat and will be operated in vacuum.
The harsh experimental conditions, with the presence of a high neutron flux, ionizing dose and magnetic field, make the design challenging and all the components must be individually tested and qualified.
The experimental results of the qualification tests are described.

Speaker: Franco Spinella (INFN (IT))

56 The Versatile Link Demonstrator Board (VLDB)

The Versatile Link Demonstrator Board (VLDB) is the evaluation kit for the Radiation Hard Optical Link ecosystem, which provides a 4.8 Gbps data transfer link for communication between front-end (FE) and back-end (BE) of the experiments. It gathers the Versatile Link main radiation hard custom ASICs: GBTx, GBT-SCA and VTRx/VTTx plus the FeastMP, a radiation hard in-house designed DCDC.

This board is the first design allowing system-level tests of the Link with a complete interconnection of the constitutive components, allowing DAQ, control and monitoring of FE devices with the GBTx – SCA pair.

Speaker: Raul Martin Lesma (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)

Poster_TWEPP2016_Raul_Sophie.pdf

57 The MuPix Telescope – A Thin, High Rate Particle Tracking Telescope

The MuPix Telescope is a particle tracking telescope, optimized for low momentum particles and high rates. It was build to test and integrate the novel High-Voltage MonolithicActivePixelSensors (“HV-MAPS”), designed for the Mu3e tracking detector. It is also used to test the Mu3e readout concept.
The telescope consists of four layers of the newest prototypes, the MuPix7 sensors, which send the fast serial data self triggered to an FPGA, where the data is time ordered and written to the PC, where online tracking is performed.
The presentation covers the chip architecture, readout concept, online reconstruction and test beam performance.

Speaker: Lennart Huth (Ruprecht-Karls-Universitaet Heidelberg (DE))

twepp16_huth_poster.pdf

58 Design Studies for the Phase II Upgrade of the CMS Barrel Electromagnetic Calorimeter

The High Luminosity LHC (HL-LHC) aims to reach the unprecedented integrated luminosity of 3 ab-1 with an instantaneous luminosity up to 5x10^34 cm2 s-1. This poses stringent requirements on the radiation resistance of detector components and on the latency of the trigger system. The barrel region of the CMS Electromagnetic Calorimeter will be able to retain the current lead tungstate crystals and avalanche photodiode detectors which will meet the performance requirements throughout the operational lifetime of the HL-LHC. The new front-end electronics and very front-end system required at high luminosities will be described.

Speaker: Adolf Bornheim (California Institute of Technology (US))

TWEPP_2016_ECAL_Upgrade_Final.pdf

59 Prototype Readout Electronics for the ALICE Inner Tracking System

The ALICE Collaboration is preparing an upgrade of the experimental apparatus. A key element of this upgrade is the construction of a new silicon-based (12 Gpixels, 10m2) Inner Tracking System. Its readout system consists of 192 readout units that control the pixel sensors, power modules and deliver the sensor data to the counting room. A prototype readout unit has been designed to test the interface between the sensor modules and readout electronics, signal integrity and data transfer reliability, the interface to the ALICE DAQ and trigger, and the system susceptibility to the expected radiation level (both TID and SEU).

Speaker: Krzysztof Marek Sielewicz (Warsaw University of Technology (PL))

TWEPP_2016_ksielewi.pdf

60 Testing and Integration of the Service Cylinders for the CMS Phase 1 Pixel

In this talk we present the design, assembly and integration of the service cylinders for the barrel pixel detector. Furthermore, we present results of the testing and calibrations carried out with a set of Phase 1 detector modules.

Speaker: Jennifer Ngadiuba (Universitaet Zuerich (CH))

Ngadiuba_TWEPP2016.pdf

61 The Common Data Acquisition Platform in the Helmholtz Association

Various german Helmholtz centers started 2014 to develop a modular data acquisition platform. This platform integrates generic hardware components like the multi-purpose HGF-AMC Hardware or the UFO smart camera framework, adding user value with linux drivers and board support packages. Technically the scope comprises FPGA-modules, frontend-electronics-interfaces, FPGA-microcontrollers plus software and high-performance data transmission to computing servers.
The core idea is a generic and component-based approach, satisfying specific requirements of different experiments.
Its ability to deploy on different hardware is an essential feature; another is MTCA.4-support for compatibility with commercial components.

Speaker: Peter Kaever (Helmholtz-Zentrum Dresden-Rossendorf)

DTS-Poster-v4.3-red.pptx.pdf

62 Phase 1 Upgrade of the CMS Drift Tubes Read-Out System

In order to cope with a twofold increase in nominal LHC luminosity, the second level of the readout system of the CMS Drift Tubes (DT) electronics needs to be redesigned to minimize event processing time and remove present bottlenecks. The uROS boards are uTCA modules, which include a Xilinx Virtex-7 FPGA and equip up to 6 12-channel optical receivers of the 240 Mbps input links. Each board collects the information from up to 72 input links (3 DT sectors), requiring a total of 23 boards. The design of the system and the first validation tests will be described.

Speaker: Alvaro Navarro Tobar (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)

63 Upgrades to the CSC Cathode Strip Chamber Electronics for HL-LHC

The luminosity, latency, and trigger rate foreseen at the High Luminosity LHC presents challenges to efficient readout of the Cathode strip chambers (CSCs) of the CMS end cap muon detector. Upgrades to the electronics are targeted for the inner rings of CSCs in each station, which have the highest flux of particles. The upgrades comprise digital cathode front end boards for nearly deadtimeless operation long latency capacity, new DAQ motherboards with higher-bandwidth links to accept the higher data rate, and a new Front End Driver system that can receive the higher input rates.

Speaker: Darien Wood (Northeastern University (US))

64 Electronics for the RICH Detectors of the HADES and CBM Experiments

The RICH detectors of the existing HADES spectrometer and the CBM experiment (to be built at FAIR) will use 64 channel Multi-Anode PMTs.
We designed a complete set of digitizing electronics, consisting of analog and digital frontend modules, power supply and data concentrator cards plugged into a backplane carrying 3x2 MAPMTs on the front side, and all readout modules on the backside.
These contain all necessary supply electronics, preamplifiers and FPGA-based TDC as well as the digital data and trigger handling logic and an optical transceiver. We are going to present the electronics along with performance test results.

Speaker: Jan Michel (Goethe University Frankfurt)

RichElectronicsHadesCbm.pdf

65 A New Profibus-DP Slave Interface Card for CERN’s Vacuum Sector Valve Controller

The vacuum control systems of CERN’s accelerators are based on PLCs, which communicate with controllers either with direct I/O, or via Profibus.
In order to improve the communication efficiency of the vacuum sector valve controllers using direct I/O, a low cost Profibus-DP slave interface card has been designed.
This paper describes the steps to design a Profibus-DP slave interface that can match user’s digital parallel bus. It presents the developed hardware and firmware, together with the corresponding assessment tests. It also flags the improvements of this new interface, in comparison with the previous system.

Speaker: Gregory Pigny (CERN)

TWEPP16_MUX_SVCU_poster_22-09-2016.pdf

66 Precision Timing with PbWO Crystals and Prospects for a Precision Timing Upgrade of the CMS Barrel Electromagnetic Calorimeter at HL-LHC

The Barrel part of the CMS Electromagnetic Calorimeter is made of 61200 scintillating lead tungstate (PbWO4) crystals, read out by avalanche photo-diodes. For the high luminosity phase of the LHC, a timing measurement with a precision of approximately 10 ps can be exploited for pileup mitigation and vertex assignment. Test beam results on the timing performance of PbWO4 crystals with various photosensors and readout electronics will be shown, along with the results from simulation studies. The implications of the very precise timing requirements on the design of the new readout electronics will be discussed.

Speaker: Vincenzo Ciriolo (Universita & INFN, Milano-Bicocca (IT))

67 Phase 1 Upgrade of the CMS Forward Calorimeter

The CMS experiment at the Large Hadron Collider at CERN is upgrading the photo-detection and readout system of the forward hadronic calorimeter (HF).  The phase-1 upgrade of the CMS forward calorimeter requires the replacement of the current photomultiplier tubes, as well as the installation of a new front-end readout system.  The new PMTs contain a thinner window as well as multi-anode readout. The front-end electronics will use the QIE 10 ASIC which combines signal digitization with timing information. This talk will describe the major components of the upgrade as well as the current status.

Speaker: Daniel Noonan (Florida Institute of Technology (US))

HF_Phase1Upgrade_TWEPP_DNoonan.pdf

68 The Address in Real Time Data Driver Card for the Micromegas Detector of the ATLAS Muon Upgrade

The ART Data Driver Card (ADDC) will be used in the ATLAS New Small Wheel (NSW) upgrade to process and transmit the Address in Real Time (ART) signals, which indicates the address of the first above-threshold event. A custom ASIC (ART ASIC) will receive the ART signals and do the hit-selection processing.
To evaluate the performance of the ADDC before the ART ASIC is fabricated, an FPGA based prototype is built. A Xilinx Artix-7 FPGA is used to emulate the ART ASIC. The bench test results of this prototype including performance and latency measurements will be described.

Speaker: Lin Yao (Brookhaven National Laboratory (US))

69 Performance and Advantages of a Soft-Core Based Parallel Architecture for Energy Peak Detection in the Calorimeter Level 0 Trigger for the NA62 Experiment at CERN

The NA62 experiment at CERN SPS has began its data-taking. Its main topic is to reduce uncertainties in the branching ratio of the ultra-rare decay $K^{+} \rightarrow \pi^{+}\enspace\nu\enspace\bar{\nu}$. In this context rejecting the background is a crucial topic. The Cal-l0 trigger get energy deposit from the calorimeters to suppress decays with $\pi^{0}$ and muons in the final state. In this work we present the performance of a soft-core based parallel architecture build on FPGAs for the energy peak reconstruction as an alternative to an implementation completely founded on VHDL language.

Speaker: Luca Federici (Universita e INFN Roma Tor Vergata (IT))

70 Performance and Operation of the Calorimetric Trigger Processor of the NA62 Experiment at CERN SPS

The NA62 experiment aims to measure the branching ratio of the rare kaon decay K+->pi+nu nubar at the CERN SPS. The calorimeter L0 trigger is the part of the TDAQ used to select events with a pi+ in the final state hadronic and to veto one of the most dominate background from events K+ -> pi+pi0. It has been developed and installed (it has taken first physics data in autumn 2014). We present the design, performance and operation during the last two years (2015 and part of 2016) high intensity data taking of the calorimeter Level 0 trigger.

Speakers: Nico De Simone (CERN), Vincenzo Bonaiuto (Universita e INFN Roma Tor Vergata (IT))

71 Development of Network Interface Cards for TRIDAQ Systems with the NaNet Framework

NaNet is a framework for the development of FPGA-based PCI Express (PCIe) Network Interface Cards (NICs) with real-time data transport architecture that can be effectively employed in TRIDAQ systems.
Key features of the architecture are the flexibility in the configuration of the number and kind of the I/O channels, the hardware offloading of the network protocols stack, the stream processing and the zero-copy RDMA (for both CPU and GPU) capabilities.
Three NIC designs have been developed with the NaNet framework for the CERN NA62 L0 trigger and for the KM3NeT-IT underwater neutrino telescope DAQ system.

Speaker: Alessandro Lonardo (Universita e INFN, Roma I (IT))

Poster_NANET_TWEPP2016.pdf

72 L-1 Trigger System for Electromagnetic Calorimeter of COMET Experiment

The COMET detector will include a electromagnetic calorimeter (ECal). The ECal signals will used for energy deposition measurement and for triggering. For triggering, the calorimeters signals will transformed into special short-shaped analog signals. These signals will then digitally processed with special algorithm, which allows one to obtain a set of logic signals necessary for event selection and a time-tag signal for time alignment of time measurements.

Speaker: Leonid Epshteyn (Budker Institute of Nuclear Physics)

73 ALICE Trigger System in RUN3

ALICE is the detector at the CERN LHC dedicated to the study of strongly interacting matter. The collaboration plans a major upgrade of the detector in RUN3. The interaction rates will increase to about 50 kHz for Pb-Pb and few hundred kHz for pp. The aim of the ALICE trigger system is to select essentially all of these interactions.The events are read out and the event records are sent to the HLT farm for further filtering. The combination of continuous readout detectors and a minimum bias trigger is used. The overview of the ALICE trigger system is presented.

Speaker: Luis Alberto Perez Moreno (Autonomous University of Puebla (MX))

ALICE_trigger_system_R3_poster_TWEPP_16.pdf

74 FPGA Based Algorithms for the New Trigger System for the Phase 2 Upgrade of the CMS Drift Tubes Detector

The Phase 2 upgrade of the CMS Drift Tubes detector aims at moving all the readout and trigger electronics from the inner detector to outside the cavern. Trigger algorithms need to be redesigned to handle direct timing information and remove present bottlenecks of resolution and deadtime, approaching to present high level trigger performance. In the present contribution we describe the work that has been performed to emulate the firmware that process 1 ns TDC hits from one DT chamber with the combinatorial problematic of the arrival time uncertainty in a detector with up to 400 ns of drift time.

Speaker: Alvaro Navarro Tobar (Centro de Investigaciones Energ. Medioambientales y Tecn. - (ES)

poster_twepp16.pdf

75 A High Bandwidth and Versatile Advanced MC Board, TRB_v1

We developed a new AMC board based on AMC.0, named as Trigger Receiver Board (TRB). TRB is a high bandwidth data-stream processor, using a Xilinx Artix-7 and 2 Kintex-7 FPGA. The Artix-7 takes care of the backplane connection while the Kintex-7s handle the front panel optical links. There are 17 optical links on the front panel, making a total bandwidth up to 150Gbps both in and out. On the backplane side, we implemented 2 Gigabit Ethernet and 8 multi-gigabit transceiver links connected to MCH and redundant MCH.

Speaker: Yifan Yang (IIHE)

TWEPP2016-J.Dong.pdf

76 Study of Hardware Implementation of Fast Tracking Algorithms

Real-time track reconstruction at high event rates is a major challenge for future experiments in high energy physics. To perform pattern-recognition and/or track fitting, artificial retina or Hough transformation have been introduced in the field which have to be implemented in the FPGA firmware.
In this contribution, we will report on a possible FPGA hardware implementation of retina algorithm based on the Floating-Point Operator IP. Detailed measurements with the algorithm are investigated. Retina performances and capabilities of the FPGA are discussed along with perspectives for further optimizations and for future applications.

Speaker: Ms Zixuan Song (Université libre de Bruxelles(ULB) - Central China Normal University (CCNU))

TWEPP2016-ZixuSONG.pdf

77 The Level-1 Tile-Muon Trigger in the Tile Calorimeter Upgrade Program

This report describes the Tile-Muon Trigger within the TileCal upgrade activities, focusing on the new on-detector electronics such as the Tile Muon Digitizer Board (TMDB) providing (receive and digitize) the signal from eight TileCal modules to three Level-1 muon endcap sector logic blocks.

Speaker: Andrey Ryzhov (Institute for High Energy Physics (RU))

ATL-COM-TILECAL-2016-034.pdf

78 Implementation of the data acquisition system for the Overlap Modular Track Finder in the CMS experiment

The Overlap Muon Track Finder (OMTF) is the new system developed during the upgrade of the CMS experiment. It uses the novelty approach to find muon candidates basing on data received from three types of detectors: RPC, DT and CSC. The upgrade of the trigger system requires also upgrade of the associated Data Acquisition (DAQ) system, that must transmit the data from the RPC detector, but for continuous monitoring of the OMTF, it should also transmit the data from the CSC and DT detectors. The paper describes the technical concepts and solutions used in the currently developed OMTF DAQ system.

Speaker: Dr Wojciech Zabolotny (University of Warsaw, Faculty of Physics (PL); Warsaw University of Technology, Institute of Electronic Systems (PL))

poster_CMS_DAQ.pdf

18:30 Optionnal Visit to KATRIN Experiment

Wednesday, 28 September

Invited Talk: (V.Goiffon, ISAE)

Convener: Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

79 CMOS Image Sensors in Harsh Radiation Environments

CMOS Image Sensors (CIS) have become the main solid state image sensor technology for visible imaging applications. Despite the higher radiation hardness of CIS compared to its CCD counterpart, there are still demanding applications where CMOS imager performances can be significantly reduced by high energy particles. This is the case for the most severe radiation environments where imaging capabilities are required: particle physics, nuclear fusion, nuclear power plants…
After a brief overview of the CIS technology and the review of basic degradation mechanisms in harsh radiation environments, mitigation techniques will be discussed and recent developments will be used as illustrative examples.

Speaker: Vincent Goiffon (ISAE-SUPAERO, Univ Toulouse)

InvitedSpeaker_Vincent_Goiffon.pdf

ASIC

Convener: Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

80 SAMPA Chip: the New ASIC for the ALICE TPC and MCH Upgrades

This paper presents the SAMPA, a new ASIC for the ALICE upgrade for Time Projection chamber (TPC) and Muon chamber (MCH) read-out frontend electronics.
The SAMPA ASIC is designed in 130nm CMOS technology with 1.2V nominal power supply. SAMPA includes 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel comprises a Charge Sensitive Amplifier, a shaping stage, and a 10-bit ADC. A DSP block and 11 SLVS output links (throughput up to 3.2 Gbps) complete the chip.
Experimental results of the first complete ASIC prototype will be presented.

Speaker: Marco Bregant (Universidade de Sao Paulo (BR))

1609_TWEPP2016_Bregant_v1.pdf

1609_TWEPP2016_Bregant_v1.pptx

81 SKIROC2_CMS : an ASIC for testing CMS HGCAL

SKIROC2_CMS is a chip derived from CALICE SKIROC2, providing 64 channels of low noise readout for 50pF Si-sensors over 10pC dynamic range. The pre-amps are followed by high/low gain 25ns shapers, 16-deep 40 MHz analog memory “waveform sampler” and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA techniques at system level.The chip, in AMS SiGe 0.35um, is expected in May. It will be tested and used for beam tests in the autumn.

Speaker: Christophe De La Taille (OMEGA (FR))

CdLT_TWEPP16.pdf

Systems, Planning, installation, commissioning and running experience

Convener: Geoff Hall (Imperial College (GB))

82 The upgrade of the CMS hadron calorimeter with silicon photomultipliers

The CMS experiment at the LHC will deploy the first large (16k channel)
silicon photomultiplier system in a high radiation environment as the central
feature of its hadron calorimeter upgrade.
The exceptional 35% photon detection efficiency of the SiPMs is critical
for ameliorating the effects of radiation damage of the calorimeter scintillator.
The SiPM signals are digitized by the QIE11 ASIC
which provides a 1% energy measurement over a 17-bit dynamic range.
We will describe the performance and radiation tolerance of the entire system,
focusing on the SiPMs, the precision control electronics, and the QIE11-based readout.

Speaker: Nadja Strobbe (Fermi National Accelerator Lab. (US))

CMSupgradeSiPM_NadjaStrobbe_Final.pdf

83 Data Acquisition System for the CALICE AHCAL Calorimeter

The data acquisition system (DAQ) for a highly granular analogue hadron calorimeter (AHCAL) for the future International Linear Collider (ILC) will be presented. The developed DAQ chain has several stages of aggregation and scales up to 8 million channels foreseen for the AHCAL detector design. The largest aggregation device, LDA (Link data aggregator), has 96 HDMI connectors, four Kintex7 FPGAs and a central Zynq SoC (System-On-Chip). Architecture and performance results will be shown in detail. Experience from CERN testbeams with a small detector prototype consisting of 15 detector layers will be reported.

Speaker: Jiri Kvasnicka (Acad. of Sciences of the Czech Rep. (CZ))

2016-09-28_TWEPP_Kvas_DAQ.pdf

10:40 Coffee Break

ASIC

Convener: Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))

84 HARDROC3, a 3rd generation ASIC with zero suppress for ILC Semi Digital Hadronic Calorimeter

HARDROC is the very front end chip designed to readout the Resistive Plate Chambers foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the calorimeter implies thousands of electronics channels per cubic meter which is a new feature of “imaging” calorimetry. Moreover, for compactness, chips must be embedded inside the detector making crucial the reduction of the power consumption down to 12 μW per channel. This is achieved using power pulsing and online zero-suppression.
Around 800 HARDROC3 were produced in 2015. The overall performance and production tests will be detailed.

Speaker: Stephane CALLIER (OMEGA - Ecole Polytechnique - CNRS/IN2P3)

SC_HR3_TWEPP2016.pdf

85 PETIROC2A, a 32-channel 20 GHz GBW readout ASIC for accurate time resolution and precise charge measurements

Petiroc2a is a 32-channel front-end ASIC designed in AMS 0.35µm SiGe technology to read out Silicon Photomultipliers (SiPMs) for applications requiring accurate time resolution and energy measurement over a large dynamic range.
Each channel integrates a 20GHz Gain Bandwidth preamplifier followed by an ultra fast discriminator and a TDC. The first incident photons can be measured with a time resolution better than 100ps. A low gain shaper ensures an energy measurement up to 400 pC. The 32 time and charge measurements are internally digitized by a 10-bit ADC.
Measurements will be detailed in this presentation.

Speaker: Christophe De La Taille (OMEGA - Ecole Polytechnique - CNRS/IN2P3)

nsm_twepp2016_petiroc2a_V2.pdf

86 First experimental results with TOFPET2 ASIC

The TOFPET2 ASIC is a low-power, low-noise, readout and digitization chip for SiPMs sensors implemented in 110nm CMOS technology optimized for time-of-flight measurements. The circuit has 64 independent channels including quad-buffered TDCs and charge integration ADCs in each channel, and is an evolution of the TOFPET1 ASIC, which was developed in 130nm CMOS technology for Positron Emission Tomography (PET) applications. Relative to the first chip, TOFPET2 implements new frontend amplifiers, charge integration, improved timing and increased event rate. The chip tape-out was done in November 2015 and first tests started in end March 2016.

Speaker: Agostino Di Francesco (LIP Laboratorio de Instrumentacao e Fisica Experimental de Part)

TOFPET2_TWEPP2016.pdf

Systems, Planning, installation, commissioning and running experience

Convener: Geoff Hall (Imperial College (GB))

87 The SoLid anti-neutrino detector's read-out system

The SoLid collaboration have developed an intelligent read-out system to reduce their 3000 silicon photomultiplier detector's data rate by a factor of 10000 whilst maintaining high efficiency for storing data from antineutrino interactions.
The system employs an FPGA level waveform characterisation to trigger on neutron signals.
Following a trigger, data from a spacetime region of interest around the neutron will be read out using the IPbus protocol.
In this talk the SoLid experiment will be introduced, the design of the read-out system will be explained and the performance of prototype versions of the system will be presented.

Speaker: David Cussans (University of Bristol (GB))

cussans-solid-twepp2016.pdf

88 Prototypes and tests of the LHCb Scintillating Fiber detector front end electronics.

The on-detector electronics of the LHCb Scintillating Fiber Detector consists of multiple PCBs assembled in a unit called Read Out Box, capable of reading out 2048 channels with an output rate of 70 Gbps. There are three types of boards: PACIFIC, Clusterization and Master Board. The PACIFIC boards host PACIFIC ASICs, with pre-amplifier and comparator stages producing two bits of data per channel. A cluster-finding algorithm is then run in a FPGA on the Clusterization board. The Master Board distributes fast and slow control, and power. We describe the design, production and test of prototype PCBs.

Speaker: Wilco Vink (Nikhef National institute for subatomic physics (NL))

SciFi_Wilco_Vink.pdf

89 A micro-TCA based data acquisition system for the triple-GEM detectors for the upgrade of the CMS forward muon spectrometer

We will present the electronic and DAQ system being developed for TripleGEM detectors which will be installed in the CMS muon spectrometer. The microTCA system uses an Advanced Mezzanine Card equipped with an FPGA and the Versatile Link with the GBT chipset to link the front and back-end. On the detector an FPGA mezzanine board, the OptoHybrid, has to collect the data from the detector readout chips to transmit them optically to the microTCA boards using the GBT protocol. We will describe the hardware architecture, report on the status of the developments, and present results obtained with the system.

Speaker: Thomas Lenzi (Universite Libre de Bruxelles (BE))

Talk_Thomas_Lenzi.pdf

Talk_Thomas_Lenzi.pptx

12:25 Lunch

Invited Talk: (S. Danzeca, CERN)

Convener: Philippe Farthouat (CERN)

90 Radiation tolerant issues for LHC accelerator

Electronic systems located in LHC underground areas can suffer by radiation induced failures. The knowledge of the radiation levels around the LHC accelerator and the cause of faults permits to improve the LHC availability every year. The shielding, relocation and equipment upgrade are the ingredients to mitigate the radiation effects. A test protocol exists for the equipment upgrade which requires radiation tolerant design. The methodology and the facilities are available to improve the radiation tolerance of the electronic systems that requires high reliability. This presentation will go through all these steps to explore the key elements that can make possible to reduce the radiation induced failures.

Speaker: Salvatore Danzeca (CERN)

InviteSpeaker_Salvatore_Danzeca.pdf

InviteSpeaker_Salvatore_Danzeca.pptx

ASIC

Convener: Alex Grillo (University of California,Santa Cruz (US))

91 A fast, ultra-low power 10-bit SAR ADCs in CMOS 130 nm technology

The design and measurement results of four ultra-low power 10-bit SAR ADCs, fabricated in CMOS 130~nm technology, are presented. All prototypes use very similar architecture with main difference in split in the capacitive DAC network. The prototypes are fully functional, achieve excellent linearity (DNL < 0.3 LSB and INL ~0.5 LSB), and show very good ENOB above 9.5 for 0.2 Nyquist input frequency, up to maximum sampling rate 40-50 MSps, depending on prototype. All prototypes consume less than 900 uW at 40 MSps achieving an excellent FOM 20-30 fJ/conversion-step.

Speaker: Dr Jakub Moron (AGH University of Science and Technology (PL))

moron_Twepp_ADC_2016_09.pdf

92 MATRIX: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure

This paper presents a 4-chanel TDC chip demonstrator with the following features: 15-ps resolution, 1280 ns dynamic range, dead time < 20 ns, up to 10 MHz of sustained input rate per channel, around 60 mW of power consumption and very low area in a 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry which is based on a resistive interpolation mesh circuit (patented) a two-dimensional regular structure with outstanding performance in terms of power consumption, area and low process variability.

Speaker: Juan Mauricio Ferre (University of Barcelona (ES))

MATRIX_TWEPP2016_FINAL.pdf

MATRIX_TWEPP2016_FINAL.pptx

93 Developments of two 4 × 10-Gbps radiation-tolerant VCSEL array drivers in 65 nm CMOS

We present designs and test results of two ASICs, VLAD and lpVLAD. Each is a 4-channel, 10-Gbps-per-channel VCSEL array driver fabricated in a 65 nm CMOS technology. lpVLAD deploys a novel high-efficient output structure to achieve a record low power consumption of 25 mW/ch when delivering 2 mA bias and 6 mA modulation currents at 10-Gbps. Eye diagrams of both two designs under post-layout simulations easily pass 10-Gbps requirement. The full-channel optical link test will be carried out in June and the results will be reported in the conference.

Speaker: Datao Gong (Southern Methodist Univeristy)

VLAD_TWEPP2016_talk.pdf

Systems, Planning, installation, commissioning and running experience

Convener: Lutz Feld (RWTH Aachen University)

94 On-detector electronics for the LHCb VELO upgrade

The LHCb Experiment will be upgraded to a trigger-less system reading out the full detector at 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator (VELO) will be a hybrid pixel detector read out by the VeloPix ASIC with on-chip zero-suppression. This paper will present the systems overview and design of the VELO on-detector electronics, including the front-end hybrid, the opto-conversion and power distribution boards. Results will be shown from the evaluation of these prototypes of these boards.

Speaker: Sneha Amogh Naik (University of Glasgow (GB))

TWEPP16_talk_SNaik.pdf

TWEPP16_talk_SNaik.pptx

95 GBT based readout in the CBM experiment

The CBM experiment at FAIR will use GBTX and Versatile link based readout systems for several subdetectors.

Particularly challenging is the readout of the silicon tracking system (STS) which requires features like a minimal number of frontend connections, AC coupling and time deterministic messages.

The paper gives a detailed description of the readout concept for the STS, emphasizing the common features with the GBT based readout in other CBM detectors.
A CBM common readout board with 3 GBTX is presented which provides the full GBT functionality for all systems and can be interfaced to various prototype readout chains.

Speaker: Joerg Lehnert (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE))

GBTReadout_CBM_TWEPP2016_JLehnert_Final.pdf

96 FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

Speaker: Kai Chen (Brookhaven National Laboratory (US))

TWEPP2016_FELIX.pdf

16:05 Coffee Break

POSTER: Session 2

Convener: Ken Wyllie (CERN)

97 Readout Channel with Majority Logic Timestamp and Digital Peak Detector for Muon chambers of the CBM Experiment

A prototype readout channel was manufactured in UMC CMOS 180 nm for the purpose of the CBM experiment at the FAIR accelerator. The channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, 6 bit SAR ADC (40 Msps, 1.5mW power consumption), digital peak detector and block of the time stamp registration. The control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1500 el and 2000 el ENC accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel.

Speaker: Evgeny Malankin (NRNU MEPhI)

poster_twepp2016_MUCHASIC.pdf

98 Front-End and Back-End Solutions in the CBM STS Readout ASIC

STS-XYTER2 is a new full-size CBM Silicon Tracking System and Muon Chamber prototype readout ASIC designed in UMC 180 nm CMOS technology. It is a self-triggered amplitude and time measurement chip implementing a digital back-end compatible with a GBTx-based data acquisition scheme with scalable data bandwidth. We present details on the front-end and back-end solutions used in this ASIC and simulation results.

Speaker: Krzysztof Kasiński (AGH University of Science and Technology, Cracow)

2016.09.26 - TWEPP - Front-End and Back-End Solutions.pdf

99 ASPIC and CABAC: Two ASICs to Readout and Pilot CCD

For several years, a group of engineers and physicists from LAL and LPNHE have been working on the design of two front end ASICs dedicated to Charge Couple Devices (CCD). ASPIC (Analogue Signal Processing Integrated Circuit), designed in AMS CMOS 0.35µm 5V technology, is meant to readout and process the analog signals of CCDs. CABAC (Clocks And Biases ASIC for CCDs), designed in AMS CMOS 0.35µm 50V technology, produces the clocks and biases needed by the CCDs to work at their full potential. This paper presents the performances of the final versions of these two ASICs.

Speaker: Jimmy Jeglot (LAL CNRS IN2P3)

2016 twepp_ASPIC_CABAC_for_CCD.pdf

100 SLVS Transmitter and Receiver for Readout ASIC

Scalable Low Voltage Signaling (SLVS) Transmitter (Tx) and Receiver (Rx) IP blocks are designed in the UMC 180 nm CMOS technology as component of the readout ASIC for the muon chambers (MUCH) of the Compressed Baryonic Matter (CBM) experiment at FAIR (Darmstadt, Germany). These blocks are a prototype of the physical layer of the e-link interface that is used for ASIC-GBTx connection. The experimental results at 320 Mbit/s are presented.

Speaker: Ivan Bulbakov (NRNU MEPhI)

poster_twepp2016_SLVS.pdf

101 A Low-Power 10 Gbps Serial Link Transmitter ASIC for Particle Detectors in 65nm CMOS

This paper presents a 10 Gbps serial link transmitter ASIC designed in a 65 nm CMOS technology. The ASIC mainly includes an LC-VCO PLL, a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 6-to-12 GHz tuning range and an RMS jitter of 0.67pS. The serializer has a deterministic jitter of 11 pS and a programmable output swing from 200mV to 800mV (pk-pk). The PLL and the serializer consumes 53.6 mW and 73mW from a 1.2V power supply, respectively.

Speaker: Prof. Jinghong Chen (University of Houston, Houston)

Poster 10 Gbps Serial Data Link.pdf

102 A Low-Power and Low Transmission Latency Dual Channel Serializer ASIC for Detector Front-End Readout

We present design and test results of a dual-channel serializer ASIC, LOCx2, for detector front-end readout. LOCx2 interfaces an ASIC ADC, ADS5272 and ADS5294. LOCx2 may take data from any 12-bit or 14-bit, multiple channel ADCs with sampling rate from 32 to 43 MSPS. We also present the design of LOCx2-130, a drop-in backup to LOCx2 based a 0.13 µm bulk silicon CMOS process. Power consumption and transmission latency for LOCx2 is 900 mW (88 mW/Gbps) and 27 ns, and 350 mW (37 mW/Gbps) and 38 ns for LOCx2-130.

Speaker: Datao Gong (Southern Methodist Univeristy)

Poster LOCx2 TWEPP16_v3.pdf

103 Integrated Input Protection Against Discharges for Micro Pattern Gas Detectors Readout ASICs

Immunity against possible random discharges inside active detector volume of the MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC and test results using an electrical circuit to mimic discharges in the detector.

Speaker: Dr Tomasz Andrzej Fiutowski (AGH University of Science and Technology (PL))

discharge.pdf

104 MGPA++ A Pre-Amplifier for CMS Barrel ECAL at HL-LHC

Upgrades are planned for the for the CMS barrel ECAL readout electronics . One option for an upgraded pre-amplifier is an improved version of the existing multi-gain pre-amplifier (MGPA). The upgraded MGPA is designed for shorter shaping time to optimize noise performance with photo-detectors damaged by radiation. It also has the ability to identify pulses generated by charge deposited directly in the photo-detectors rather than resulting from scintillation light.

Initial studies in ASIC design for an upgraded MGPA, together with work to evaluate the performance of the design are presented.

Speaker: Sema Zahid (Brunel University (GB))

105 A Temperature Compensated Triple-path PLL for DUNE Experiments

Many HEP applications require circuits to continuously operate over large temperature range. In particular, the DUNE experiment requires circuits be capable of operating at cryogenic temperature. We present a novel temperature-compensated triple-path PLL (TP-PLL) for this application. The TP-PLL is capable of automatically compensating its frequency as temperature changes while maintaining stable operation and good jitter performance. A prototype TP-PLL at 2.56GHz has been implemented using 65nm CMOS process. It occupies an area of 0.08 mm2, consumes 13.2 mW, and has a frequency drift reduction by 99%.

Speaker: Mr Tianwei Liu (Southern Methodist University)

106 uTRiG: A Mixed Signal Silicon Photomultiplier Readout ASIC for Ultra-Fast Timing and Ultra-High Rate Applications

We present the development of uTRiG, a mixed signal Silicon
Photomultiplier readout ASIC in UMC 180nm CMOS technology, dedicated to
the Mu3e experiment. It extends the ultra-fast timing performance of
the STiCv3 chip with a fast digital readout for ultra-high rate
applications. The high timing performance of the silicon proven, fully
differential SiPM readout channels and 50 ps time binning TDCs are
complemented by a redesigned digital readout logic and a gigabit
data link, allowing event rates up to 1.3 MHz/channel. The design
of uTRiG and the characterization results of the data link will be
presented.

Speaker: Huangshan Chen (Ruprecht-Karls- Universität Heidelberg)

2016_TWEPP_MuTRiG_POSTER.pdf

107 Pixel Architectures in HV/HR CMOS Process for ATLAS Inner Detector Upgrade

Some pixel architectures designed in LFoundry 150 nm HV CMOS process for the ATLAS Inner Detector upgrade will be presented. These pixels can be readout standalone or can be connected to the FE-I4 readout chip via bump bonding or glue. Negative high voltage is applied to the HR (>2 kOhms.cm) substrate in order to deplete the DNW (Deep N-Well) charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 µmx250 µm for all pixels.

Speaker: Yavuz Degerli (CEA/IRFU, Centre d'etude de Saclay, Gif-sur-Yvette (FR))

Yavuz_Degerli.pdf

108 Multiple Use SiPM Integrated Circuit (MUSIC) for SiPM Anode Readout

This paper presents an 8 channel ASIC for SiPM anode readout. The Multiple Use SiPM Integrated Circuit (MUSIC) is based on a low input impedance current conveyor (patented). It provides a differential channel summation and individual SE (analog or ToT) channel readout. MUSIC is designed using AMS 0.35um SiGe technology. Full die simulation yields these specifications: 500MHz bandwidth for channel sum and 150MHz for individuals channels, output pulse width at half maximum (FWHM) between 5-10ns and with a power consumption of 30mW/ch plus 200mW for 8 ch sum. Encapsulated samples will be tested in spring of 2016.

Speaker: Gerard Fernandez (University of Barcelona (UB))

MUSIC_TWEPP2016.pdf

109 A Low-Power 10-bit 250-MS/s Dual-Channel Pipeline ADC in 0.18 µm CMOS

This paper presents a 10-bit 250-MS/s time-interleaved pipelined ADC. A distributed clocking scheme is developed to eliminate timing skew between channels without introducing load capacitance to the driving buffer. The channel offset and gain mismatch error is calibrated in digital domain. In addition, a switch-embedded opamp-sharing technique is developed to reduce ADC power consumption and eliminate the memory effect. The simulated SNDR and SFDR are 61.84 dB and 78.2 dB, respectively. The ADC core consumes 28mW under a 1.8V supply at 250 MS/s sampling rate.

Speaker: Prof. Jinghong Chen (University of Houston)

Poster ADC.pdf

110 Characterization of the Column-Based Priority Logic Readout of Topmetal-II- CMOS Pixel Direct Charge Sensor

We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct
charge sensor integrated 72x72 pixels each capable of directly collecting charge through exposed
metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of
the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through
comparators with individually DAC settable threshold. Hits are read out via a column-based priority logic, pertaining both hit location and time information. We study the detailed working behavior
and performance of this readout and demonstrated its potential in imaging applications.

Speaker: Mr Wei Zhang (Central China Normal University)

111 2.5Gb/s Simple Optical Wireless Communication System for Particle Detectors in High Energy Physics

We successfully demonstrated simple and low cost 2.5 Gb/s optical wireless transmission at 10 cm distance, aiming to be employed in high-energy physics experiments using off-the-shelf VCSEL and PIN photodiode with proper ball lens. The measured tolerance to misalignment is around ±1mm at Bit Error Rate of 10^-12.

Speaker: Wajahat Ali (SSSUP Pisa Italy)

112 Versatile Transceiver Production and Quality Assurance

The Versatile Link project has developed a radiation-hard optical link for LHC phase 1 detector upgrades. The project has reached its final stage and we have launched the series production of the Versatile Transceivers (VTRx) and Versatile Twin Transmitters (VTTx). This paper provides an update of the production status and a detailed description and results of the quality assurance programme. The QA programme includes qualification and acceptance testing at CERN and production testing at the manufacturer’s premises.

Speaker: Lauri Juhani Olantera (CERN)

113 First Implementation of a Two-Stage DC-DC Conversion Powering Scheme for the CMS Phase-2 Outer Tracker

A novel, 2-step DC-DC conversion powering scheme will be used for the “2S” silicon strip modules of the HL-LHC CMS tracker. Each module is equipped with a service hybrid, which carries two DC-DC converters along with a LP-GBT and a VTRx+ module. The first DC-DC converter generates 2.5V, required for the opto-electronics, while the second stage converts 2.5V to 1.25V, required for all other ASICs. We will present a service hybrid prototype, describe its performance and demonstrate the feasibility of an on-module, 2-step powering scheme with system tests.

Speaker: Katja Klein (Rheinisch-Westfaelische Tech. Hoch. (DE))

KatjaKlein_TWEPP2016.pdf

114 Spotting and Curing Noise Issues in the Silicon Vertex Detector of the Belle II Experiment

The Belle II experiment will use a Silicon Vertex Detector based on DEPFET pixel (PXD) and double-sided microstrip (SVD) technology. In 2014 at a combined SVD/PXD beam test we observed electrical noise in the SVD system which caused many headaches for more than two years. Since then Electromagnetic Compatibility (EMC) tests using some of the best equipment available in an EMC tight hall, but also using cheap and even self-made probes helped to improve the SVD prototype. At another combined beam test in April 2016 we finally identified the noise source. It was not the suspected PXD...

Speaker: Richard Thalmeier (Austrian Academy of Sciences (AT))

115 An Advanced Power Analysis Methodology Targeted to the Optimization of a Digital Pixel Readout Chip Design and its Critical Serial Powering System

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (Shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensively investigate dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

Speaker: Sara Marconi (INFN and University of Perugia (IT))

twepp2016-poster-v2.1.pdf

116 High Precision, Low Disturbance Calibration of the High Voltage System of the CMS Barrel Electromagnetic Calorimeter

The CMS Electromagnetic Calorimeter utilizes scintillating lead tungstate crystals, with avalanche photodiodes (APD) as photo-detectors in the barrel part. 1224 HV channels bias groups of 50 APD pairs, each at a voltage of about 380V. The APD gain dependence on the voltage is 3%/V. A stability of better than 60 mV is needed to have negligible impact on the calorimeter energy resolution. Until 2015 manual calibrations were performed yearly. A new calibration system was deployed recently, which satisfies the requirement of low disturbance and high precision. The system is discussed in detail and first operational experience is presented.

Speaker: Giuseppe Fasanella (Universite Libre de Bruxelles (BE))

TWEPP_Fasanella_v3.pdf

117 System-Level Considerations of the Front-End Readout ASIC in the CBM Experiment from the Power Supply Perspective

Paper presents the Silicon Tracking System low-voltage power system design starting from the power budget and noise spectrum requirements resulting from the front-end chip design (STS/MUCH-XYTER2). Power-supply rejection ratio simulation results, estimation on how the simulated and measured noise spectra of the voltage regulators would affect the front-end electronics, power budget and selection of feasible powering scheme in the experiment including aspects of area, power efficiency and radiation hardness will be presented.

Speaker: Dr Krzysztof Kasiński (AGH University of Science and Technology, Cracow, Poland)

2016.09.26 - TWEPP - System Level Considerations.pdf

118 Testing of Hybrid Circuits for the CMS Tracker Upgrade of Front-End Electronics

The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, front-end modules, which implement L1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests, before they are assembled into modules. Test methods are proposed together with their corresponding testing hardware and software. They feature functional tests and signal injection in cold environment aiming at finding the possible failures of the hybrids under real operating conditions.

Speaker: Tomasz Gadek (CERN)

TWEPP-16_TG_GB_MK.pdf

119 Test Strategies for Industrial Testers for Converter Controls Equipment

Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex. To achieve a high MTBF of the system, a set of industrial testers for the converters controls electronics is used. The paper is a follow-up after a similar paper at TWEPP2015, including more test platforms(Boundary-Scan) and the outcome after test phase in production. We report on the test software and hardware design and test strategy applied for a number of devices, that resulted in maximizing the test coverage and minimizing the test design effort.

Speaker: Patryk Wojciech Oleniuk (Ministere des affaires etrangeres et europeennes (FR))

Poster_TWEPP16_Testers_v3.pdf

120 Lessons Learned in High Frequency Data Transmissions Design

HEP experiments requirements lead to highly integrated systems with many electrical, mechanical and thermal constraints. A complex performance optimisation is required. High speed data transmission lines are designed, while simultaneously minimising radiation length. Methods to improve the signal integrity of point to point links and multi-drop configurations are described. FEA calculations are essential to the optimisation which allow data rates of 640 Mbps for point to point links over a length of up to 1.4m, as well as 160 Mbps for multi-drop configuration. The designs were validated using laboratory measurements of S-parameters and direct BER tests.

Speaker: Stephanie W Sullivan (STFC - Rutherford Appleton Lab. (GB))

Stephanie_Sullivan.pdf

121 A PCI DAQ Board Prototype after the ATLAS Pixel Detector IBL-Layer 1 and 2 ROD Cards

The ATLAS Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL) that is read out via two boards: the Readout-Driver card (ROD) and the Back-of-Crate card (BOC). In this presentation we summarize first the experience of building and commissioning the boards to read out the ATLAS Pixel detector, with particular emphasis to the ROD card.
In addition, here it is presented the design and the preliminary tests of a prototype card, backward compatible with ATLAS Pixel Detector, which also features PCI express and GBT and other I/O interfaces.

Speaker: Luca Lama (Universita e INFN, Bologna (IT))

122 Design of a Radiation Tolerant System for Total Ionizing Dose Monitoring Using Floating Gate and RadFET Dosimeters

The necessity to improve the accuracy of the Total Ionizing Dose (TID) measurements at CERNs’ radiation zones, has driven the research of new TID-measuring candidates. For this purpose, a TID Monitoring System (TIDMon) is designed, that investigates the effects of the TID on a Floating Gate Dosimeter (FGDOS) compared to Radiation-sensing Field-Effect Transistors (RadFETs). The monitoring system is characterized inside the CERN test facilities where the LHC mixed radiation field is reproduced. The architecture of the TIDMon, the radiation tolerance techniques and the design choices adopted for the system are presented in this work

Speaker: Rudy Ferraro (Universite Montpellier II (FR))

TWEPP_poster.pdf

123 Adaption of Low Cost Safety COTS MCU For Low Level Radiation Applications in Accelerator Facilities

Our work targets soft errors in embedded systems operating in particle accelerator physics experiments. We propose to use the safety mechanisms included in the low cost Cortex-R4F to mitigate Single Event Effects, as well as additional procedures to recover data from external memories. These procedures include making an interleaved backup of the program data by using the DMA controller. In case the CRC mechanism detects a mismatch either in the interleaved backup data or in the program/heap/stack, the faulty data can be rewritten from the copy or the original data.

Speaker: Antonio Lucio (Goethe-Universität Frankfurt am Main)

TWEPP_Poster.pdf

124 Radiation Hardened by Design, Low Jitter, 2.56 Gbps LVDS/SLVS Based Receiver in 65 nm CMOS

This paper proposes a 2.56 Gbps, radiation hardened by design, LVDS/SLVS like receiver designed in a commercial 65 nm CMOS technology. Simulation results predict 500 µW power consumption and 400 fs RMS output jitter. A replica receiver with a compensation loop is used to measure and compensate variations in the propagation delay of the output edges due to total ionizing dose (TID) radiation effects and/or process-temperature and voltage variations. This loop will ensure an equal propagation delay of the rising and falling output edges, to allow the use in accurate timing circuits.

Speaker: Bram Faes (KU Leuven)

Bram_Faes.pdf

125 Integration and Testing of the DAQ System for the CMS Phase 1 Pixel Upgrade

The CMS pixel detector phase 1 upgrade in 2017 requires an upgraded DAQ to accept higher data rates. A new DAQ system has been developed based on a combination of custom and standard microTCA parts. Custom mezzanines on FC7 AMCs provide a front-end driver for readout, and front-end controller for configuration, clock and trigger. The DAQ system is undergoing a series of integration tests including readout of the pilot pixel detector already installed in CMS, checkout of the phase 1 detector during its assembly, and testing with the CMS central DAQ.

Speaker: Bora Akgun (Rice University (US))

Poster_BoraAkgun.pdf

126 Precision Electronics for a System of Custom MCPs in the TORCH Time of Flight Detector

The TORCH detector to provide low-momentum particle identification is an R&D project, combining Time- of Flight and Cherenkov techniques to achieve charged particle pi/K/p separation up to 10 GeV/c. The measurement requires a timing resolution of 70ps for single photons. Based a scalable design, a Time of Flight (TOF) measurement system has been developed to instrument a novel customized 512-channel Micro Channel Plate (MCP) device. A Gigabit Ethernet-based readout scheme that operates the TORCH demonstration unit consisting of ten such MCPs will be presented. The trigger and clock distribution will also be discussed.

Speaker: Rui Gao (University of Oxford (GB))

TORCH_Poster_TWEPP2016.pdf

127 ATLAS Phase-II-Upgrade Pixel Data Transmission Development

The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

Speaker: Marius Wensing (Bergische Universitaet Wuppertal (DE))

ATLAS Phase-II-Upgrade Pixel Data Transmission Development

128 A Versatile Small Form Factor Twisted-Pair TFC FMC for mTCA AMCs

In continuous readout systems of particle physics experiments, providing a common clock, time reference and the distribution of critical low latency messages to the processing and fronted layers of the readout is a crucial task. In the context of CBM, a versatile small form factor TFC interfacing FMC was developed, offering bidirectional twisted-pair (TP) links for communicating between TFC nodes and a versatile clocking including voltage controlled oscillators and the connection to the telecommunication clock lines of mTCA crates. Being designed for both TFC Master and Slaves, the card allows rapid system developments without additional Slave hardware circuits.

Speaker: Lukas Meder (Karlsruhe Institute of Technology)

Meder_A_versatile_Small_Abstr107_Board18_TWEPP16.pdf

129 A Universal FMC-Based DAQ System

Towards development of a 10MGy rad-hard ASIC, evaluation of innovative 3D integration technology and CMOS - active edge pixel sensor characterization, a versatile DAQ system is presented. Based on a Saprtan 6 PCIe board, an FMC mezzanine card is developed providing a 68-channel digital input. Featuring automatic bi-directionality and variable output level (0.9V - 4.8V) with high impedance capability, each cannel is independently adjustable. The 8.5ns transceiver rise time assures required 40MHz rate for HL-LHC conditions. An 8bit ADC combined with clock buffering and serialization, limit to four the number of control lines.

Speaker: Mr Jimmy Jeglot (Laboratoire de l'accélérateur linéaire)

TWEPP.pdf

130 Digital Readout Board for CMS and TOTEM Precision Proton Spectrometer Timing Upgrade Project

For the CMS and TOTEM Precision Proton Spectrometer Project, a digital readout board was designed to take front-end data of the Diamond Detectors and Quartz Timing Cherenkov Detectors, reformat the data timing packets, and transmit them to the CMS and TOTEM data acquisition systems through optical data links. This board is capable of having HPTDC or SAMPIC mezzanines for high-resolution timing measurement of the leading and trailing edges in the hit pulses with the resolution of 10 - 20 ps.

Speaker: Francesca Cenna (Universita e INFN Torino (IT))

GA_TWEPP16_poster.pdf

131 The Next Generation Front-End Controller for the Phase 1 Upgrade of the CMS Hadron Calorimeters.

In the Phase 1 Upgrade of the CMS Hadron Calorimeters, the ngFEC is the system responsible for distributing the LHC clock, the synchronization signals and the slow controls to the frontend electronics using a GBT bidirectional link. It is based on the FC7, a μTCA AMC developed at CERN and built around the Xilinx Kintex-7 FPGA. Its main features are: a fixed latency for fast signals across power cycles, a redundancy scheme in the communication with the frontend modules, and the ability to program all frontend modules. This contribution reviews the characteristics and the development status of the ngFEC.

Speaker: Francesco Costanza (Deutsches Elektronen-Synchrotron (DE))

ngFEC_TWEPP16_FCostanza.pdf

132 Design of an AdvancedTCA board Management Controller Solution

The AdvancedTCA (ATCA) standard has been selected as the hardware platform for the upgrade of the back-end electronic of the CMS and ATLAS experiments of the Large Hadron Collider (LHC). In this context, the electronics systems for experiments group for experiments at CERN is running a project to evaluate, specify, design and support xTCA equipment. As part of this project, an Intelligent Platform Management Controller (IPMC) for ATCA blades, based on a commercial solution, has been designed to be used on existing ATCA blades. This poster reports on the status of this project presenting the hardware and software developments.

Speaker: Julian Maxime Mendez (CERN)

133 ALICE Inner Tracking System Readout Electronics Prototype Testing with the CERN “Giga Bit Transceiver”

The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to DAQ. To prototype various aspects of this readout system of the ITS, an FPGA based carrier board and an associated daughter card containing the CERN Gigabit Transceiver (GBT) chipset has been developed. This contribution describes laboratory and radiation testing results with this prototype board set.

Speaker: Joachim Schambach (University of Texas (US))

TWEPP2016_schambach_final.pdf

134 A Silicon Strip Telescope for Prototype Sensor Characterisation Using Particle Beam and Cosmic Rays

We present the design and the performance of a silicon strip telescope that we have built and recently used as reference tracking system for prototype sensor characterisation. The telescope was operated on beam at the CERN SPS and also using cosmic rays in the laboratory. We will describe the data acquisition system, based on a custom electronic board that we have developed, and the online monitoring system to control the quality of the data in real time.

Speaker: Jinlin Fu (Università degli Studi e INFN Milano (IT))

TWEPP2016.pdf

135 Web-Based DAQ Systems: Connecting the User and Electronics Front-Ends

Systems designed to control and monitor particles detectors often make use of a back-end server to interact with the front-end electronics and to deliver the DAQ interface and real-time information to the user. We propose to port the functionalities of the back-end server to web interfaces and to the front-end electronics by implementing them on a dual soft-core processor : one core running an HTTP and WebSocket server to deliver the DAQ interface and establish real-time communication with the user for monitoring activities, and one core tightly connected to the electronics for control purposes.

Speaker: Thomas Lenzi (Universite Libre de Bruxelles (BE))

Poster_Thomas_Lenzi.pdf

136 The CMS Electron and Photon Trigger for the LHC Run 2

The CMS experiment implements a sophisticated two-level triggering system composed of Level-1, instrumented by custom-design hardware boards, and a software High-Level-Trigger. A new Level-1 trigger architecture with improved performance is now being used to maintain the thresholds that were used in LHC Run1 for the more challenging luminosity conditions experienced during Run2. The upgrades to the calorimetry trigger will be described along with performance data. The algorithms for the selection of final states with electrons and photons, both for precision measurements and for searches of new physics beyond the Standard Model, will be described.

Speaker: Dev Nabarun

Nabarun_Dev.pdf

137 Design and Performance of the Phase I Upgrade of the CMS Global Trigger

The Global Trigger is the final decision stage of the Level-1 Trigger of the CMS Experiment at the LHC. Previously implemented in VME, it has been redesigned and completely rebuilt in microTCA technology, using the Virtex-7 FPGA chip family. This allows implementing trigger algorithms close to the final analysis selection, combining different physical objects. The flexible and compact new system is presented, together with performance tests at a proton-proton centre-of-mass energy of 13 TeV. Firmware and software developments for the operation and validation of the Global Trigger will also be discussed.

Speaker: Johannes Wittmann (Austrian Academy of Sciences (AT))

TWEPP2016_Poster_Wittmann_final.pdf

138 Readout and Trigger for the AFP Detector at ATLAS Experiment

AFP, the ATLAS Forward Proton consists of silicon detectors at 205 m and 217 m on each side of ATLAS. In 2016 two detectors in one side were installed. The FEI4 chips are read at 160 Mbps over the optical fibers. The DAQ system uses a FPGA board with Artix chip and a mezzanine card with RCE data processing module based on a Zynq chip with ARM processor running Linux.
In this contribution we give an overview of the AFP detector with the commissioning steps taken to integrate with the ATLAS TDAQ. Furthermore first performance results are presented.

Speaker: Martin Kocian (SLAC National Accelerator Laboratory (US))

afpposter_v3.pdf

139 A Prototype for an Artificial Retina Processor Aimed at Reconstructing Tracks at the LHC Crossing Rate

We present the results for the prototype of a processor capable of reconstructing events in a silicon strip tracker at about 1 MHz rate with sub-microsecond latency. The processor is based on an advanced pattern-recognition algorithm, called “artificial retina”, inspired to the vision system of the mammals. We design and implement this processor on a DAQ board designed to run at 1 MHz event rate. This is the first step towards a real-time track reconstruction system working at the nominal collision rate of LHC.

Speaker: Riccardo Cenci (SNS and INFN-Pisa, Italy)

140 Pulsar IIb Design, System Integration and Next-Generation Full Mesh ATCA Backplane Test Results

The Pulsar IIb is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs. In this talk we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from different vendors, how the full-mesh is used for data transfer, how the inter-shelf and intra-shelf synchronization works and the experience gained throughout this process.

Speaker: Zijun Xu (Peking University (CN))

TWEPP_Poster_2016-09-22.pdf

141 Processing of the Liquid Xenon Calorimeter’s Signals for Timing Measurements

For identification of neutron-antineutron pair production events in the CMD-3 experiment (BINP, Russia) near threshold is necessary to measure the particles flight time in the LXe-calorimeter with accuracy of about 3ns. The duration of charge collection to the anodes is about 5mks, while the required accuracy of measuring of the signal arrival time is less than 1/1000 of that. Besides, the signal shapes differ substantially between events, so the signal arrival time is measured in two stages. To implement that, a developed special electronics performs waveform digitization and OnLine measurement of signals' arrival times and amplitudes.

Speaker: Leonid Epshteyn (Budker Institute of Nuclear Physics)

142 A Neural Network on FPGAs for the z-Vertex Track Trigger in Belle II

Background originating from events outside of the interaction point is going to play a major role in the upcoming Belle II experiment. In order to reduce this background a track trigger based on the reconstruction of an event's z position is employed on FPGAs. This paper presents the architecture and implementation of neural networks and supporting preprocessing that is going to be used at the upcoming cosmic ray test of Belle II. Using hit information from simulations figures of merit like latency, accuracy and resource demand are presented.

Speaker: Steffen Baehr (Karlsruhe Institute of Technology)

A Neural Network on FPGAs for the z-Vertex Track.pdf

143 Tile Rear Extension Module for the Phase-I Upgrade of the ATLAS L1Calo PreProcessor System

After the Phase-I ATLAS upgrade the Tile calorimeter will have to provide its data via fast optical links to the new Feature Extractor (FEX) modules of the L1Calo trigger system. In order to provide the FEXes with digitised Tile data, new Tile Rear Extension (TREX) modules need to be developed and installed in the existing L1Calo PreProcessor system. The TREX modules are highly complex PCBs, with state-of-the-art FPGAs and high-speed optical transmitters working at rates up to 14 Gbps. The prototype design of TREX and first corresponding test results will be presented.

Speaker: Victor Andrei (Ruprecht-Karls-Universitaet Heidelberg (DE))

ATL-COM-DAQ-2016-106.pdf

144 A High-Speed DAQ Framework for Future High-Level Trigger and Event Building Clusters

Modern data acquisition and trigger systems require a throughput of several GB/s and latencies down to the microsecond level. In order to satisfy such requirements, we developed a heterogeneous system with FPGA-based readout cards and GPU-based computing nodes coupled by fast links. Remote DMA engines are used for direct communication between Xilinx FPGAs and GPUs from AMD / "DirectGMA" and NVIDIA / "GPUDirect". Scalability is ensured by InfiniBand interconnects using the same technologies. In this contribute we present the system architecture and we compare the performance of the different solutions in terms of data throughput and latency.

Speaker: Michele Caselle (KIT - Karlsruhe Institute of Technology (DE))

18:30 Conference Dinner

Thursday, 29 September

Invited Talk: P. Moreira, CERN

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

145 Radiation hard High-Speed Optical Links for HEP

Optical links are ubiquitous in particle physics data acquisition systems spanning experiment control, data-acquisition and trigger applications. With today’s computing power, future data acquisition systems could benefit from collecting data from large segments of the detectors and involve them in trigger systems. This places challenges on optical links for High Energy Physics requiring high data-rate and low-power consumption components. The HL – LHC upgrade radiation will be 10 times higher than in the LHC environment requiring careful choice and qualification of ASIC technologies. In this talk the LHC links will be reviewed and current developments for the HL – LHC upgrade discussed.

Speaker: Paulo Rodrigues Simoes Moreira (CERN)

v2moreiraTWEPP2016.09.29.0900.pdf

v2moreiraTWEPP2016.09.29.0900.pptx

ASIC

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

146 A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 $\mu m$ technology for the ALICE Inner Tracking System front-end ASIC.

The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 um process from TowerJazz. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process.

The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

Speaker: Giovanni Mazza (INFN Torino (IT))

TWEPP2016-GMazza-ID35.pdf

Systems, Planning, installation, commissioning and running experience

Convener: Gregory Michiel Iles (Imperial College (GB))

147 The ATLAS Level-1 Topological Trigger Design and Operation in Run-2

The ATLAS Level-1 Trigger system performs event selection using data from calorimeters and the muon spectrometer to reduce the LHC collision event rate down to about 100 kHz. Trigger decisions from the different systems are combined in the Central Trigger Processor for the final Level-1 decision. A new FPGAs-based AdvancedTCA sub-system was introduced to calculate in real time complex kinematic observables: the Topological Processor System. It was installed during the shutdown and commissioning started in 2015 and continued during 2016. The design and operation of the Level-1 Topological Trigger in Run-2 will be illustrated.

Speaker: Olga Igonkina (Nikhef National institute for subatomic physics (NL))

igonkina.pdf

Optoelectronics and Links

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

148 Optical Link for Detector Instrumentation: In-Detector Multi-Wavelength Silicon Photonic Transmitter

We report on our recent progress in developing an optical transmission system based on wavelength division multiplexing (WDM) to enhance the read-out data rate of future particle detectors. The design and experimental results of the prototype of a monolithically integrated multi-wavelength transmitter are presented as well as temperature studies of electro-optic modulators and optical (de-)multiplexers. Furthermore, we show the successful permanent coupling of optical fibers to photonic chips, which is an essential step towards packaging of the opto-electronic components.

Speaker: Djorn Karnick (Karlsruhe Institute of Technology (KIT))

karnick_twepp2016.pdf

Trigger

Convener: Gregory Michiel Iles (Imperial College (GB))

149 The CMS Barrel Muon Trigger Upgrade

The increase of luminosity expected by LHC during Phase1 will impose several constrains for rate reduction while maintaining high efficiency in the CMS Level1 trigger system. The TwinMux system is the early layer of the muon barrel region that concentrates the information from different subdetectors: DT, RPC and HO. It arranges and fan-out the slow optical trigger links from the detector chambers into faster links (10 Gbps) that are sent to the track finders. Results, from collision runs, that confirm the satisfactory operation of the trigger system up to the output of the barrel track finder, will be shown.

Speaker: Andrea Triossi (CERN)

Triossi_twepp16.pdf

10:40 Coffee Break

Optoelectronics and Links

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

150 Versatile Link PLUS Transceiver Development

The Versatile Link PLUS project (VL+) targets the phase II upgrades of the ATLAS and CMS experiments. It will develop a radiation resistant optical link, operating at up to 10Gbps in the upstream and 5Gbps in the downstream directions with a smaller footprint and higher channel count than its predecessor. A low-profile package is being developed that allows volume production at reduced costs, but which nevertheless can be configured at assembly time to suit the individual needs of different detectors. This paper describes the development strategies and summarizes the status of the feasibility demonstration phase of the project.

Speaker: Csaba Soos (CERN)

VLplus_TWEPP2016_v2.pdf

151 High speed electrical transmission line design and characterisation

Many experiments require high data rates, implying custom link design using transmission line theory.

Transmission line theory is presented including FEA analysis of energy dissipation in exemplar designs. The choice of transmission line designs are reviewed.

Transmission line design principals and testing equipment are presented. The characterisation techniques of time-domain reflectometry and frequency-domain measurements are discussed and compared.

Bit-error-rate testing is presented and its limitations for design discussed. Finally, the gains in error free transmission rates due to signal equalization that corrects for signal degradation, including; pre-emphasis, CTLE or adaptive methods, is given.

Speaker: Leyre Flores Sanz De Acedo (University of Glasgow (GB))

Leyre_Flores_TWEPP_2016.pdf

Leyre_Flores_TWEPP_2016.pptx

152 The 10G TTC-PON: Challenges, Solutions and Performance

The TTC-PON (Timing, Trigger and Control system based in passive optical networks) was first investigated in 2010 in order to replace the current TTC system, responsible for delivering the bunch clock, trigger and control commands to the LHC experiments. A new prototype of the TTC-PON system is now proposed, overcoming the limitations of the formerly presented solutions. A new upstream data transmission scheme relying on longer bursts is described, together with a high-resolution calibration procedure for aligning bursts in a time division multiplexing access. An error correction scheme for downstream data transmission is also depicted.

Speaker: Eduardo Brandao De Souza Mendes (CERN)

TTC-PON_TWEPP2016_EMendes_29_09_16.pdf

Trigger

Convener: Gregory Michiel Iles (Imperial College (GB))

153 The Trigger Readout Electronics for the Phase-I Upgrade of the ATLAS Liquid Argon Calorimeters

LHC is planned to run at high luminosity during Run 3 from 2021 through 2023. In order to improve the identification performance for electrons, photons, taus, jets, missing energy at high background rejection rates, a new trigger readout system is being designed to process the signals with higher spatial granularity. The LAr Trigger Digitizer Board (LTDB) that will process 320 Super Cells signals is being developed. In this paper, results of the 64-channel LTDB and LTDB pre-prototype will be presented. Progress of development of the LTDB prototype for the final trigger readout system will be discussed as well.

Speaker: Hao Xu (BNL)

Hao_Xu1.pdf

154 An FPGA based track finder at Level 1 for CMS at the High Luminosity LHC

A new CMS Tracker is under development for the High Luminosity LHC from 2025. It includes an outer tracker based on "PT-modules" which will construct stubs, built by correlating clusters in two closely spaced sensors. Reconstruction of tracks from stubs is required if the tracker is to contribute to the Level1 trigger under increased luminosity. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented. Results from a hardware demonstrator system, where a slice of the track finder has been constructed to help gauge the performance of a full system, will be included.

Speaker: Mark Pesaresi (Imperial College Sci., Tech. & Med. (GB))

Mark_Pesaresi.pdf

Mark_Pesaresi.pptx

155 ProtoPRM: An FPGA-Based High Performance Associative Memory Pattern Recognition Mezzanine

Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track finding algorithms, particularly for silicon based tracking triggers. In the talk we present our latest PRAM-based pattern recognition mezzanine card design which supports both ASIC and FPGA based PRAMs, and describe how the PRAM interface and FPGA firmware modules work in conjunction to implement a high performance fully pipelined low latency track finding engine. This work is part of the overall program for Level-1 silicon-based tracking trigger generic R&D for high luminosity LHC.

Speaker: Jamieson Olsen (Fermi National Accelerator Lab. (US))

2016-09-29_protoPRM.pdf

12:25 Lunch

Invited Talk: K. Meier, University of Heidelberg

Convener: Alessandro Marchioro (CERN)

156 Neural hardware architectures for spatio-temporal data processing

The brain is characterized by extreme power efficiency, fault tolerance, compactness and the ability to develop and to learn.
It can make predictions from noisy and unexpected input data. Any artificial system implementing all or some of those features is likely to have a large impact on the way we process information. With the increasingly detailed data from neuroscience and the availability of advanced VLSI process nodes the dream of building physical models of neural circuits on a meaningful scale of complexity is coming closer to realization. Such models deviate strongly from classical processor-memory based numerical machines as the two functions merge into a massively parallel network of almost identical cells. The lecture will introduce current projects worldwide and discuss computational principles suited for the analysis of spatio-zemporal patterns in large data volumes.

Speaker: Karlheinz Meier

Radiation tolerant components and systems

Convener: Salvatore Danzeca (CERN)

157 Application of flash-based field-programmable gate arrays in high energy experiments

Field-programmable gate arrays (FPGAs) based on flash memories provide a high radiation tolerance. We discuss potential application of the Microsemi IGLOO2 FPGAs in high energy experiments. We implement a 24 channel time-to-digital converter with a time binning of 0.78 ns and evaluate the performance. The time resolution is obtained to be 0.25 ns. The radiation tolerance against total ionizing dose is studied by irradiating gamma ray up to 10 kGy using Cobalt-60 source. The degradation of the performance on the ring oscillator, the phase-locked loop, and the high-speed transceiver is evaluated.

Speaker: Yuta Sano (Nagoya University (JP))

TWEPP2016_v6.pdf

158 Total Ionizing Dose effects on a 28nm Hi-K metal-gate CMOS technology up to 1 Grad

This paper presents the results of an irradiation campaign up to 1 Grad on single transistors manufactured in a 28nm commercial CMOS technology. This technology is of interest for future upgrades for HL-LHC. NMOS transistors have been irradiated and electrical parameters have been measured. Moderate threshold voltage shift and sub-threshold slope degradation have been observed, while leakage current shows an increase of 3-4 orders of magnitude. These measurements are significant as this is the first technology evaluated for HEP applications using a High-K dielectric material for the transistor gate

Speaker: Serena Mattiazzo (University of Padova (IT))

TWEPP2016_Mattiazzo.pdf

TWEPP2016_Mattiazzo.pptx

159 First studies on AMS H35 CMOS devices for application in the ATLAS tracker upgrade

H35Demo chips are HV-CMOS devices produced in the 350nm AMS technology with the purpose of inquiring the opportunity to introduce this technology in the next ATLAS tracker upgrade. Each chip includes four different pixel matrices and three test structures. The results of TCT (Transient Current Technique) and edge-TCT analysis on the test structures from with different substrate resistivity before and after irradiation will be shown. Also the first results from the stand alone readout of the monolithic matrices will be shown.

Speaker: Emanuele Cavallaro (IFAE - Barcelona (ES))

Cavallaro_TWEPP.pdf

Trigger

Convener: Julie Whitmore (Fermi National Accelerator Lab. (US))

160 Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade

In Run 3, the ATLAS Level-1 Calorimeter Trigger will be augmented by an Electron Feature Extractor (eFEX), to identify isolated e/g and t particles, and a Jet Feature Extractor (jFEX), to identify energetic jets and calculate various local energy sums. Each module accommodates more than 420 differential signals that can operate at up to 12.8 Gb/s, some routed over 20 cm between FPGAs. Presented here are the module designs, the processes that have been adopted to meet the challenges associated with multi-Gb/s PCB design, and the results of tests that characterise the performance of these modules.

Speaker: Weiming Qian (STFC - Rutherford Appleton Lab. (GB))

ATL-COM-DAQ-2016-108.pdf

ATL-COM-DAQ-2016-108.pptx

161 Real Time FPGA Design for the L0 Trigger of the RICH Detector of the NA62 Experiment at CERN SPS

The NA62 experiment aims to measure rare kaon decays, in order to precisely test the standard model. The RICH detector of the experiment is instrumental in charged-particle identification and in measurement of their crossing time, with a resolution better than 100ps. Here we describe the design of the Level-0 trigger system for the RICH, which provides a precise time reference by counting the input hit multiplicity within programmable fine-time windows. Because the design doesn’t use spatial information and stands the maximum input rate of TDC-based NA2 systems, it can be employed also in other detectors.

Speaker: Mattia Barbanera (Universita e INFN, Perugia (IT))

RICH_L0_Barbanera.pdf

RICH_L0_Barbanera.pptx

162 Evaluation of GPUs for High-Level Triggers in High Energy Physics

Modern High Energy Physics Trigger Systems require high data throughput on the Gigabyte scale and latencies in the range of a few microseconds.
Traditionally, those requirements could only be met by expensive, dedicated hardware like FPGAs and ASICs.
However, GPUs provide high-performance and pose an affordable and easily programmable alternative.
In this paper we evaluate modern GPGPUs as a flexible alternative to traditional approaches.
We discus the performance, throughput and latency of commonly used algorithms and give an overview of possible benefits as well as downsides of this approach.
Finally, we give a brief outlook of possible future developments.

Speaker: Hannes Heiner Mohr (KIT - Karlsruhe Institute of Technology (DE))

TWEPP2016_white.pdf

16:05 Coffee Break

WG 1: xTCA

Convener: Markus Joos (CERN)

163 Welcome

Speaker: Markus Joos (CERN)

xTCA-IG.pdf

xTCA-IG.pptx

164 Design of an AdvancedTCA board Management Controller Solution

Speaker: Julian Maxime Mendez (CERN)

xTCA Meeting group - 29-09-16 - v2.pdf

xTCA Meeting group - 29-09-16 - v2.pptx

165 Proposal of a specification for ATCA shelves used in experiments at CERN

Speaker: Vincent Bobillier (CERN)

xTCA_IG_Sep2016_ATCA_specs.pdf

xTCA_IG_Sep2016_ATCA_specs.pptx

166 Present and future xTCA developments in CMS DAQ group

Speaker: Attila Racz (CERN)

RACZ_twepp_utca_session.pdf

RACZ_twepp_utca_session.ppt

167 A generic software component enabling communication between IP-Bus and OPC-UA

Speaker: Piotr Nikiel (CERN)

168 The use of ATCA in CMS at the HL-LHC

Speaker: Eric Shearer Hazen (B)

Hazen_ATCA_CMS.pdf

169 Discussion

WG 3: FPGA

Conveners: Ken Wyllie (CERN), Salvatore Danzeca (CERN)

170 Introduction

Speakers: Ken Wyllie (CERN), Salvatore Danzeca (CERN)

FPGA_WG_intro.pdf

FPGA_WG_intro.pptx

171 FPGAs in radiation: Recent results from Kintex7

Speaker: Vlad-Mihai Placinta (Horia Hulubei National Institute of Physics and Nuclear Enginee)

Kintex-7 irradiation results IFIN-HH.pdf

172 FPGAs in radiation: Recent results from Artix7

Speaker: Rudy Ferraro (Universite Montpellier II (FR))

TWEPP_Artix7.pdf

173 FPGAs in radiation: Recent results from SmartFusion2

Speaker: Nikolaos Trikoupis (CERN)

TRIKOUPIS-ResultsFromSmartFusion2IrradiationAtCHARMCERN.pdf

TRIKOUPIS-ResultsFromSmartFusion2IrradiationAtCHARMCERN.pptx

174 GBT-FPGA tutorial

Speaker: Julian Maxime Mendez (CERN)

GBTTutorial - TWEPP2016.pdf

GBTTutorial - TWEPP2016.pptx

Friday, 30 September

Plenary: Trigger

Convener: Julie Whitmore (Fermi National Accelerator Lab. (US))

175 The CMS Level-1 Calorimeter Trigger for LHC Run II

Results from the completed Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed in two stages, with the first running in 2015 for pp and Heavy Ions and the final stage for 2016 data-taking. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Stages of the upgrade were commissioned in parallel with the previous trigger. Innovations were evaluated, such as embedded linux on trigger processing boards and simultaneous eye-scans on data links. The final stage architecture is time-multiplexed.

Speaker: Alexandre Zabi (Centre National de la Recherche Scientifique (FR))

Twepp2016_AZabi_CalorTrigger_final.pdf

176 Installation, Commissioning, and Running of the ATLAS Fast Tracker Hardware System

The ATLAS detector at the LHC is in the process of integrating new components to handle the increased collision energies and luminosities being delivered since 2015. The Fast TracKer (FTK) is a hardware processor built to reconstruct tracks at a rate of up to 100 kHz and provide them to the high level trigger. FTK uses FPGA's to match inner detector hits with pre-defined track patterns stored in associative memory on custom ASICs. This presentation describes the electronics facilitating FTK’s massive parallelization alongside the planned installation and commissioning of the system during 2016.

Speaker: Nikolina Ilic (Stanford University (US))

FTKTWEPPFinal.pdf

Plenary: ASIC

Convener: Alessandro Marchioro (CERN)

177 TOFFEE: a fully custom amplifier-comparator chip for timing applications with silicon detectors.

In this contribution we present the design of a 8-channel amplifier-comparator chip specifically optimized to match the signals produced by Ultra-Fast Silicon Detectors (UFSD). The time resolution of the TOFFEE – UFSD system is expected to be around 30 ps. The chip is designed in UMC 110nm CMOS technology, it has a 2x2 mm area and it requires 40 mW per channel. It features LVDS outputs and the signal dynamic range matches the requirements of the HPTDC system.

Speaker: Francesca Cenna (Universita e INFN Torino (IT))

toffee_twepp2016.pdf

toffee_twepp.pdf

178 The VeloPix ASIC

The LHCb upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in triggerless mode, with full event selection being performed offline. The Vertex Locator (VELO) will be upgraded to a pixel device with a new dedicated ASIC, the VeloPix, a 130 nm technology chip with data driven and zero suppressed readout. The sensors are positione at just 5.1 mm from the LHC beams and the hottest ASICs will experience rates of more than 900 Mhits/s. The recently submitted ASIC will be presented along with the first test results.

Speaker: Tuomas Sakari Poikela (CERN)

TWEPP_2016_The_VeloPix_ASIC_Tuomas_Poikela_.pdf

10:40 Coffee Break

Plenary: ASIC

Convener: Alessandro Marchioro (CERN)

179 AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

This paper describes the AM06 chip, a highly parallel processor for
pattern recognition in high energy physics. AM06 contains memory banks
that store up to 2^17 patterns made up of 8x18 bit words and integrates
SER/DES IP blocks for 2.4 Gb/s IO to avoid routing congestion.
AM06 combines custom memory arrays, standard logic cells and IP blocks
within a 168 mm^2 silicon area with 421 million transistors and can
perform bitwise comparisons at 1.6 Pbit/s, consuming ~2 fJ/bit per
comparison thanks to an optimized design based on XORAM cells.

Speaker: Valentino Liberali (Università degli Studi e INFN Milano (IT))

TWEPP2016_Liberali.pdf

180 Rad-hard DCDC converters for HL-LHC experiment's tracker modules power distribution

In the context of investigating a more efficient rad-hard power distribution scheme for HL-LHC trackers modules based on switching DC/DC converters, we developed two new prototypes, upFEAST2 and DCDC2S. The combination of upFEAST2 and two DCDC2S can provide the three required voltages (2.5V for the opto-electronics, 1V for digital and 1.2V for analog circuitry).
DCDC2S and upFEAST2 are manufactured with commercial 0.13um and 0.35um high voltage CMOS technology respectively. Design techniques, functional and radiation tests of the prototypes will be discussed.

Speaker: Giacomo Ripamonti (CERN, Ecole Polytechnique Federale de Lausanne (CH))

Ripamonti_TWEPP2016.pdf

CLOSE OUT

Convener: Alessandro (CERN) Marchioro (CERN)

12:25 Lunch

Tutorial: Microelectronics Reliability (G. Groeseneken, IMEC)

Convener: Alessandro Marchioro (CERN)

181 Reliability and failure mechanisms of Integrated Circuits and devices

When scaling down CMOS towards smaller and smaller dimensions, the electrical fields inside the devices is increasing which leads to potential failures of the transistors. This can limit the lifetime of the circuits that are made in these technologies. As a result reliability is becoming more and more a fundamental limiting factor for the further downscaling of the technology. This lecture explains the main failure mechanisms that are acting at transistor level with focus on Time-dependent dielectric breakdown, Bias-temperature Instability and to a lesser extent also Hot carrier degradation. The basics as well as the test structures and characterization techniques needed to quantify the degradation, the voltage and temperature acceleration models and ways to cope with the problem and to improve the lifetime.

Speaker: Guido Groeseneken (IMEC)

FEOLreliability-Karlsruhe-Groeseneken.pdf