The workshop covers all aspects of electronic systems, components and instrumentation for particle and astro-particle physics such as: electronics for particle detection, triggering, data-acquisition systems, accelerator and beam instrumentation.
Operational experience in electronic systems and R&D in electronics for LHC, High Luminosity LHC, FAIR, neutrino facilities and other present or future accelerator projects are the major focus of the workshop.
The purpose of the workshop is:
- Present original concepts and results of research and development for electronics relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities;
- Review the status of electronics for running experiments and accelerators;
- Identify and encourage common efforts for the development of electronics;
- Promote information exchange and collaboration in the relevant engineering and physics communities.
The main topics of the workshop will be recent research and developments in the following areas:
- Highly integrated detectors and electronics;
- Custom Analogue and Digital Circuits;
- Programmable Digital Logic Applications and Verification;
- Optoelectronic Data Transfer and Control;
- Packaging and Interconnect Technologies;
- Radiation and Magnetic Field Tolerant Systems;
- Testing and Reliability;
- Power Management and Conversion;
- Grounding and Shielding;
- Design Tools and Methods.
The workshop programme will include invited plenary talks, sessions for oral presentations, poster presentations.
Information about registration to the workshop and local organisation is available at: https://www.ppe.gla.ac.uk/twepp24
Authors are invited to submit abstracts and summaries describing original developments and new contributions, including recent progress, in the workshop topic areas.
Abstracts (max. 100 words long) and summaries (max. 500 words long) along an optional file containing diagrams or plots must be submitted through the Integrated Digital Conference tool at https://indico.cern.ch/e/twepp2024.
The summary will be the basis for paper selection. The summary should describe quantitative specifications of the work, challenges, implementation and results.
Submissions without comprehensive summaries will not be considered. Submissions directly from the presenters are encouraged. Summaries should clearly describe the aspects of the work relevant to the topics of TWEPP. Standard summaries targeted to physics or detector instrumentation conferences might need to be updated accordingly.
The submission deadline is 30 April 2024.
*** No extensions are foreseen ***
Abstracts will be made available at the time of the workshop and will include all contributions selected for either oral or poster presentation.
The proceedings of the workshop will be published in the peer-reviewed journal of Instrumentation, JINST.
Information concerning the workshop scientific programme and submissions is available at: https://indico.cern.ch/e/twepp2024
Enquiries can be directed to the Workshop Secretariat, by email at twepp@cern.ch
Local organisation information is be available on https://www.ppe.gla.ac.uk/twepp24
Enquiries concerning the local organisation can be directed to the local organisation committee, by email at phas-twepp24@glasgow.ac.uk
Scientific organisation
A. Kluge (CERN, CH, Chair)
J. Alme (UIB, NO)
S. Baron (CERN, CH)
R. Bates (University of Glasgow, UK)
A. Boccardi (CERN, CH)
H. Chen (BNL, US)
S. Danzeca (CERN, CH)
C. Fernandez Bedoya (CIEMAT, ES)
M. French (RAL, UK)
D. Gascon (UB, ES)
P. Gui (SMU, US)
M. Hansen (CERN, CH)
C. G. Hu (IPHC-IN2P3, FR)
D. Maneuski (University of Glasgow, UK)
G. Lehmann Miotto (CERN, CH)
A. Ricci (CERN, CH, Secretary)
A. Rivetti (INFN, IT)
W. Snoeys (CERN, CH)
F. Vasey (CERN, CH)
K. Wyllie (CERN, CH)
Organised by University of Glasgow – School of Physics and Astronomy with support from the European Organization for Nuclear Research (CERN).
With over 6 million channels, the High Granularity Calorimeter (HGCAL) for the CMS HL-LHC Upgrade presents a unique data challenge. The ECON ASICs provide critical on-detector data reduction for the 40 MHz trigger path (ECON-T) and 750 kHz data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65nm CMOS, are rad-tolerant (600 Mrad) with low power consumption (<2.5 mW/channel). This presentation is the first comprehensive description of the ECON designs, first functionality and radiation tests for the ECON-T ASIC, and first high statistics characterization results from the full production of 75k ECON-D and ECON-T ASICs.
The High-Granularity Calorimeter (HGCAL) of CMS will undergo a major upgrade during the Long-Shutdown 3. The Endcap Concentrators (ECON) ASICs represent key elements in the readout chain, processing trigger (ECON-T) and data (ECON-D) streams from the HGCROC to the LpGBT. The ECONs will operate in a radiation environment with a High-Energy Hadron (HEH) flux of $3\cdot10^{6} cm^{-2}s^{-1}$.
This contribution describes the Universal Verification Methodology (UVM)-based functional verification of the ECON ASICs focusing on the re-use of existing components to manage the complexity of the verification environment.
Many high-energy physics experiments require high-data-rate links between readout ASICs and digital back-end processors over lossy channels, such as radio-pure cables. The preferred solution uses a forwarded clock architecture in which the back-end transfers a low-frequency reference clock (e.g., from a crystal oscillator) to the readout system over a low-speed cable, which is then used by a frequency synthesizer to generate the high-frequency data-rate clock. Here we describe an integer-N synthesizer in 65nm CMOS technology suitable for such applications. The circuit can be programmed to generate low-jitter clocks between 30MHz and 4GHz that are locked a 10-50 MHz reference input.
The ATLAS experiment requires a high-precision bunch clock distribution for the High-Luminosity upgrade of the Large Hadron Collider. A new trigger and timing distribution system based on FPGA transceivers and high-speed serial links will replace the existing one. In preparation for this upgrade, we characterized the clock phase uncertainty of AMD UltraScale+ transceivers after reset. We found the performance of the GTH type to be adequate, and we implemented a workaround to correct the behavior of the GTY type receiver. In addition, we extensively studied the effect of silicon temperature variations on the phase and implemented a compensation algorithm.
Picosecond-level phase determinism in timing distribution systems is a requirement for future detectors in High Energy Physics. FPGA transceivers traditionally used to propagate timing do not meet by default this stringent requirement, and suffer from phase jumps at startup and temperature drifts. While ad-hoc solutions have been developed based on particular FPGA features to measure phase shifts and to apply phase corrections, they remain FPGA specific and therefore cannot be generalized to any type of timing link. This paper presents a study of discrete components for phase shifting and monitoring, allowing the implementation of a generic deterministic link.
The LHC RF and Timing Distribution backbone is being upgraded for the HL-LHC. A White Rabbit technology solution for the generation and the distribution of the RF, similar to the system currently employed in SPS, is being considered. To verify its suitability from a phase stability perspective, an investigation was conducted on a proof-of-concept system. The requirement for the end-nodes is ± 1 degree of the 200 MHz SPS RF frequency. The key figure of merit to check compliancy is peak-peak phase variation which must be < 28 ps. The compliance tests campaign will be described, and results presented.
The UK was the first to have a National Quantum Technology Programme with the aim of building practical systems that use quantum superposition, entanglement or squeezing to produce new sensors and clocks with improved accuracy over present commercial systems. Many other countries have followed with their own quantum technology programmes either to build quantum computers or to develop quantum technology for civilian applications. Atomic clocks were first produced in the 1950s and most accurate atomic clocks are still large systems that have to be operated inside temperature controlled laboratories. For many practical civilian applications, sensors and clocks have to be significantly smaller with reduced size, weight, power, mass and cost. I will present work using micro- and nano-fabrication techniques aiming to make a range of practical and far smaller quantum sensors and miniature atomic clocks with far greater accuracy than present commercially available systems. Examples of chip-scale atomic clocks, optically pumped magnetometers and inertial sensors will be presented and a number of the potential applications discussed. The work demonstrates how cold atoms can be produced inside miniature MEMS vapour systems which is an enabling technology for many cold atom clocks and sensors. The magnetometers can be used for navigation or for magnetoencephalography (magnetic imaging of the brain). Gravimeters made using cold atoms and from MEMS sensors will be presented with examples of field trails on boats for navigation, for water table monitoring to predict flooding and trying to measure magma changes in volcanoes to predict when volcanoes might erupt.
Douglas Paul has an MA degree in Physics and Theoretical Physics and a PhD from the Cavendish Laboratory, University of Cambridge.
He presently holds a Royal Academy of Engineering Research Chair in Emerging Technologies at the University of Glasgow. He previously held an EPSRC Quantum Technology Fellowship awarded to provide leadership for the UK Quantum Technology Programme and an EPSRC Advanced Research Fellowship. He was the first Director of the James Watt Nanofabrication Centre at Glasgow.
Doug is a Fellow of the Royal Society of Edinburgh, Fellow of the Institute of Physics, a chartered physicist, a chartered engineer and a Senior Member of the IEEE. He was the recipient of the Institute of Physics President's Medal in 2014.
Doug's research uses micro-fabrication and nano-fabrication approaches to produce practical quantum technology systems for applications including position, navigation, timing, LiDAR, quantum imaging, memories, gravity imaging, sensing and secure communications. He has supervised over 30 PhD students and 29 post doctoral researchers in Cambridge and Glasgow.
He has been principal investigator on over £74M of collaborative grants which included 10 Innovate UK grants with UK industry over the past 5 years and has multiple research contracts from industry. He is a partner in 3 of the 4 UK Quantum Technology Hubs and leads an EPSRC Programme Grant to build a Quantum Navigator.
Doug frequently gives outreach talks to the public at a range of events around the UK and annually gives invited presentations at many international conferences.
He presently sits on a number of government department committees and previously sat on the Home Office CBRN Scientific Advisory Committee, MOD Defence Science Advisory Council and MOD Defence Science Expert Committee. He was the U.K. representative to the NATO CBP Science Panel and presently sites on the EPSRC Scientific Advisory Teams for Infrastructure and ICT.
When not working Doug can frequently been seen out with the family or on a bicycle on the hills and paths around Glasgow. He still tries to find time to play the piano as well as keeping abreast of good wines after being a Wine Steward at St Edmund's College for many years.
As front-end ASIC complexity in HEP experiments grows, there is a shift towards more modular, programmable, and cost-effective designs. This work introduces the SOCRATES platform, a radiation-tolerant SoC generator toolset, centered on SoCMake, a hardware/software build system that automates SoC assembly and verification. Utilizing existing IP blocks, SoCMake generates the interconnects and the software framework to run application code. The platform includes radiation-tolerant IPs and supports fault-tolerant extensions for redundancy and error correction. A prototype ASIC based on the RISC-V Ibex processor, created using SOCRATES in a 28nm CMOS process, validates the toolset through SEE and TID testing.
In response to the need for higher timing resolution innovative readout schemes are being explored for silicon vertex detectors like being under development ALICE ITS3 and EIC ePIC SVT. A promising direction is the event-driven approach, exemplified by the EDWARD (Event-Driven With Access and Reset Decoder) architecture. This presentation will highlight the capabilities of the EDWARD65P1 test ASIC, which includes a digital event generator to generate uncorrelated hits at varying rates. For the first time presented at TWEPP 2021, EDWARD has been shown operational, offering substantial improvements in timing resolution and setting new benchmarks for asynchronous readout systems.
High pileup densities imply new challenges. In this context, 4D tracking with a timing resolution of ~10ps is essential for track reconstruction. For Muon Colliders, precise timing information becomes indispensable to mitigate the Background Integrated Beam (BIB). Therefore, a high-precision Time-To-Digital (TDC) stands as a crucial component in realizing 4D tracking. In 2023, we introduced the design of a 4-channel sub-10ps TDC ASIC fabricated using 28nm CMOS technology. This presentation highlights resolved technical issues since the initial design as well as the characterization setup and test outcomes.
For the High-Luminosity Large Hadron Collider era, the trigger and data acquisition system of the Compact Muon Solenoid experiment will be entirely replaced. Novel design choices have been explored, including ATCA platforms with SoC controllers and interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger data analysis will be performed through sophisticated algorithms, including widespread use of Machine Learning, in large FPGAs, such as the Xilinx Ultrascale family. The system will process over 50 Tb/s with a selection rate of 750 kHz. The system design and prototyping are described and examples of trigger algorithms reviewed.
The Overlap Muon Track Finder (OMTF) is one of the subsystems of the CMS L1 Trigger. For the High-Luminosity Large Hadron Collider era (CMS phase-2 upgrade), a new version of the OMTF is currently under development. This upgraded version will be implemented on a custom ATCA board X2O, which houses a Xilinx UltraScale+ FPGA and 25 Gbps optical transceivers. This contribution focuses on the firmware implementation of the muon trigger algorithm and input data pre-processing, leveraging High-Level Synthesis (HLS) technique. The current design and verification results and experience in using both standard and non-standard HLS development workflow are presented.
The FAST3 (Fast Amplifier for Silicon detector for Timing) is a low noise 16-channel ASIC, belonging to the FAST ASIC family. FAST3 has been implemented in UMC 110 nm CMOS technology, and the design has been optimized for the read-out of 50µm-thick LGAD (Low-Gain Avalanche Diode). The figure of merit of FAST3 is the excellent temporal jitter below 20ps in a wide dynamic range of input charge (from 5 up to 60 fC of charge). This contribution presents the characterization of FAST3 in the laboratory and at test beams.
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to ~ 40-50ps per hit. The ETROC2 is the first full size prototype design fully compatible with the final chip specifications for CMS ETL. The ETROC2 chips have been extensively tested over the past year since May 2023, with laser, hadron beam at CERN and electron beam at DESY, with temperature vs voltage vs TID scan, with proton beam and heavy ion beam for SEU and wafer probe testing and stress testing using charge injections. The ETROC2 design and test results will be presented.
The IGNITE project develops technical solutions for the next generation of trackers at colliders. It plans to implement an integrated module, comprising sensor, electronics, and fast readout, aimed at fast 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In the present paper we present measurement results concerning the performance of the first-born prototype ASIC, which explores circuital solutions for Analog Front End and Time-to-Digital Converter circuits. Such prototype structures have been tested before being integrated in a subsequent design, containing a 64x64 pixel matrix for the readout of pixelated sensors.
The HL-LHC has motivated a generalized upgrade in electronic systems across all experiments. In the new electronics architecture for the CMS Drift Tubes detector, the trigger generation moves from on-detector ASICs to the back-end, to be carried out by top-range FPGAs. The new algorithm aims to deliver full-resolution, offline-grade performance in the reconstruction of muon segments. To achieve this objective, meeting the latency and data rate requirements, a high-speed, highly-pipelined FPGA design with several optimizations has been developed. This work describes the architecture and performance of this algorithm, as well as the challenges encountered during implementation and the solutions adopted.
Phase-2 CMS will replace the trigger and data acquisition system in preparation for the HL-LHC. This upgrade will allow a maximum accept rate of 750kHz and a latency of 12.5us. To achieve this, new electronics and firmware are being designed. We describe the first version of an algorithm capable of detecting and identifying muon showers, running in the first layer of the trigger system.
It was designed to be implemented on FPGAs with minimum resource utilization, increasing the robustness of the current algorithm. This will allow to recover efficiency compared to the current algorithm at high pt muons.
We report on the development, implementation, and performance of a fast neural network used to measure the transverse momentum in the CMS Level-1 Endcap Muon Track Finder. The network aims to improve the triggering efficiency of muons produced in the decays of long-lived particles. We implemented it in firmware for a Xilinx Virtex-7 FPGA and deployed it during the LHC Run 3 data-taking in 2023. The new displaced muon triggers that use this algorithm broaden the phase space accessible to the CMS experiment for searches that look for evidence of LLPs that decay into muons.
Abstract
In particle physics accelerators remain the key tools for understanding the building blocks of matter and the origin of the universe.
Exploring collisions at even higher energy will enable the investigation of yet smaller and more intricate features. Many feasibility studies for new accelerators reaching the energy frontier are currently under way. These accelerators include both linear and circular collider projects such as ILC, CLIC, FCCee, FCChh, Muon and plasma-based colliders. This talk gives an overview of the future collider concepts, their challenges, technical readiness levels and addresses the requirements for the new detectors.
Biography
Dr. Edda Gschwendtner obtained her PhD in physics from the Vienna University of Technology, Austria, working at CERN on benchmarking the particle background in the LHC ATLAS experiment. During the last 25 years she has contributed significantly to several accelerator and particle physics projects. She was involved in the development of the LHC beam loss detection system, the LHC luminosity detectors and high-resolution detectors for future neutrino factory experiments. She was the responsible beam physicist for the CERN Neutrino Gran Sasso beam, led as liaison physicist the design, commissioning and operation of beam lines from the CERN SPS to the experimental areas and was SPS supervisor, responsible for optimizing the performance of the SPS.
Since 2012 Edda Gschwendtner is the Project Leader of CERN’s plasma wakefield acceleration experiment, AWAKE; This accelerator R&D experiment demonstrated for the first time ever plasma wakefield acceleration of electrons in wakefields driven by a SPS proton bunch and has the aim to bring the R&D development to a point where particle physics applications can be proposed and realized in the near future.
Edda’s area of research involves also Physics Beyond Colliders studies on particle physics applications based on the AWAKE technology.
As co-chair of the “Expert Panel on High-Gradient – Plasma and Laser Accelerators” she was involved in the preparation of a plasma accelerator R&D roadmap for HEP colliders and applications for the European Strategy for Particle Physics.
Edda Gschwendtner is Section Leader of the ‘Lepton Accelerator Facilities’ section at CERN, which is responsible for theoretical, numerical, and experimental studies on the beam dynamics of future lepton accelerators, facilities, and colliders such as FCCee, CLIC and the Muon collider.
Edda is co-author of more than 150 papers and has supervised undergraduate students, PhD students and post-doctoral students, some of them winning PhD thesis prizes and young career awards.
Edda Gschwendtner is Principal Scientist at CERN and is member of several international scientific advisory committees and review panels.
Highly granular precision timing detectors are required to achieve scientific breakthroughs across HEP, NP, BES, and FES. To enable the development of these detectors, 3D-intgration between advanced sensor wafers and scaled CMOS technology nodes is required but is currently cost-prohibitive for use in scientific applications. Closing this technology gap is the joint SLAC, FNAL and LLNL effort pursuing development of LGAD structures compatible with fabrication in commercial 12-inch wafer processes that can be cost-effectively 3D-integrated with high-performance readout ASICs under development. The design of the first ASIC prototype is presented.
The design, testing, system integration and performance of the ATCA processor (APx) boards firmware and software for the Phase 2 CMS trigger upgrade are presented. The 76 boards plus spares comprise the Calorimeter Trigger and half of the Global Track and Correlator Triggers. The production boards are based on the Xilinx VU13P and have 124 25G optical interfaces. A new optical link protocol provides robust performance. Large-scale optical link test results are shown. A full-slice environment for testing algorithms on multiple different boards together has been deployed. Measurements of thermal performance and latency are shown.
MightyPix is the first iteration of a High-Voltage CMOS (HV-CMOS) sensor chip developed for the LHCb Mighty Tracker. The digital readout of this chip is compatible to LHCb specifications. To verify the digital functionality of the chip in an LHCb environment, an emulator has been developed . This setup comprises the FPGA, CERN's developed VLDB, some custom interface boards and support electronics. The emulated design can be used for testing the DAQ chain, firmware and I2C communication between lpGBT and emulated chip. The data transmission from lpgbt to emulated chip over I2C is successfully done and observed on the oscilloscope.
The CMS Collaboration will replace its current endcap calorimeters with a new high granularity calorimeter (HGCAL) for operations at the HL-LHC. The HGCAL back-end DAQ system comprises 96 FPGA-based ATCA boards, each processing data from 108 input optical fibres operating at 10 Gb/s. This paper describes in detail the architecture and prototyping of the elementary readout unit in the back-end DAQ system of the HGCAL. We then describe its integration and performance in a full detector test system. The resulting system provides an average data acquisition throughput at the detector's nominal rate of 750 thousand events per second.
The performance of ASICs for high-bandwidth communications is heavily influenced by the interconnection with the hosting module and paired devices, including the bonding scheme and the PCB layout. The validation campaign of the DART28 high-speed transmitter has highlighted that a coordinated simulation and design of the power delivery network is required to obtain satisfactory performance. In this context, the results obtained from two variants of test-bench board are compared, examining how optimisation of layout and wire-bond placement are reflected in improvements of the serial link characteristics. Electromagnetic simulations support the analysis and provide guidelines for developing the subsequent versions.
We present the design and preliminary test results of a MAPS sensor prototype MIC6_V1 based on a 55nm Quad-well CMOS Image Sensor process for the vertex detector application. In order to achieve high-spatial resolution, fast readout, and low power consumption, MIC6_V1 has implemented a new node-based, data-driven parallel readout architecture. The integration time is 5us, and by sharing VCO in the pixel group, the hit arrival time resolution can reach 10ns. The pixel size of MIC6_V1 is 23.6 μm × 20 μm. The pixel matrix is 64 rows by 64 columns, and the size of MIC6_V1 is 2.8mm × 2.8mm.
The Belle II experiment searches for physics beyond the standard model. Among the intriguing candidates are decays with an offset vertex. However, the current level-1 trigger dismisses these candidates. To address this problem, a new trigger system is required that can identify such decays when they exhibit two tracks from an offset vertex. The approach uses parallel calculations of Hough transforms under different origin hypotheses. The implementation of this Hough transformation must be resource-efficient implemented, especially when the transformation and post-processing are executed multiple times parallel on the trigger FPGA.
Accurate time measurement is essential for future high-energy physics experiments, such as Calorimeters and Time of Flight detectors of the Circular Electron Positron Collider (CEPC). The advancement of detector performance necessitates the need of high-resolution timing circuits. We introduce a ring-oscillator based timing block controlled by a delay locked loop, employing passive interpolation techniques, achieving an average bin-size as low as 5.2 ps in a 55 nm process. The core power consumption is estimated to be less than 30 mW. The prototype design will be submitted soon, and the architecture, key circuits and simulation results will be presented.
The GRAiNITA prototype has been developed as a first step toward the development of a next-generation calorimeter for FCC-ee. To evaluate GRAiNITA performance, a special test bench was built. The principle consists in tracking the cosmic ray muons that pass through the prototype to check the response of it as a function of the region traversed. Wavelength-shifting fibers capture the light emitted when muon particles travel through the crystal and transmit it to silicon photomultiplier detectors. A fast acquisition system is used to count the individual photoelectron. An offline analysis allows one to correlate the tracks with the deposited energy.
This work describes the design, in a 28 nm CMOS technology, of a front-end channel for the readout of pixel sensors in future particle accelerators. The channel being developed leverages the Time-Over-Threshold technique for the numerical conversion of the detector signal amplitude, and includes a low-noise charge sensitive amplifier featuring a compact gain stage architecture. A prototype chip including a matrix of 8x32 readout channels is going to be submitted in Q3-2024. Simulation results for the front-end channel, together with a discussion of the integration of the matrix, are reported in the conference paper
Quality analogue radiation-hardened design in 28nm CMOS is an iterative process best achieved through IP development. Rutherford Appleton Laboratory (RAL) ASIC Design Group has implemented two test-structure ASICs, PURNIX and YELNIX, to validate the performance of circuits up to 1GRAD TID. PURNIX includes essential building-block radiation-hardened IP, while YELNIX includes a prototype LGAD preamplifier and TDC sub-circuit options. Irradiated performance will be evaluated in collaboration with the universities of Birmingham and Oxford. In parallel, we continue our developments with an improved low-voltage amplifier architecture, low-profile 8bit-ADC, <20ps TDC and 25Gbps readout circuits. We present test results and current circuit developments.
At PSI the future standard hardware platform based on CompactPCI-Serial is already widely spread for developments in several applications and is under discussion for use on all our accelerators.
With the focus on cost optimization smaller sub-racks are now part of the toolbox as well as rear boards with a subtle set of interfaces.
Based on the requirements of a Fill-Pattern Monitor for SLS 2.0 there is a near-term development of a CPCI-S front board on the way. Its generic design approach regarding board management and configuration interfaces shall enable easy-access for further application-specific developments.
CosmoLink is a compact coincidence detector comprising two scintillators for portable on-site muon flux measurement. The Scintillators are coupled with wavelength shifting (WLS) fibers for efficient light guiding to Silicon photomultipliers (SiPMs). Each readout channels equipped with a Transimpedance preamp, Discriminator and peak hold circuit. Upon successful coincidence trigger the peak amplitude is digitized using Analog to Digital Converter. The coincidence count and ADC data are acquired using a low cost microcontroller. Multiple detectors can be grouped together like swarms and arranged in different geometry to collect data collectively.The acquired data is wirelessly transmitted to a central server.
Before starting the High-Luminosity Large Hadron Collider (HL-LHC) runs, the CMS detector will be substantially upgraded to cope with the significant increase in instantaneous luminosity. The entire CMS Inner Tracker (IT) detector will be replaced, and the new detector will feature increased radiation hardness, higher granularity, and the capability to handle higher data rates and longer trigger latency. In this contribution, the new TEPX detector - a large forward disk detector - will be presented, with an emphasis on disk characterization in terms of the data transmission quality along with the performance of CROCv2 modules.
The Taishan Antineutrino Observatory (TAO) aims to measure the energy spectrum of reactor antineutrinos, providing a reference spectrum for the JUNO and offering benchmark references for the nuclear databases.
The JUNO-TAO experiment uses 4024 SiPM tiles with 8048 ADC channels to ensure the proposed energy resolution(<1.5% @ 1 MeV), spatial resolution(around 1 cm), and timing performances(around 1 ns).
This paper presents an implementation of timing and synchronization system with the White Rabbit(WR) distributed synchronous timing technology.
The R&D effort carried out to study the timing and synchronization and the other components, supported by laboratory test results, will also be presented.
We developed signal readout electronics for a liquid argon time projection chamber detector, envisioned for use in neutrino oscillation and nucleon decay search experiments. The front-end electronics are based on the ASIC technology, which consists of a 16 channels analog processor, an analog-to-digital converter, and a signal transmitter for digital processing. We demonstrated that the electronics possess a dynamic range for input charge up to 1400 fC and output signal with an appropriate time constant, which meet the requirements of the experiments. We also tested the electronics at cryogenic temperature and confirmed the same performance as at room temperature.
The High-Luminosity LHC will start operations for physics in 2029.
The expansion of the dataset will be achieved by increasing the number of collisions per bunch crossing, leading to higher radiation doses and busier events. To cope with those harsher conditions, the ATLAS Liquid Argon Calorimeter readout will be upgraded to be able to efficiently measure the deposited energies.
A new ATCA-compliant signal processing board has been designed that will receive digitized data from the detector at 40 MHz. In total the 278 boards will have to receive and process 345 Tbps of data via 33000 links at 10 Gbps.
The design and measurement results of a prototype TDC fabricated in CMOS 130nm technology are presented. The TDC architecture with analog interpolators was chosen, which was motivated by previous experience in ADC design. The measured time difference between the event and the trigger signal is converted to the amplitude and then digitised by a 10-bit ADC. The TDC prototype is functional nad achieve good DNL and jitter (below 1LSB), slightly dependent of the selected time precision. The circuit has configurable time resolution from 15ps to 140ps, which gives the total possible time measure range from $\pm$9.5ns to $\pm$70ns.
The ASIC EICROC is designed to read out the AC-LGAD detectors for the future EIC at Brookhaven National Laboratory (BNL). These detectors should combine excellent temporal (20 ps) and spatial (20 um) resolution, enabling a new generation of pixel detectors with precise time measurement. Designing an ASIC to read out the AC-LGAD detector represents a significant technological challenge. EICROC measures and digitizes the charge and the Time-of-Arrival (ToA) (25 ps), transmitting these data to the back-end electronics. The first prototype of EICROC was submitted (in CMOS 130 nm node) in 2022. The ASIC architecture and performances will be presented.
The Embedded Monitoring Processor (EMP) is a state-of-the-art multi-processing System on Chip (MPSoC) based platform, designed for the Detector Control System (DCS) of the ATLAS experiment upgrade. Utilizing the advanced capabilities of the Xilinx Ultrascale+ architecture, the EMP interfaces with the monitoring and control functionalities of its radiation hard front-ends through high-speed optical transceivers. The firmware and software infrastructure comprises the EMP operating system (epos), quasar-based OPC UA servers, a set of firmware IP blocks and associated software libraries that form an integrated ecosystem. This contribution focuses on the current hardware verification and firmware/software developments.
In preparation for the operation at HL-LHC the electronics of the Electromagnetic calorimeter Barrel must be replaced. 12240 new very front end (VFE) cards will amplify and digitize signals of 62100 lead-tungstate crystals instrumented with avalanche photodiodes. 2448 low voltage regulator cards provide power for the VFE and digital interface cards. Reliable operation of these cards with failure rates as low as 0.5% at the end-of-life, after ~20 years, is targeted, requiring environmental stress screening (ESS). We present the implementation of the hardware and software components of the custom developed ESS system, highlighting its modularity, configurability, flexibility, and scalability.
During the upcoming Long Shutdown (LS3) of the LHC, the three innermost layers of the ALICE Inner Tracking System (ITS2) will be replaced by ITS3, a new vertex detector utilizing curved, stitched wafer-scale monolithic silicon sensors, fabricated using 65 nm CMOS technology and thinned to 50 μm. The feasibility of this technology for ITS3 was examined in the initial test production run (MLR1). This contribution will provide a brief overview of the MLR1 submission and discuss the latest sensor characterization results of the Analogue Pixel Test Structure, focusing on the detection efficiency, timing response and radiation hardness.
The STS detector in the CBM experiment delivers data via multiple E-Links connected to GBTX ASICs. In the process of data aggregation, that data must be received, combined into a smaller number of streams, and packed into so-called microslices containing data from specific periods. The aggregation must consider data randomization due to amplitude-dependent processing time in the FEE ASICs and different occupancy of individual E-Links. During the development of the STS readout, the continued progress in the available technology affected the requirements for data aggregation, its architecture, and algorithms. The contribution presents considered solutions and discusses their properties.
The ATLAS Strip Tracker for HL-LHC consists of individual modules of silicon sensors and front-end electronics. The modules are mounted on carbon-fiber substructures with 14 modules per side. An End-of-Substructure (EoS) card connects up to 28 data lines to lpGBT and VL+ ASICs that provide data serialization and 10 GBit/s optical data transmission to off-detector systems, respectively. The EoS is powered by a dedicated DC-DC converters. As the production of ~2000 EoS cards and DC-DC converters is close to completion, we report on production experience including detailed QC statistics. We conclude with a few lessons learned during the project duration.
New-generation physics detectors create a need for high-speed, high-flexibility datalinks in the community. Specific interest lies with commercial standards, compatible with off-the-shelf hardware, therefore replacing custom backends.
We present encouraging first results of an effort evaluating 100Gb/s Ethernet for data readout in the context of typical High-Energy Physics detector requirements. Due to asymmetric data-rate requirements in up- and downlinks, the unidirectional operation of Ethernet is examined. The results are verified with synthetic and realistic traffic, using a series of demonstrators. Additionally, to qualify the radiation hardness of 100Gb/s Ethernet, a statistical analysis is performed based on recent radiation test data.
Next generation particle physics experiments like Electron Ion Collider (EIC) demand high-speed data communication and lower mass designs for its detectors.
This poster presents initial test results for circuits designed to meet the EIC high-speed data requirements. These include a dual-frequency Phase Locked Loop (PLL) that supports two frequency modes of operation, a 5 GHz Pseudo-Random Bit Sequence (PRBS) Generator for system testing, an I2C block and a high speed CML receiver.
Abstract: We present the architectural design, prototype fabrication and first measurements for the second revision of the High Pitch digitizer System-on-Chip (HPSoC) prototype. The HPSoC concept is that of a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip was fabricated in 65nm technology and targets picosecond-level timing resolution via high speed waveform sampling (10 Gsps) and autonomous chip triggering. Details on the front end Transimpedance amplifier design and measurements without and with LGAD sensors will be presented.
ITk strip module is the basic unit in ITk strip upgrade. To do an irradiation test for module with smaller size, the collaboration developed a board called BETSEE. We finish BETSEE test with all latest version of ASICs using proton beam at China Spallation Neutron Source, which is the first time using 10(Mrad/h) level dose rate. From our result, SEE effect is acceptable but TID effect become quite significant, and the system become very unstable during TID peak. The powerboard even get broken with both communication and power supply. Our results could help the collaboration to check all ASICs' reliability.
The ATLAS collaboration will replace its inner detector by an all-silicon tracker for the HL-LHC.
The new pixel detector will cover a sensitive area of 13m2 with about 9000 modules, made of planar and 3D silicon sensors bump bonded to new Front-End ASIC.
The modules are loaded on carbon structures in the form of (half)rings and staves.
Electrically functional prototypes of these local supports based were built and extensive system-level tests were carried out evaluating serial powering, grounding and shielding, monitoring, and the overall performance of the multi-module systems.
In this contribution the results of these system tests are presented.
A new on-detector power distribution scheme for the High Granularity Calorimeter (HGCAL) Phase-2 upgrade of CMS is under development. This scheme is based on a heavy-copper flexible printed circuit board (FPC), allowing for an efficient use of the tight integration space, with minimal insulation overhead, excellent electrical and thermal performance and simplified integration, when compared with a wired solution. This work introduces the technology, how it allows the HGCAL challenges to be overcome, and the characterization studies. Simulations and prototypes testing are presented to validate the concept and quantify the manufacturability, electrical performance, and safety of the proposed solution.
Silicon particle detectors struggle to follow the miniaturisation of available commercial processes, partially due to the relatively large transistors required for the optimal performance of the analogue frontend. Particam instead uses a digital only approach which is focused on digital storage cells switching due to transient radiation. With a pixel being little more than a memory cell it can be designed with close to minimum feature size with very few transistors allowing pixel pitches of a few microns.
Results of initial proof-of-principle MPWs as well as plans for the next steps in the project are presented.
High-precision time measurements are the latest trend for experiments and PET applications.
Compactness, scalability and applicability to thousands of channels is required for the readout electronics.
CAEN A5203 board, part of a synchronizable and distributable Front-End Readout System (FERS), integrates the CERN picoTDC ASIC on a small unit for high-resolution time measurements of ToA and ToT.
This poster presents the performance of the A5203 unit, in terms of time resolution, walk correction, background reduction and signal amplitude reconstruction. The results of its application to the Picotech PET system are also included.
Developing a cost-effective single-die pixel-detector hybridization method using Anisotropic Conductive Films (ACF) or Anisotropic Conductive Paste (ACP) aims to replace fine-pitch bump bonding with conductive micro-particle embedding in adhesive film or paste. This technology enables integration of hybrid or monolithic detectors in modules, replacing wire bonding or solder-bumping. Within the scope of this project, also an Electroless Nickel Immersion Gold (ENIG) plating process has been developed for single-die chips to achieve the required pixel pad topology. This contribution introduces the ENIG, ACF and ACP processes, alongside test results from test structures, functional chips and hybrid pixel assemblies with flip-chip bonding.
NνDEx-100 is the phase I of NνDEx, which is a proposed 0νββ detection experiment based on the high pressure gaseous TPC filled with SeF6. Thousands of sensors will be placed on the readout plane located in one end-cap of the TPC. The sensors collect ions, measure the charge and output analog waveforms with the integrated CSA. The outputs are then digitized, aggregated, and transmitted to the back-end DAQ system. This presentation introduces the prototype design of the 19-sensor front-end module and the integration with DAQ system. The design and integration with Am-241 radiation source in a TPC will be presented.
Next-generation silicon pixel detectors with fine granularity will allow for precise measurements of particle tracks in both space and time. A reduction in the size of pixel data must be applied at the collision rate of 40MHz to fully exploit the pixel detector information of every interaction for physics analysis.
We developed radiation hard readout integrated circuit with on-chip digital artificial intelligence in 28nm CMOS. We will present hardware test results on the first prototype fabrications. Preliminary results indicate that reading out clusters from particles above a modest momentum threshold could enable using pixel information at 40MHz.
Results are presented for reliability tests of the SFP+ transceivers and the readout board of Thin Gap Chambers (TGC) for the ATLAS experiment at HL-LHC. The radiation tolerance was evaluated for the SFP+ transceivers from Broadcom and FS and the TGC frontend board with gamma ray irradiation up to O(100) Gy at the Cobalt-60 facility of Nagoya University. An accelerated aging test was also performed for the SFP+ transceivers with the Kintex-7 evaluation board integrated in the temperature chamber.
The ALICE experiment at the Large Hadron Collider (LHC) has planned an upgrade of the Inner Tracking System, ITS3, which will be installed during the LHC Long Shutdown 3 (LS3, 2026-2028). This presentation will show fresh results about the resolution performance obtained at the end of 2024 with 65 nm CMOS MAPS Analogue Pixel Test Structures during beam tests at CERN SPS. Resolution performance results comparing different sensor configurations (different design, pitch, reverse-bias voltage) and irradiation conditions will be shown and discussed.
To cope with the increase of the LHC instantaneous luminosity, new trigger readout electronics were installed on the ATLAS Liquid Argon Calorimeters.
On the detector, new electronic boards digitise 10 times more signals than the legacy system. Downstream, large FPGAs are processing up to 20 Tbps of data to compute the deposited energies. Moreover, a new control and monitoring infrastructure was developed.
This contribution will present the challenges of the commissioning, the first steps in operation, and the milestones to be completed towards the full operation of the legacy and the new trigger readout for the LHC Run-3.
The Global Trigger will be the final stage of the new Level-1 trigger for Phase-2 operation of CMS. Based on high-precision inputs from the muon-, calorimeter-, track- and particle flow triggers, it will evaluate a menu of O(1000) cut-based and machine-learning-based algorithms in a system of up to thirteen Serenity processing boards equipped with AMD Ultrascale+ FPGAs and interconnected with 25 Gb/s optical links. We report on tests of a firmware prototype, integration tests with the upstream systems and the ongoing integration of a prototype into a slice test connected to the running experiment.
High-voltage CMOS Pixel technology is being considered for future Higgs factory experiments. The ATLASPix3.1 chip, with a pitch of 50μm x 150μm, fabricated using TSI 180nm HV-CMOS technology, is a full reticle-size monolithic HV-CMOS sensor with shunt-low dropout regulators that allow serial powering for multiple sensors. A beam test was conducted at DESY using 3-6 GeV positron beams, with chips operated in triggerless readout mode with zero suppression, demonstrating multi-chip capability. This was further evaluated with hadron beams, both with and without the built-in power regulators. This talk summarises the electrical characterisations and test beam results of ATLASPix3.1 sensors.
The ATLAS experiment is preparing for the High-Luminosity LHC era, by replacing the current innermost detector with an advanced all-silicon tracker (pixels and strips) to withstand radiation damage and increased particle activity. Pixel module quality control spans various production stages which necessitates a robust data acquisition software capable of handling high data rates and MHz calibrations. Yet Another Rapid Readout (YARR) software, adaptable to diverse hardware platforms including ATLAS Phase-2 readout board i.e. FELIX, facilitates these testing scenarios. This contribution highlights YARR's development, key features, and benchmark performance in calibrating multiple pixel modules using the FELIX readout board.
In this talk, we report the R\&D program underway at CCNU to develop a pixel chip for the readout of GEM detectors appropriate for use in the CSR external-target experiment (CEE) at HIRFL for beam monitoring. The chip offers simultaneous time-over-threshold (TOT) and time-of-arrival (TOA) measurements, and a data-driven readout scheme with a rate of 40 MPixels/s. Two generations of the chips were produced, with the second generation offering much-improved performance over the first one. The design and characterization of the chips are presented, including the tests using injected pulses, $\alpha$ particles, laser beams, and heavy-ion beams.
Following the ALICE ITS3 detector development line of wafer-scale monolithic stitched pixel detector prototypes in the TPSCo. 65nm CMOS imaging technology, the MOSAIX chip is the prototype of the final full-size and full-functionality ITS3 sensor.
MOSAIX has a die size of 26.6x1.96 cm2 with >94% of active area. It has 144 sensor tiles which can be powered individually to compensate for manufacturing defects. Each tile has 69.2k pixels with 22.8x20.8µm2 pixel size. This contribution highlights the lessons learnt from the predecessors MOSS and MOST chips, summarizing the architectural decisions of the MOSAIX implementation and focusing on the yield enhancement techniques.
For the LS3 ALICE ITS3 upgrade the detector material budget reduction has been pushed to the limit by proposing a system composed almost exclusively of silicon wafer thinned to 50$\,\mu\mathrm{m}$. This improves performance, but adds complexity to the ASIC design. It requires a wafer-scale module with embedded power delivery network and on-chip data transfer, which were usually done through flexible printed circuit cable.
This contribution covers different aspects of the power delivery network design for a wafer-scale detector. It describes the difficulties, shows possible solutions and presents the power scheme design of the full-size ITS3 sensor prototype MOSAIX.
The Monolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of $26~\textrm{x}~1.4~\textrm{cm}^2$ size with the primary goal of understanding the stitching technique and yield. It is a proof-of-concept chip for the final sensors of the ALICE ITS3 upgrade. Given the large size, high yield is paramount for the ITS3 sensors and an in-depth yield characterization was performed on MOSS sensors. Short circuit failures were observed across 24 wafers with varying frequency. Dedicated test systems and failure analysis methods were developed, and root cause analysis was performed. Methods, results, and potential mitigation techniques will be presented in this contribution.
A family of fully integrated (including all capacitors and inductors) rad-hard DCDC converters has been developed for the first time in the HEP community. This work presents the experimental results of three functional ASICs prototypes designed in a 28nm CMOS technology using 0.9V-rated transistors. All prototypes have been designed to withstand 1Grad. iPOL5V and iPOL2V3 are state-of-the-art resonant DCDC converters, able to regulate respectively from 5V and 2.3V to 0.8-1V. They respectively feature a peak efficiency of 67% and 80%. Furthermore, a linear regulator (linPOL1V2) able to convert 1.2V down to 0.8-1V has been designed and tested.
Efforts aiming at consolidating the powering for the CMS detector have led to the development of a Low Voltage Power Supply (LVPS). The LVPS converts 380 VDC to 12 VDC, suitable for powering the widely used bPOL12V Point-Of-Load DC-DC converter. To limit cables size, the LVPS must be hosted in the CMS experimental cavern, being exposed to ionizing radiation and stray magnetic field of up to 120 mT. The device is made of Commercial Off-The-Shelf (COTS) components, therefore thorough qualifications at various design stages were performed to ensure its reliable operation in the harsh environmental conditions for the HL-LHC era.
DC/DC converters that are tolerant to high magnetic fields and radiation are needed to improve the power distribution scheme of High Energy Physics (HEP) experiments. This paper presents 2 topics: firstly, an optimised rad-hard production-ready module for 48V to 5V-12V conversion (including) a custom PCB air core inductor, and secondly the outcome of a R&D program for developing next generation DC/DC converters. In this context, a framework for analysing, optimizing, and comparing different conversion topologies has been developed. Furthermore, the most promising topologies for input voltages up to 48 V (Buck, 3-Level Buck, and Berkeley Series Capacitor) are experimentally validated.
Abstract
Since CERN was founded, there have been significant changes in detector technologies which in turn have necessitated big changes in the readout and data acquisition electronics. Many of them have taken place since about 1990 during the preparations for LHC, profiting especially from the commercial impetus driving the rapid growth of consumer electronics. As a non-historian, and not even a qualified electronic engineer, I will attempt to trace how some of these technologies have evolved, citing examples with which I am most familiar, and make some comments about the challenges and risks for the future.
Biography
Geoff Hall is a Professor of Physics at Imperial College London, now semi-retired. He became involved with silicon detectors in the mid-1980s, originally motivated by a SLAC charm photoproduction experiment using a rapid-cycling bubble chamber, and contributed to the first UK experimental developments of silicon microstrips. This led into several other silicon sensor development projects, and then in the 1990s to silicon radiation damage studies and ASIC developments for the LHC, eventually culminating in the APV25 ASIC used by CMS and many other projects. With many students and colleagues he contributed to several electronic readout systems for the CMS experiment, which has more recently included ASIC and novel module developments for the CMS tracker HL-LHC upgrade.
The MOSS wafer-scale monolithic sensor, designed for the vertex detector (ITS3) of the ALICE experiment, features a pixel input capacitance of ~5fF. Such a small input capacitance is needed to reach a satisfactory SNR with a low-power analog front-end (30nW/pixel). This makes the design of the pulsing circuitry needed to characterize the front-end performance particularly challenging. As an example, measurements of the front-end of MOSS are presented, showing that even a parasitic capacitance < 5aF can significantly alter the charge injection from the pulsing circuit. In this contribution, design methods and solutions to address these challenges are detailed.
The ASIC for the high-granularity pre-shower detector of the FASER experiment at CERN is a full-reticle imaging chip (1.5x2.2 cm^2) for TeV-scale electromagnetic showers at the LHC. It features a monolithic pixel sensor with 65 µm side hexagonal pixels in IHP 130nm SiGe BiCMOS. The pixels integrate analog memories for charge measurement (0.5 fC÷64 fC) and the frontend with 100-ps-level jitter and ENC < 200 electrons. The chip features 100 ps time binning, a frame-based 200 MHz readout, and has a power consumption below 150 mW/cm^2.
This work presents the design, the corresponding challenges and the first silicon validation results.
The RD50-MPW prototypes are High Voltage CMOS pixel chips in the 150 nm technology from LFoundry S.r.l. aimed at developing monolithic silicon sensors with excellent radiation tolerance, fast timing resolution and high granularity for tracking applications in future challenging experiments in physics. RD50-MPW4, the latest prototype within this programme, implements significant improvements for a high breakdown voltage (> 400 V), and therefore an excellent radiation tolerance, through a multiple ring structure around the chip edge and substrate backside-biasing to high voltage. This contribution will present the laboratory evaluation of RD50-MPW4 samples irradiated with neutrons to $10^{16}$ ${\rm n_{eq}/cm^2}$ high fluence.
In preparation of the operation of the CMS electromagnetic calorimeter (ECAL) barrel at the High Luminosity Large Hadron Collider (HL-LHC) the entire on-detector electronics will be replaced. The new readout electronic comprises 12240 very front end (VFE), 2448 front end (FE) and low voltage regulator (LVR) cards arranged into readout towers (RTs) of five VFE, one FE and one LVR cards. The results of testing one RT of final prototype cards at CERN’s CHARM mixed field facility and PSI’s proton irradiation facilities are presented. They demonstrate the proper functioning of the new electronics in the expected radiation conditions.
The Beam Gas Ionization (BGI) profile monitor, situated within the PS and SPS accelerators, requires a radiation-tolerant readout system to transfer data from the challenging accelerator surroundings to the back-end for processing. Operating 1m below the beam pipe, the front-end must ensure reliability, given limited hardware access, and preserve signal integrity for the high-speed Timepix3 data (32 channels at 320 MHz). The outcome is the Beam Instrumentation PiXeL (BIPXL) readout system, employing radiation-hardened components like the GBTx and the FEASTMP, both developed at CERN. This system will be compatible with forthcoming hybrid pixel detector initiatives in similarly harsh radiation conditions.
The Radiation Monitoring System (RadMon) for CERN accelerator complex measures radiation levels in the accelerator tunnels, adjacent shielded galleries and experimental areas. This allows the correlation of observed radiation-induced equipment failures with the respective accumulated radiation levels. The main component of the system is the RadMon device, a compact detection and communication system capable of measuring Total Ionizing Dose (TID), Displacement Damage (DD) in Silicon, High Energy Hadrons (HEH) and thermal neutrons fluence. A separate, smaller sensor module, connected to the main RadMon device, allows measurements in less accessible locations, as large experiment caverns and inner detectors.
The APOLLO ATCA platform is an open-source design that separates into a generic "Service Module" (SM) and customizable "Command Module" (CM), allowing cost-effective use in applications such as readout of the inner tracker and Level-1 track trigger for the CMS Phase-II upgrade at the HL-LHC. The SM incorporates an intelligent IPMC, robust power entry and conditioning systems, a powerful system-on-module computer, and flexible clock and communications infrastructure. The CM is designed around 2 Xilinx Ultrascale+ FPGAs and high-density, high-bandwidth optical transceivers capable of 25 Gb/s. Crates of APOLLO blades are being tested at Boston University, Cornell University, and CERN.
The LHC-synchronous part of the Phase-2 CMS DAQ and timing systems
will be built around two custom ATCA boards, interfacing the
subdetector back-ends to the central trigger-DAQ systems. The DAQ and
Timing Hub provides a 10 Gb/s connection to the central timing system,
and up to 400 Gb/s of DAQ bandwidth. This board can be combined with
one/multiple DAQ800 boards to increase the data bandwidth.
With the prototyping phase completed, we now present our first
experience with partial- and full-chain systems, demonstrating the
core of the Phase-2 CMS DAQ, timing, and trigger control systems.
The data acquisition system of LHCb Upgrade I is a single stage readout followed by event building, real time reconstruction and selection. The current system already has to process 32 Tbps of data, and this will rise to above 200 Tbps with Upgrade II. The new PCIe Gen 5 readout board called PCIe400 embedding the most powerful altera’s Agilex M-series FPGA and 112 Gbps serial links is the baseline readout board for LHCb future upgrades. Presented here is the technical challenges encountered during the hardware design process with a focus on simulation performed.
Firmware testing on actual hardware is an optimal way to validate large-scale FPGA-based trigger/DAQ systems. For the ATLAS Phase-II level-0 muon trigger system's Sector Logic (SL) firmware, a methodology using prototype ATCA-based SL boards was developed, featuring self-complete DAQ, high-statistics test patterns, and various nature of input test data. The design exploits Zynq SoC on the board for control, injection of BRAM-based test patterns data and flexible DAQ to probe the process. The success is owing to the flexibility of the SL board design around the SoC device. This methodology facilitates precise firmware validation and systematic debugging.
HEP data acquisition systems are often built from high-end FPGAs. As such systems scale in the HL-LHC era, severe underutilization of FPGA transceivers can occur because frontend links prioritize radiation hardness and power consumption over raw data bandwidth. This work evaluates recently introduced low-power, low-cost FPGA devices as an alternative building block for future readout architectures. We implement a readout backend on FPGA where the frontend protocol is based on the Low-Power GigaBit Transceiver (lpGBT) and the readout protocol is based on 10 Gigabit Ethernet, using the LHCb Run 4 RICH detector as a practical case study.
Deep Neural Networks are increasingly deployed at safety-critical operations. In order to enable this technology for harsh environments that contain high levels of radiation, fault analysis and mitigation is required. In this study, we present a model-based fault injection campaign to analyze the impact of multiple Single-Event Upsets (SEUs) in Deep Neural Networks (DNNs). Furthermore, we propose a Fault-aware Training (FAT) methodology to increase the reliability of DNNs without any modification to the hardware. Experimental results show that the FAT methodology improves the fault tolerance up to a factor of 20.
A high-performance event-driven readout electronics system based on Timepix4 has been developed for energy-resolved neutron imaging detectors at China Spallation Neutron Source (CSNS). The system achieves a position resolution better than 55 µm and a timing resolution better than 1 µs. The readout electronics feature a large-capacity cache, high readout bandwidth, and FPGA-based hardware acceleration algorithms for real-time data analysis. The system supports a sensitive area of 6.94 cm², counting rates up to 40 Mhits/cm²/s, and a maximum readout bandwidth of 40Gbps. Neutron imaging test experiments have demonstrated the good performance of the readout electronics system.
This work describes a custom electronics board (“PicoTDC board”) developed at INFN Bologna, whose goal is to provide fast timing measurements to generic detectors able to test different front-end electronics using a common FMC interface. The fast timing measurements are achieved using 2 PicoTDC ASICs from CERN, providing 128 channels with 3.05 ps LSB. Design choices and performance of the card are discussed. The results obtained using the PicoTDC board with a FMC card hosting the LIROC chip for the readout of SiPMs and LGADs at a test-beam at the Proton Synchrotron facility at CERN will also be presented.
PixESL is a virtual prototyping framework tailored for forthcoming particle detectors. It aims to enable high-level abstraction for describing detectors developed in High Energy Physics experiments, simulating the entire chain from particle interaction to data packet readout. This contribution describes three different models developed in the PixESL framework for pixel detector applications: a timing-oriented pixel design including an analog front-end and in-pixel clustering, a data-driven pixel array readout architecture, and a triggered pixel array readout architecture. The first two models are inspired by the LHCb VeLo upgrade II, while the third one by the CMS ITk Phase-II upgrade design (RD53c).
RDMA communication can be a good solution for many communication use cases, such as in data acquisition systems and any other system requiring high bandwidth and low latency. Multiple options for an RDMA-based communication system have already been tested, such as profiling based on message size and message count, using multiple simultaneous clients for FPGA-based RDMA senders, or streaming data over RDMA links for software senders. Now, all of these are being put together in a system supporting streaming of data from a FPGA-based system over an RDMA link to one or more clients and new features are being added.
Abstract
In this presentation, we will explore the critical role of on-chip ESD protection in advanced semiconductor processes. Starting with an introduction to ESD events and their potential to catastrophically damage semiconductor circuits, we will delve into the strategies employed to mitigate these risks. Traditional ESD protection methods, while sometimes effective, often introduce challenges such as excessive capacitance, large area consumption for power clamps, and inflexible design constraints.
We will then shift focus to a local clamp approach, which utilizes ESD clamps inside the I/Os to offer greater design flexibility, significant overall area savings, reduced leakage, and minimized parasitic capacitance, all while ensuring robust protection for thin oxide transistors. This approach's effectiveness will be demonstrated through examples in advanced semiconductor processes, including 28nm and 22nm CMOS, as well as 16nm to 3nm FinFET technologies.
For the particle physics research at CERN, electronics must be designed with greater radiation tolerance. Traditional ESD clamps frequently rely on thick oxide transistors which cause excessive leakage after radiation. Over the past few years, Sofics has successfully delivered ESD clamps and I/O circuits across several process nodes to CERN, contributing to the design of radiation-hardened electronics and sensors.
Join us to gain insights into the latest advancements in ESD protection and learn how Sofics is pushing the boundaries of semiconductor reliability and performance.
The HKROC is designed to read out the Photo Multiplier Tubes (PMTs) for next-generation neutrino experiments, which involve multi-ton detector with thousands of PMTs. It measures and digitizes the charge (up to 2500 pC) and Time-of-Arrival (ToA) (25 ps), transmitting this data to the back-end electronics. A second prototype of the HKROC, submitted in CMOS 130 nm node by summer 2022, aimed to improve performance in both noise and cross-talk, has undergone our complete testing procedure. In this presentation, we will show the results and performance of this improved ASIC
ALTIROC3 is a 2x2 cm² CMOS 130nm ASIC with 225 channels to read-out the new ATLAS HGTD detector for the High Luminosity-LHC upgrade. It was designed using “Digital-On-Top” flow and triplicated for radiation hardness. Chip level IR-Drop analyses were performed to evaluate accurately the power distribution impact, especially for the Time- to- Digital- Converters implemented in each pixel. These studies that drove implementation choices will be presented as well as the challenging performance obtained at system level with a jitter of 25 ps for input charges of 10 fC and under irradiation (SEE and TID).
The Cleopatra ASIC is a 12-channel prototype ASIC for the readout of hydrogenated amorphous silicon sensors used for real-time dosimetry in radiation diagnostic and radiation therapy.
The architecture is based on a current to frequency conversion based on the recycling integrator principle in order to cover a dynamic range of four orders of magnitude with high linearity.
Three different input amplifier configurations have been implemented in order to check the trade-off between detector capacitance and maximum output frequency.
Cleopatra has been designed in CMOS 28 nm technology and successfully tested in laboratory.
For the upcoming high-luminosity LHC, the endcap calorimeters of the CMS experiment will be replaced by the high-granularity calorimeter (HGCAL), a sampling calorimeter using both silicon and scintillator as active materials in different regions depending on the radiation dose. This contribution describes the integration details of the scintillator-based front-end into the DAQ readout chain of HGCAL. For the first time, both sensor technologies are integrated into a single system utilizing the Serenity-S FPGA cards. Initial results from a beam test at CERN showcase both detector technologies of HGCAL, validating the vertical integration stack of the latest available front-end prototype hardware.
The contribution will concern the analysis of data provided by Gas Electron Multiplier (GEM) detectors already installed in the Compact Muon Solenoid (CMS) experiment. We will focus on the correlations among the baseline current observed in the High Voltage (HV) system, the background radiation, and the Large Hadron Collider (LHC) beam luminosity. Additionally, an update on the discharge rates observed during this year’s operations will be provided.
We present the running experience of GE1/1, a new muon tracking and triggering station made of Triple-GEM detectors installed in the most forward region of the CMS muon spectrometer. GE1/1 records data since 2022. Each of the 144 detectors has 24 VFAT3, 3 GBTx, 3 VTRx, 2 VTTx and a Virtex-6 FPGA. All powered by 10 FEAST DCDC converters. We will present the GE1/1 electronics performance over the first 2 years of running at LHC. We will also present the lessons learned and the improvements expected for the next 2 stations to be built, GE2/1 and ME0.
Driven by advancements in manufacturing technologies, microelectronics has evolved significantly beyond Moore's Law, now embracing "More than Moore".
This shift emphasizes heterogeneous integration and innovative packaging schemes to overcome challenges like interconnect bottlenecks.
3D integration has emerged as a crucial approach, combining miniaturization benefits with new flexibility in circuit design, particularly in fields such as image sensors, high-performance computing, and artificial intelligence.
These innovations are driving forward more efficient systems with unprecedented functionalities, supported by ongoing R&D efforts.
Perceval Coudrain received a PhD degree from Institut Supérieur de l’Aéronautique et de l’Espace in Toulouse (France) in 2009. He joined STMicroelectronics in 2002 and entered the advanced R&D group in 2005 where he was involved in the early development of backside illumination and monolithic 3D integration for CMOS image sensors. For fifteen years he has been focusing on 3D integration technologies including TSV and Cu-Cu hybrid bonding development. He moved to CEA-Leti in 2020 where his research focuses on 3D integration, wafer level packaging and embedded thermal dissipation solutions.
A High-Voltage CMOS (HV-CMOS) pixel sensor for particle detection in high energy physics experiments, named UKRI-MPW1, has been developed. It has a high breakdown voltage of ~700 V, while keeping the leakage current below 100 $\mathrm{nA/cm^2}$. This is achieved by improving the sensor cross-section with a customised P-Shield layer and using an advanced chip guard ring scheme. With high biasing voltages, the sensor of UKRI-MPW1 is expected to have high radiation tolerance. The design and measurements of UKRI-MPW1 after irradiation are presented in this contribution.
This work presents the design of a 4-channel ASIC developed in a 65 nm CMOS technology specifically designed to measure the energy captured by the PMTs in the LHCb Upgrade II Calorimeter. The processing chain stands on rail-to-rail fully differential blocks that improve the common noise rejection and maximize the voltage range. A dual gain structure is adopted to extend the dynamic range up to 12 bits. Each gain path is based on two time-interleaved subchannels that remove the dead time of the switched integrators. A dedicated phase-lock loop (PLL) generates the necessary clock signals to synchronize each channel independently.
Multi-channel analog-to-digital converters (ADCs) operating over a wide temperature range are required for data acquisition in high-energy physics experiments, space missions, medical imaging, astronomy, and quantum computing. For example, charge readout of the liquid argon (LAr) time projection chambers (TPCs) used by the DUNE far detectors relies on cooled ADCs operating at 89K. Successive approximation register (SAR) ADCs are suitable for such applications due to their highly-digital nature, low analog complexity, and power efficiency. Here we describe an 8-bit SAR ADC in open-source 130 nm CMOS technology designed to operate reliably from 4K-400K at sampling rates up to 10 MS/s.
DAMIC-M is an experiment that searches for low-mass dark matter particles through their interactions with silicon nuclei or electrons in the bulk of charge-coupled devices (CCDs).
The experiment has developed a new electronics which allows it to read skipper CCDs with a single-ionization charge resolution. An Acquisition and Control Module board (ACM) drives the multiple non-destructive measurements of the pixel charge, the signal digitization and FPGA-based signal processing. This talk will summarize the status of the experiment, and the electronic chain performances from prototype detectors installed at the Modane Underground Laboratory.
The harsh environment of the High-Luminosity Phase of LHC will force the CMS experiment to replace the present pixel detector with a new Inner Tracker implementing 65 nm CMOS read-out chips (CROC). The modules, i.e. the Inner Tracker subunits, are powered in series and read-out through a sophisticated opto-electrical chain. Full-scale systems are realized and tested for validation and performance assessment. The latest results obtained with a serial chain of the final prototypes CROC modules for the TBPX sub-detector will be presented. This system test also implements prototype mechanics and the final electrical opto-conversion stage.
For the high-luminosity upgrade of the ATLAS Inner Tracking detector, a new pixel detector will be installed to increase bandwidth and to cope with higher radiation, among other challenges. In this contribution, the design aspects and qualification of the data transmission from pixel modules to optical readout are presented. A focus is put on the data cable bundles and their performance for one of the Pixel sub-systems, the Outer Barrel. The development of a custom system for production testing of the bundles is discussed. Finally, in preparation of the detector integration, developments regarding functionality and connectivity testing are analyzed.
We report characterization results for our new silicon photonic chip for high-speed data transmission, called COTTONTAIL (Chip for detector instrumentation with wavelength division multiplex). Modulation bandwidths of different conventional and radiation-hardened travelling-wave Mach-Zehnder modulators are sufficient for very high data transmission rates. Wavelength filters for wavelength division multiplexing show a very low transmission loss of less than 2 dB with a slight wavelength shift of the filtering characteristics. Also included photodiodes are well suited for high speed downlinks in excess of 40 Gbps or on-chip modulator monitoring.
The increasing luminosity in CERN experiments enabled by future upgrades demands optical links with enhanced bandwidth and radiation tolerance. Silicon Photonics (SiPh) emerges as the optoelectronic technology meeting these requirements and is being considered for the next generation of optical readout systems of CERN detectors. We present the progress on Silicon Photonics for High Energy Physics (HEP) made in the CERN EP R&D WP6 project. We show the measurement results of the photonics circuits integrated into two test chips designed at CERN, along with the progress on the system aspects of the SiPh radiation-tolerant optical links.
This study details the experimental characterization of silicon photonic ring modulators (RMs) and silicon-germanium (SiGe) electro-absorption modulators (EAMs) exposed to 12 MGy(SiO2) total ionizing dose (TID) within INFN’s project FALAPHEL. We extensively report on the evolution of their key performance metrics as a function of TID. These trends are analyzed in relation to the underlying physical mechanisms responsible for TID-induced degradation. We demonstrate the TID tolerance of SiGe EAMs and the effectiveness of room-temperature forward-bias annealing as a technique for recovering RMs from TID damage, along with its potential as damage compensation if applied periodically during irradiation.
The China Spallation Neutron Source (CSNS) is undergoing an upgrade to CSNS-II, increasing its power to 500 kW. This talk summarizes the readout electronics for the 10 neutron instruments currently in operation or commissioning at CSNS, discussing challenges, solutions, and glitches encountered. We also present the development and testing of low-power readout electronics for 3He PSD arrays and high-density neutron scintillators, which are the main detector types for CSNS-II. The progress on prototypes, including ASIC-based preamplifiers, ultra-low power FPGA-based channel reduction circuitry, and low-power FPGA-based processing modules, will be discussed.
The SiSMUV project aims to develop a compact modular UV detector based on SiPMs for use in space telescopes, targeting the study of fluorescence and Cherenkov signals produced by Ultra-High Energy Cosmic Rays (UHECRs). SiSMUV has the objective of incorporating into a monolithic block, state-of-the-art sensors and low-power read-out electronics, creating a complete end-to-end system, which can be easily interfaced with a PC for standalone operation or back-end electronics in the case of a more complex system. The Monolithic Photo-detection Block is defined as the combination of a matrix of SiPM, signal-processing front-end electronics, and a local intelligence.
The Circular Electron Positron Collider (CEPC) drift chamber requires high-performance readout electronics for accurate dN/dx measurement and particle identification (PID) using cluster counting techniques. The prototype readout electronics consists of high-speed op-amp based fast current amplifiers, 1.3 Gsps ADCs, and FPGAs for data acquisition and buffering. The system aims to acquire accurate current signals and send them for machine learning-based cluster counting algorithms. Systematic simulations, tests of high-bandwidth pre-amplifiers, and the development of multi-channel high-speed sampling electronics will be presented. The prototype, with more than 10 channels, will be evaluated in testbeam experiments to assess PID capability.
The growing interest on the use of CMOS circuitry for quantum computing and sensing is increasing the momentum of the R&D on cryogenic CMOS, unmistakably demonstrated by an almost tenfold increase on the number of related yearly publications since 2017, and creating new collaborative efforts between academia and industry partners on the optimisation of semiconductor technology and CMOS processes and modelling for operation at cryogenic temperatures.
On the one hand, the availability of enabling infrastructures and key capabilities for the development of cryogenic mixed-signal integrated electronics operating below 4K and down to the mK will finally solve the long standing wiring bottleneck of the quantum computers, paving the way for scalability into the million qubit realm.
On the other hand, the excellent performance of CMOS at the mild cryogenic temperature range opens interesting opportunities on the development of innovative readout concepts for rare-event searches on neutrino physics and direct dark matter detection using noble liquid targets. Single and dual-phase detectors employing (solid-state) photon sensors require front-end readout electronics operating at 165K (LXe) or 88K (LAr), as future large-scale experiments will call for innovative cold integrated readout electronics implementing digital signal processing embedded in the photodetection module.
In both cases, reliable cold CMOS Process Design Kits are fundamental for the development of complex mixed-signal ASICs allowing for innovative detector architectures and concepts, data transfer, readout and control. While MOSFET device models on both VDSM bulk and FD-SOI technologies seem to scale relatively well down to 77K, CMOS PDKs are typically qualified down to 233K. Silicon foundries, CAD software houses and fabless IP providers are now ramping up the development of CMOS processes, cold IPs and PDKs qualified for very low temperatures.
We will discuss the outlook for the design of system-capable “cold” ASICs in astroparticle and high-energy physics, discussing ongoing efforts and options in academia and industry for the creation of infrastructures for the development of CMOS electronics for cryogenic environments.
BIOGRAPHY:
Manuel Rolo received his Electronics Engineering degree from University of Aveiro and holds a PhD in Physics from the University of Turin. His previous experience in the semiconductor manufacturing industry (Qimonda AG), with European microelectronics service providers (CMP, Grenoble) and as a Senior Manager for Microelectronics at PETsys Electronics is now complemented with over 10 years at INFN developing and coordinating R&D on ASIC design for particle, astroparticle, nuclear physics and industrial applications. He is author or co-author in over 400 journal papers and several international patents in the field of radiation sensors and integrated electronics.
The consolidation of the Large Hadron Collider (LHC) Beam Instrumentation requires the digitisation of the analogue signals from the detectors within the radiation areas. Subsequently, the digital data are transmitted via the existing fibre plant to the back-end area for processing. In order to manage the increased volume of data with the existing infrastructure, the proposed Coarse Wavelength Division Multiplexing (CWDM) link project merges four optical carrier signals of different wavelengths into a single optical fibre through two high-speed radiation-tolerant optical twin transmitters. This paper outlines the project’s current status and radiation tolerance of the constituent components.
We developed a prototype of muon beam monitor for the COMET experiment. The detector consists of SiC PN-diodes and dedicated readout electronics. By tailing the 256 sensors in a matrix, the beam parameters extracted from this monitor are utilized for the essential background estimation. The electronics is designed in 65 nm CMOS, including 16 channels analog processor, ADC, PLL, and CML drivers. We demonstrated the functionality of the ASIC with a designed peaking time and voltage gain. We also tested the electronics at cryogenic temperature and confirmed stable behaviors down to -100 degree Celsius.
The COLUTA ASIC is an 8-channel, 15-bit, 40 MSPS, analog-to-digital (ADC) converter designed for the high-luminosity LHC (HL-LHC) upgrade of the Liquid Argon calorimeter readout electronics. The production version of the ADC meets and exceeds the specifications for the analog performance and the HL-LHC radiation tolerance. The production testing will be performed by a custom-designed robotic test setup which will test 80,000 chips required for the upgrade. The chip performance results, and the chip quality information are stored in a local and centralized database. The robotic setup, chip-quality tests, data archival infrastructure, and the production yields will be presented.
The CoRDIA X-ray detector is a development targeting experiments at modern diffraction-limited synchrotron rings and free-electron lasers operating either in continuous wave or quasi-continuous long burst modes with photon bunch frequencies up to a few 100kHz. It’s a hybrid detector with sensitive tiles formed by a read-out ASIC bump bonded to a sensor. Since 2020 4 prototype ASICs were manufactured on order to validate and characterize the single circuit building blocks as well as to prove the concept of the complete detector. Test results, ASIC design details and plans will be presented.
This contribution presents the methodology and verification strategy for OBELIX, the monolithic active pixel CMOS sensor designed for the proposed upgrade of the Belle II vertex detector. Leveraging a dual verification approach with cocotb and UVM, we ensure the integrity of OBELIX's digital logic. This methodology addresses the complexities of ASIC design, which includes an 896x464 pixel matrix with 7 bits Time-over-Threshold (ToT) resolution per pixel and implements a trigger logic with two stages of memory. Through comparative analysis, we enhance error detection during the design phase, thereby bolstering confidence in OBELIX's functionality.
Since full waveform sampling can provide more accurate signal information which is important for particle detectors. So high-speed, high precision and low power consumption Analog to Digital Converter is needed. A two-step sub-SAR ADC is used to achieve low power consumption and using pipeline principle to improve the speed. In-stage and between-stage redundancy technologies are used to improve the SNDR. A three stages amplifier without any internal phase compensation are used as the residue amplifier to decrease the power consumption. The simulation results show that the SNDR can be up to 84.2dB, and the power consumption is less than 25mW.
Ever more precise time information is required to separate independent events at planned and proposed particle physics experiments. Typically, a combination of internal gain, very fast amplifiers and complex sampling circuitry are used to achieve this high time resolution. In this contribution a novel circuit to improve the time resolution of a depleted monolithic active pixel sensor (DMAPS) is presented. Its amplifier feedback is designed such that within its dynamic range the time walk of the trailing edge of the amplifier is compensated, making it the better estimate of the time of arrival (ToA).
We present the R&D of FPMROC, an ASIC for ToF-PET with a fast MCP-PMT (FPMT). The design architecture includes a preamplifier, a discriminator with programmable threshold, a time- to-digital converter, an event builder with a serializer, a clock unit, and a SPI. We aim for a time resolution below 10 ps, matching the targeted FPMT parameters. We are designing the first prototype using a 55 nm CMOS technology. Although the development is for a ToF-PET, the design may find applications in time measurements in future physics experiments. The prototype submission is in July.
The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an on-detector ASIC, Monitoring Of Pixel System (MOPS), and channeled to the Detector Control System (DCS) via a newly developed FPGA-based interface known as MOPS-Hub.
The implementation details and experimental outcomes of the MOPS-Hub will be presented. Additionally, mitigation strategies for addressing potential Single-Event Upset (SEU) issues in the new system along with the irradiation results is presented.
We present the design and preliminary test results of a MAPS sensor, MIC6_Explorer0, based on a 55nm Quad-well CMOS Image Sensor process for high-energy physics experiment vertex detector applications. MIC6_Explorer0 comprises 3 large matrices and is intended to investigate the charge collection properties of the 55nm process with various MAPS design parameters, including pixel pitch, diode geometry, reset method, and readout circuit structure. Preliminary test results demonstrate that the pixel array with a 24μm x 24μm pixel pitch achieved a 95% charge collection efficiency when exposed to a 55Fe source.
In High Energy Physics, ASICs are becoming more and more complex with the integration of many digital processing and monitoring structures. The next generation of System-On-Chips will require reprogrammable logic to let the user change the ASIC behavior after its fabrication. CPROC (Central Processing ReadOut Chip) is a processor demonstrator based on the RISC-V Instruction Set Architecture. It will open the era of FPGASIC with a user-defined program executed by the embedded processor. The CPROC chip was received in May 2024: an introduction to RISC-V, architectural choice and capabilities will be presented.
JUNGFRAU is a state-of-the-art charge-integrating detector for imaging experiments at synchrotrons and free-electron lasers. It is currently limited to a frame rate of 2.2 kHz. With the goal to increase the frame rate of the detector to > 10 kHz, we have designed a 3.125 Gbps high-speed serial readout recently. Thus, the development of a fast Analog-To-Digital Converter ADC has become our main objective. This poster focuses on design features of the new ADC prototype along simulations and measurements of the GOTTHARD-II ASIC’s ADC taken as reference for our new development.
The CMS Electromagnetic Calorimeter (ECAL) uses lead tungstate scintillating crystals to measure the energy of electrons and photons produced at the Large Hadron Collider (LHC). The High Luminosity upgrade of the LHC (HL-LHC) at CERN during the LHC Long Shutdown 3 imposes significant challenges for its experiments. The higher luminosity changes the environmental conditions in which the ECAL detector will operate. In this contribution the upgrade plans and preliminary designs to accommodate the new operational requirements of the CMS ECAL Barrel Safety System are summarized, including the design and development of hardware components for RTD interfacing and the interlock control.
A monolithic CMOS pixel sensor named OBELIX is beeing designed to equip new detection layers proposed as an upgrade of the current vertex detector of the Belle II detector. Based on the TJ-Monopix2 sensor, OBELIX integrates an extended matrix with 33 micrometers pixel pitch. The chip includes a unique combination of features for this granularity: low-dropout regulators, hit logic to match the Belle II trigger at 120 MHz/cm2 hit rates and a fast hitOR signal used to both time-stamp hits with a few ns precision and to provide fast information for track triggering.
The design and simulation results of an ultra-low power fast 10-bit SAR ADC in CMOS 130~nm technology, are presented. This ADC is an extension of experimentally verified (INL,DNL $<$ 0.5~LSB, ENOB$>$9.5) 10-bit SAR ADC working up to 50~MSps and consuming 680~uW@40~MSps. The goal of the new design was to add an internal threshold for the processed input signal, so as to stop the conversion and thus greatly reduce power consumption in case the signal is below the threshold. The designed ADC will soon be submitted for fabrication.
This contribution introduces a novel test system developed to evaluate the signal transmission quality in high-speed data links for the 2026 Inner Tracker upgrade of the ATLAS experiment. Using an FPGA-based data acquisition framework, the setup can run simultaneous Bit Error Rate (BER) tests for many channels and generate virtual eye diagrams, for qualifying the ~26K electrical links of ATLAS ITk, data rate of 1.28Gbps. The presentation will include results from system calibration yielding its contribution to the measured losses, and preliminary results from tests of prototype and pre-production assemblies of on-detector links of the three ATLAS ITk Pixel subsystems.
he TaichuPix chip, a dedicated monolithic pixel sensor for the CEPC vertex detector R&D, demands a raw data rate up to 3.84Gbps and power consumption of less than 25mA/Gbps for the serializer circuit. The TaichuPix1 achieved a maximum data rate of 3.36Gbps with large jitter and current. Subsequently, two 4Gbps serializers were developed and optimized to meet the requirements. Despite encountering a biasing issue, test results indicate that the RMS jitter of both PLL clocks is less than 1.2ps. A revision has been implemented to address the biasing issue and is ready for testing. Updated test results will be presented.
The High-Luminosity LHC will start operations for physics in 2029.
This expansion of the dataset will be achieved by increasing the number of collisions per bunch crossing, leading to higher radiation doses and busier events. To cope with those harsher conditions and to be compatible with the new ATLAS data acquisition paradigm, the ATLAS Liquid Argon Calorimeter on-detector electronics will have to be replaced.
The presentation will cover the validation of the performance of the new boards boards, a critical step before launching the full production of about 1500 boards and their installation which is planned to start in 2027.
Validation of the recent FPGA firmware logic used in particle physics is being hard, since the implemented logic becomes larger and more complex with increasing FPGA resources. In order to address efficiently, we have developed a firmware validation system using the FPGA accelerator produced by FPGA vendors. We have established a system by developing the interface with CPU of host computer, which receives and sends various size of input/output data. The concept and details of implementation of the developed system will be presented.
At LHC phase 2, the CMS detector electronics need a precise clock to discriminate piled-up events. The backend electronics of the barrel electromagnetic calorimeter (ECAL) supplies the high-precision clock to the frontend. However, after a reset in the deserializer, the resulting phase of the recovered clock is not accurately repetitive. Therefore we have studied a case where the system seamlessly switches on-the-fly to a local clock so it keeps running when the link that delivers the clock to the backend, unlocks. This approach prevents the loss of the backend links towards the on-detector electronics ensuring clock phase repeatability.
For nearly 20 years, the Power Supply and Crate Service at CERN has been responsible for the maintenance tracking of power supplies and crates used by the CERN experiments. With this experience, and with the imminent introduction of a new generation of power supplies for the HL-LHC, the timing is opportune to conduct a statistical analysis to draw lessons from the past and make recommendations for the future. This study aims to analyze failures, identify the most vulnerable components, expose the improvement solutions, and highlight the benefits of preventive maintenance campaigns to ensure reliable long-term operation.
The CBM experiment uses a free streaming DAQ with interaction rates up to 10MHz resulting in data rates, which exceed storage capabilities, necessitating online processing. The SPADIC ASIC of the CBM-TRD provides hit messages with oscilloscope-like sampling of the detector data, encoding valuable information. To speed up data unpacking and free up computing time, feature extraction is moved to the readout FPGA. In the mCBM experiment, this approach is tested, demonstrating the benefits of HLS and C++ template programming for algorithm development. Results show resolution improvements and significant reductions in data volume and unpacking speed at the computing cluster.
The FELIX system, initially deployed for ATLAS in LHC Run 3, will evolve for Run 4, serving all subdetectors. The system will consist of 350 servers with new custom PCIe FELIX cards and 200 GbE interfaces, handling data at 1 MHz readout rate for a 4.6 TB/s throughput. The new PCIe cards, featuring an AMD Versal Premium FPGA/SoC and advanced connectivity, run upgraded firmware to decode data and manage timing and control information. Preliminary reviews in 2022 and 2024 confirmed the validity of the firmware and card design. Server and software upgrades will also facilitate increased data and trigger rates.
The design and measurement results of a SoC readout ASIC, called FLAXE, developed for the ECAL-p, the electromagnetic calorimeter at the LUXE experiment are presented. The FLAXE consists of 32 channels with programmable gain front-end, fully differential shaper, and a 10-bit SAR ADC in each channel, working nominally at 20 MSps. Due to a very low bunch crossing rate of 10Hz foreseen for the LUXE experiment, the ASIC is equipped with an internal DAQ memory, read via the SPI bus. The detailed characterization of the FLAXE, performed with a dedicated test setup is presented and discussed.
The use of ultra-lightweight flexible Printed Circuit Boards (PCBs) in silicon-based particle detectors was pioneered for the ALICE Inner Tracking System 1 (ITS1) and the STAR tracker in the early 2000s. These PCBs feature thin, flexible interconnections made of µm-scale polyimide (e.g. kapton) and metal (e.g. copper or aluminum), offering low-mass yet with stability of mechanical and electrical properties. However, decreasing feature sizes by keeping a low percentage of defects and dimensions close to nominal values requires high process control and sustained quality control efforts. This study introduces innovative microfabrication approaches and systematically characterizes thin flexible PCBs mechanically and electrically.
The Monolithic Active Pixel Sensor (MAPS) implemented in high-voltage CMOS (HVCMOS) technology is one of the most sophisticated detectors for detecting high-energy particles. Over the past decade, the development of HVCMOS sensors has primarily focused on technology nodes ranging from 180 nm to 130 nm. To explore performance improvements in smaller technology nodes, a prototype of the next-generation HVCMOS sensor has been done using 55 nm high-voltage technology. This technology offers the benefits of smaller feature size and reduced power consumption. The prototype sensor chip was produced in a Multi Project Wafer (MPW) run. It is being tested currently.
The contribution will concern the analysis of data provided by Gas Electron Multiplier (GEM) detectors already installed in the Compact Muon Solenoid (CMS) experiment. We will focus on the correlations among the baseline current observed in the High Voltage (HV) system, the background radiation, and the Large Hadron Collider (LHC) beam luminosity. Additionally, an update on the discharge rates observed during this year’s operations will be provided.
With the streaming data acquisition scheme planned for the CBM experiment, the quality of event reconstruction depends on the accuracy of clock and time distribution. The Timing and Fast Control (TFC) system ensures that all the readout FPGA boards are aligned in time on the sub-clock and the absolute scales. This is achieved by distributing the time information over an optical link with deterministic latency and clock recovery. In this work, implementation of reliable deterministic time forwarding has been explored. This allows for a scalable multi-hop architecture, to handle the large number of FPGA boards planned in the experiment.
The High-Luminosity upgrade of the LHC (HL-LHC) will triple the proton-proton collision rate, posing challenging requirements for the ATLAS trigger and readout system. A low-latency, FPGA-based hardware trigger for muons in the barrel region will be implemented to identify candidates within 1.7 μs from collisions for further refinement by the Monitored-Drift-Tubes-Trigger-Processor. An additional layer of RPC detectors and the replacement of the trigger and readout electronics will keep high efficiency for both single-muon and multi-muon triggers, without any rate increase compared to the current one, despite the higher collision rate. Tests are progressing to be ready for HL-LHC operations.
The Phase-II Upgrade of the LHC will increase its instantaneous luminosity by a factor of 7. At the HL-LHC, the number of proton-proton collisions in one bunch crossing increases significantly, putting more stringent requirements on the LHC detectors electronics.
The ATLAS Liquid Argon calorimeter measures the energy of produced particles produced and feeds the ATLAS trigger to identify interesting events. To enhance the ATLAS detector physics discovery potential an excellent resolution and an accurate detection of the deposited time is crucial.
The computation of the deposited energy is performed in real-time using dedicated data acquisition electronic boards based on FPGAs.
Depleted Monolithic Active Pixel Sensors (DMAPS) using high-resistivity substrates offer a good signal-to-noise ratio for Minimum Ionizing Particle (MIP) detection as well as an enhanced radiation tolerance with respect to standard CMOS sensors. The fully depleted bulk and fast charge collection through drift enable the DMAPS technology for timing measurements in High Energy Physics (HEP) experiments. In this work, the in-lab calibration and the preliminary test-beam results of a new prototype, mini-CACTUS-V2 will be presented.
The High Luminosity Large Hadron Collider (HL-LHC) necessitates a complete replacement of the current Compact Muon Solenoid (CMS) silicon tracker due to harsh conditions. The Phase-2 Outer Tracker (OT) is designed with high radiation tolerance, increased granularity, and enhanced data rate handling. It will provide tracking data to the Level-1 trigger, maintaining sustainable trigger rates without compromising physics potential. Featuring modules with two closely spaced sensors read by custom front-end ASICs, it generates "stubs," allowing tracking at 40 MHz. This contribution will describe the quality assurance procedures and the calibrations used to ensure the functionality of the modules.
The data acquisition system of the Micro-Vertex Detector in the PANDA experiment, including the recent advancements in the design of the data concentrator (MDC) ASIC, will be presented. The MDC is a local digital controller on the detector module. The contribution describes the entire readout chain, encompassing the double-side microstrip sensors, the ToASt front-end ASICs, the MDC, the lpGBT links and the off-detector electronics. Recent performance results of the beam test at the Marburg Ion therapy facility are presented.
The high luminosity operation of the LHC will deliver collisions with a luminosity about 10 times the original design value. This poses a big challenge for trigger and data acquisition due to nearly 200 overlapping collisions, called pile up, within the same bunch crossing. Disentanglement of the pileup particles from those of interesting physics processes is achieved by implementing the Pile-Up Per Particle or PUPPI algorithm. We present the strategy for implementation of PUPPI at Level-1 trigger, focusing on the Hadron Forward Calorimeter detector of the CMS experiment. The features of the custom firmware developed for this purpose is discussed.
A phase locked loop (PLL) and a time to digital converter (TDC) have been developed for the FastIC+ chip, an 8-channel ASIC to readout fast timing detectors. The chip is designed to work with sensors such as multi-anode photo multipliers (MAPMTs), microchannel plates (MCPs), silicon photomultipliers (SiPMs), among others. The PLL generates the clock reference for the whole chip, including a high-speed serializer and the TDC. The voltage controlled oscillator (VCO) provides 16 phases at \SI{1.28}{\giga\hertz}. The TDC channels sample the phases of the VCO to obtain their LSBs, while their MSBs are obtained from the frequency divider.
Based on the fourth generation synchrotron radiation light source, the stability of X-ray beam is an urgent problem to be solved in current cutting-edge experiments. This project is based on fast response time of diamond detectors. A fast response four channel weak current measurement and data acquisition circuit based on diamond detectors was developed using ADA4530. Experimental tests show that when the weak current is greater than 10pA, the circuit has an error of 1.3%. Moreover, for weak currents of the pA level, it can measure and refresh the beam position above 10kHz, and achieve 24 bit high-precision signal acquisition.
Verification is a critical aspect of designing Front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks, such as clock generation, reset handling, configuration, as well as hit and fault injections. The components were developed as part of the CHIPS initiative and they have been successfully used in the verification of multiple HEP ASICs.
Special considerations have been made in the design to reduce digital state changes and ensure reliable operation, we tested the effectiveness of the protection by running separate chips inside the proton beam, and layout is that all chips concurrently fit into a 20 mm beam spot. The
study of corrected bit flips in registers and actual SEEs in LCB and LP path is carried out under different energies. The preliminary estimate there will be approximately Ο(10) corrected bit flips per HCC bit per year at the HL-LHC. The total ionizing dose effect is monitored as well during the experiment.
Monolithic active pixel sensors are considered as the nominal choice for a large variety of particle physics experiments. Consequently, the design of pixel matrices faces a wide range of specifications.
We developed a pixel matrix read-out architecture based on the local interconnection of asynchronous N:1 time arbiters with fixed priority. This architecture is not limited by global signals and can achieve high bandwidth with a fully column-parallel stream. Layouts of a small prototype of 32x32 pixels were completed in a 65 nm CMOS imaging process, for various combinations of controllers with ratios from 64:1-2:1 with a pixel size of 25x16µm2.
In preparation for the High-Luminosity-Upgrade of the Large Hadron Collider, new silicon strip detector modules need to be built for the ATLAS ITk strip tracker. The powerboard flexes in ITk strip modules are responsible for powering all readout electronics as well as controlling and monitoring module voltages, currents and temperatures. In total, about 6000 end-cap powerboards need to be assembled into functional modules. This contribution summarizes the latest status of the powerboard mass production performed at the University of Freiburg including developed setups, latest results from quality control measurements and the challenges encountered with varying flex quality in single batches.
To mitigate the impacts of pileup caused by luminosity increase in the ATLAS Phase-II upgrade, the High Granularity Timing Detector (HGTD) is proposed to measure the timing of tracks precisely. The Peripheral Electronics Board (PEB) is an important part of the HGTD, which acts as a bridge between the front-end modules and the off-detector electronics. We have designed and produced a prototype PEB board, named PEB 1F. Our tests, especially the comparative testing between the PEB 1F and a dedicated front-end module test setup based on a commercial evaluation board (ZC706), will fully evaluate the performance of the PEB 1F.
The COMET (COherent Muon to Electron Transition) experiment at J-PARC requires particle detectors on the beam axis for proton and muon-pion flux monitoring. The GAROP-2 (GAted-ReadOut Proton 2) is thus dedicatedly developed as the read-out electronics for the diamond or SiC monitors. The detectors and GAROP-2 are gated off at the proton pulse phase to prevent it from saturation. Added to this version of GAROP-2 is an auto-tuning threshold circuit for each read-out channel, which can address the problem of inconsistent device baseline. We ordered fabrication and tested the performance of the GAROP-2.
After Run III the ATLAS detector will undergo many upgrades to cope with the harsher radiation environment and increased number of proton interactions in the high luminosity phase of the LHC. One key project of this upgrade is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out at 1,28Gb/s with a BER at 95%CL less than 10^-12. The Optosystem performs opto-electrical conversion of signals from the pixel modules. We present recent results related to irradiation studies on Optosystem components, the powering system, the whole chain performance and the impedance measurement of the Optosystem.
The HGTD is a novel detector introduced to augment the new all-silicon Inner Tracker in the pseudo-rapidity range from 2.4 to 4.0, adding the capability to measure charged-particle trajectories in time as well as space. A prototype of Peripheral Electronics Board (PEB), which supports up to 55 front-end modules with 12 lpGBT, 9 VTRx+ and 52 bPOL12v, is developed to work as a bridge between the front-end modules and the off-detector TDAQ. The on-going R&D effort carried out to study the readout and transmission chips, and the other components, supported by laboratory test results, will also be presented.
Resistive Plate Chambers (RPCs) are versatile detectors widely used in HEP experiments due to their excellent timing resolution and efficiency. However, conventional gas mixtures used in RPCs include C2H2F4 and SF6, freon-based gas mixtures with high global warming potential (GWP). So, a transition to eco-friendly gas is necessary to reduce the environmental impact and long-term operation of RPC detectors. In this study, we present efficiency, timing and charge response measurements of glass RPC detector under different CO2 compositions. Measurements have been conducted on single gap detector using a VME-based data acquisition system.
This work focuses on Total Ionizing Dose (TID) test of LVDS receivers that will be used for the readout system of the ATLAS muon barrel spectrometer within the High Luminosity (HL)-LHC program. We designed an experimental setup that allows to investigate TID effects on power consumption and signal integrity, including variations in amplitude, rise/fall time, jitter, signal-to-noise ratio, as well as inferring on bit error rate. This TID test are being conducted at CERN CC60 facility that is equipped with a ~ 10 TBq 60Co radioactive source. After the irradiation, annealing effects will be assessed.
The High Luminosity LHC upgrade requires a full revamp of CMS Drift Tubes (DT) electronics due to trigger rates exceeding current capabilities. Leveraging optical and bandwidth advancements, this upgrade redefines DT electronics architecture. On-detector functions are streamlined for data processing relocation to a more accessible back-end. The On-detector Board for Drift Tubes (OBDT) is pivotal, integrating essential functions like slow control and time distribution. Design enhancements prioritize integration into CMS, with radiation-resistant components. OBDT deployment in a CMS sector alongside ATCA-compliant back-end prototypes marks a significant milestone. Rigorous testing ensures suitability for HL-LHC, promising enhanced performance in challenging conditions.
Particle tracking and imaging detectors are becoming increasingly complex, driven by demands for densely integrated functionality and maximal sensitive area. These challenging requirements can be met using 3D interconnect techniques widely used in industry. In this paper, we present the results of an evaluation of the 3D through-silicon-via (TSV) technology, using the Timepix4 integrated circuit as a test-vehicle. We will present the concepts for 3D integration and test results from TSV-processed chips bonded to custom-designed circuit boards conceived as proofs-of-principle for future detector modules.
In order to reduce the material budget and maximize the active area of sensors used in future experiments, a 30um thick lightweight flex has been produced. The presented fabrication technology coupled with novel interconnection technologies allows for compact packaging with a direct attachment of the chip connection pads to the flex. Beyond interconnection technologies such as Anisotropic Conductive Films and gold studs, we demonstrate the successful application and bonding of nanowires using bonding principles such as sintering and glue-assisted bonding. This contribution will present the module concepts as well as the first electrical and mechanical results from demonstrator modules.
The bus tapes required for ATLAS ITk strips are very challenging because of the data rates and lengths of the transmission lines. The impedances need to be very well controlled. The designs must allow for sensor operation at 500V. The required quality of the Ni/Au plating for wire bond pads is difficult to achieve for such large tapes. The tapes must be radiation tolerant and we have seen material that failed the tests. Custom Bus Tape Testing Robots have been produced to check all the electrical and dimensional requirements. Tapes are in production at CERN and Elgoline.
T2K is a long baseline neutrino experiment, entering Phase II with a Near Detector upgrade.
A challenge of T2K Phase II is the development and testing of the Front-end electronics boards
(FEB) for the read-out of the Super-FGD, new active tracking neutrino target. We hereby present
the performance tests confirming that the FEB aligns with design requirements, and the hardware
qualification of 243 FEBs through a custom QC test bench designed to detect and locate hardware
failures. Complete installation in the detector took place in March 2024, one year after the
beginning of the FEB mass production.
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The CMS Tracker Phase-2 Upgrade requires the production of new Strip-Strip (2S) and Pixel-Strip (PS) modules to cope with the requirements of the HL-LHC. All-together 47520 hybrid circuits are required to construct 8000 2S and 5880 PS modules. The hybrids pre-production phase is now completed. At first, a kick-off batch enabled the identification of different issues, that were resolved for the completion of the pre-production. The various issues and respective solutions will be reported.
The Phase-2 Upgrade of the CMS Outer Tracker requires the manufacturing of 8000 Strip-Strip and 5880 Pixel-Strip modules, altogether incorporating 47520 hybrid circuits of 15 variants. To ensure complete functionality of the modules it is essential to perform production-scale testing of the hybrids before the module assembly. For that reason, a complex and scalable test system was designed, manufactured, and commissioned. However, difficulties with the system deployment exceeded expectations, which required extensive debugging and creative problem solving. The problems, solutions and lessons learned from the system deployment will be presented.
This work presents Twin_Peaks_CFD1, a custom analog front-end card designed for the read-out of PMTs coupled to lanthanum bromide scintillators. It integrates 16 discrete analog constant fraction discriminators (CFDs) on a compact 12x10 cm board, providing precise timing information for nuclear lifetime measurements.
The design emphasizes cost-effectiveness, utilizing off-the-shelf discrete components, as well as compactness, achieved through innovative use of miniature coaxial connectors and cables as delay elements. The minimalist analog shaper/discriminator design is devised without operational amplifiers, making use of only a handful of RF transistors and LVDS receivers in place of comparators.
Designed for accelerator beam diagnostics and photon science applications, KALYPSO is a line array camera that stands out for its high-speed performance with the ability to operate at rates upto 12 Mfps in continuous readout mode while maintaining full occupancy. In this contribution, the KALYPSO system with sensor based on TI-LGAD is presented. The latest version of this system is employed as a beam diagnostic imaging sensor to measure radiation profiles of the particle beam at the KIT accelerator, KARA. The system's key features will be presented, including its linearity, sensitivity, and dynamic range.
For the HL-LHC, the ATLAS experiment will replace its current Inner Detector with an all-silicon Inner Tracker (ITk), consisting of pixel and strip systems. In the end-cap, silicon sensor modules of the strip system are mounted onto support structures called “petals”. To facilitate the assembly of petals, an automated system has been developed for mounting which streamlines the production process and ensures uniformity. This contribution presents the latest results from the assembly of the first ITk pre-production petals, including characterization of their electrical performance and studies of their robustness at very cold (≤ −35 °C) temperatures.
The ATLAS ITk Pixel system requires large-scale flex circuits for low-voltage power, high-voltage sensor bias, and command/data transmission due to tight space constraints. This reports will focus on the design and production of the services that runs from the modules and the first patch panel of the ITk Pixel Outer Barrel. The results from the quality control tests on the pre-production (10% of what is needed to equip the final detector) will be discussed. In this report we also describe the procedure developed for the complex 3D bending needed to accommodate the routing and to respect the mechanical envelope.