TWEPP 2023 Topical Workshop on Electronics for Particle Physics

1 Oct 2023, 10:00 → 6 Oct 2023, 17:00 Europe/Zurich

Geremeas, Sardinia, Italy

Alex Kluge (CERN), Alessandro Cardini (INFN Cagliari, Italy)

The workshop covers all aspects of electronic systems, components and instrumentation for particle and astro-particle physics such as: electronics for particle detection, triggering, data-acquisition systems, accelerator and beam instrumentation.   
Operational experience in electronic systems and R&D in electronics for LHC, High Luminosity LHC, FAIR, neutrino facilities and other present or future accelerator projects are the major focus of the workshop.

The purpose of the workshop is:   
- Present original concepts and results of research and development for electronics relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities;   
- Review the status of electronics for running experiments and accelerators;   
- Identify and encourage common efforts for the development of electronics;   
- Promote information exchange and collaboration in the relevant engineering and physics communities.

The main topics of the workshop will be recent research and developments in the following areas:   
- Highly integrated detectors and electronics;   
- Custom Analogue and Digital Circuits;   
- Programmable Digital Logic Applications and Verification;   
- Optoelectronic Data Transfer and Control;   
- Packaging and Interconnect Technologies;   
- Radiation and Magnetic Field Tolerant Systems;   
- Testing and Reliability;   
- Power Management and Conversion;   
- Grounding and Shielding;   
- Design Tools and Methods.

The workshop programme will include invited plenary talks, sessions for oral presentations, poster presentations and a tutorial on "Digital Verification for FPGA and ASIC Designers". 

Agenda overview:

October 2, until 10:00, Registration

October 2, 10:00-11:50, Plenary presentations (organised by the local organising committee)

October 2 afternoon, October 3-5 all day and October 6 9:00-11:40, scientific program in plenary, parallel and poster sessions

October 2, evening, Welcome reception in conference hotel

October 4, afternoon, social activity

October 5, evening, conference dinner

October 6, 14:00-17:00, tutorial: Digital Verification for FPGA and ASIC Designers (https://indico.cern.ch/event/1255624/page/28776-training-tutorial, registration required)

Information about registration to the workshop and local organisation is available at: https://twepp23.ca.infn.it/

Authors are invited to submit abstracts and summaries describing original developments and new contributions, including recent progress, in the workshop topic areas.

Abstracts (max. 100 words long) and summaries (max. 500 words long) along an optional file containing diagrams or plots must be submitted through the Integrated Digital Conference tool at https://indico.cern.ch/e/twepp2023.

The summary will be the basis for paper selection. The summary should describe quantitative specifications of the work, challenges,  implementation and results.

Submissions without comprehensive summaries will not be considered. Submissions directly from the presenters are encouraged. Summaries should clearly describe the aspects of the work relevant to the topics of TWEPP.  Standard summaries targeted to physics or detector instrumentation conferences might need to be updated accordingly.

The submission deadline is 30 April 2023.    
*** No extensions are foreseen ***

Abstracts will be made available at the time of the workshop and will include all contributions selected for either oral or poster presentation.   
The proceedings of the workshop will be published in the peer-reviewed journal of Instrumentation, JINST.

Information concerning the workshop scientific programme and submissions is available at: https://indico.cern.ch/e/twepp2023 

Enquiries can be directed to the Workshop Secretariat, by email at twepp@cern.ch

Local organisation information is be available on https://twepp23.ca.infn.it/

Enquiries concerning the local organisation can be directed to the local organisation committee, by email at twepp2023@ca.infn.it

Scientific organisation   

A. Kluge (CERN, CH, Chair)
J. Alme (UiB, NO)
C. F. Bedoya (CIEMAT, ES)
A. Boccardi (CERN, CH)
J.P. Cachemiche (CPPM–IN2P3, FR)
A. Cardini (INFN, IT)
H. Chen (BNL, US)
S. Danzeca (CERN, CH)
D. Gascon (ICCUB, ES)
M. French (RAL, UK)
P. Gui (SMU, US)
M. Hansen (CERN, CH)
C. G. Hu (IPHC-IN2P3, FR)
C. Joram (CERN, CH)
A. Lai (INFN, IT)
A. Ricci (CERN, CH, Secretary)
A. Rivetti (INFN, IT)
W. Snoeys (CERN, CH)
F. Vasey (CERN, CH)
K. Wyllie (CERN, CH)
 

Organised by INFN, Istituto Nazionale di Fisica Nucleare, sezione di Cagliari and Università degli Studi di Cagliari with support from the European Organization for Nuclear Research (CERN).

TWEPP-2023_Poster.pdf

Sunday 1 October

Registration

Monday 2 October

Registration

Welcome

Convener: Alessandro Cardini (INFN Cagliari, Italy)

1 Opening

Speaker: Alex Kluge (CERN)

20231002TWEPPintroduction.pdf

20231002TWEPPintroduction.pptx

2 Introduction

Speaker: Alessandro Cardini (INFN Cagliari, Italy)

TWEPP-2023-Sardegna_V2-small.pdf

TWEPP-2023-Sardegna_V2-small.pptx

3 The search for gravitational waves from LIGO/Virgo/KAGRA detectors to Einstein Telescope: recent results and new frontiers of gravitational wave instruments and astronomy

Einstein Telescope is the future European Laboratory for gravitational waves. The discovery of gravitational waves (GW), in 2015, 100 years after the publication of Einstein’s general theory of relativity, was soon followed, in 2017, by the assignment of the Nobel prize for physics to three scientists of the LIGO-VIRGO collaboration. LIGO in the USA and VIRGO in Italy are, at present, the unique detectors worldwide capable to observe the GW signals. In 2017 with a coordinated effort of LIGO-VIRGO and a network of Telescopes on earth and in the space the gravitational waves signal from a neutron star collision was detected and combined with its electromagnetic counterpart, opening the era of multi messenger astronomy.

This provided the substantial momentum which led to the proposal of a third generation GW detector in Europe. In July 2021 Einstein Telescope was officially approved and inserted in the ESFRI program. The detector will substantially improve the current ones in sensitivity and in background suppression. In the present configuration it is designed as a triangle, underground, of 10 km per side, but a twin L shape system, with same concept of the LIGO detector is under consideration, There are presently two site candidates, one in Italy, in Sardinia, and one in the Netherlands, in the Limburg region.

This presentation will cover both the genesis of the project and the principles of GW detection, its technological challenges and an overview of the present status and future schedule.

Speaker: Alberto Masoni (Universita e INFN, Cagliari (IT))

ET TWEPP OCT-23.pdf

ET TWEPP OCT-23.pptx

4 Associazione "Sardegna verso l'UNESCO"

Speaker: Prof. Antonello Sanna

sanna - Sardinia towards Unesco Presentation_2 ottobre 2023.pdf

sanna - Sardinia towards Unesco Presentation_2 ottobre 2023.pptx

5 Sardinia cultural heritage: the nuraghi and nuragic civilization

Sardinia has an age old history told by a great cultural heritage and the nuraghi are probably the most important archaeological and cultural evidence. These majestic stone towers, built in the second millennium B.C., have represented a long term landscape marker and a symbolic reference point for Sardinian communities. Extraordinary ancient architects designed and built at least 7000 monumental buildings all over the island, big stone towers that were symble and centre of life of a great civilization. Sardinia territory still preserves many other archaeological evidences of this great people life, such as monumental tombs (giant's tombs), temples as sacred wells, sanctuaries, villages and an important bronze artifact production (axes, swords, figurines, ecc.). Nuragic people controlled the whole island from North to South, but were also involved in the main sea routes and traffics of the Mediterranean sea. Nuragic finds in Cyprus, Crete, Sicily, Spain, Northern Africa show us the important role of this civilization in the Mediterranean Bronze and Iron age trades and networks.

Speaker: Dr Giovanna Fundoni (Università degli Studi di Sassari)

conferenza Cagliari TWEPP.pdf

conferenza Cagliari TWEPP.ppt

12:30 Break

ASIC

Convener: Angelo Rivetti (INFN - National Institute for Nuclear Physics)

6 Performance of H2GCROC3, the readout ASIC of SiPMs for the back hadronic sections of the CMS High Granularity Calorimeter.

H2GCROC is the 130nm CMOS ASIC designed to read out the SiPMs coupled to the scintillating tiles of the back hadronic sections of CMS HGCAL (High Granularity Calorimeter). Each of its 72 channels is composed of a current conveyor, a high-gain preamplifier, a shaper, and ADC to read the energy, with two discriminators connected to TDCs for time-of-arrival and time-over-threshold information, respectively. This work presents the ASIC architecture and its characterization in lab and test beam, proving good adaptability in calibration, radiation tolerance, capacity to measure SiPM SPS (single-photon-spectrum), MIP's time and energy with high resolution.

Speaker: Jose David Gonzalez Martinez (OMEGA (FR))

H2GCROCv3_TWEPP_1_5.pdf

H2GCROCv3_TWEPP_1_5.pptx

7 First test results for ECON-T and ECON-D ASICs for CMS HGCAL

With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65nm CMOS, are radiation tolerant (200 Mrad) with low power consumption (<2.5 mW/channel). We report the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype including a comparison of single event effect (SEE) cross sections measured for different methods of triple modular redundancy.

Speaker: Cristina Ana Mantilla Suarez (Fermi National Accelerator Lab. (US))

CMS_TWEPP_2023.pdf

8 Testing and characterisation of the prototype readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker

This talk describes the characterisation and validation campaign of the prototype of the CMS Readout Chip (CROC), a 65 nm CMOS pixel readout ASIC for the CMS Inner Tracker upgrade for High Luminosity LHC. This validation campaign includes tests with single-chip and multi-chip modules, irradiation campaigns, test beams and wafer-level tests. The main results obtained in the testing of the CROC prototype will be outlined. Key improvements and fixes that have been implemented in the final version of the chip before the summer 2023 submission will be described.

Speaker: Michael Grippo (Universita e INFN Torino (IT))

crocv1-twepp2023-v2p1.pdf

Trigger and Timing Distribution

Convener: Alex Kluge (CERN)

9 CMS Level-1 trigger Data Scouting firmware prototyping for LHC Run-3 and CMS Phase-2

A novel Data Acquisition (DAQ) system, known as Level-1 Data Scouting (L1DS), is being introduced as part of the Level-1 (L1) trigger of the CMS experiment. The L1DS system will receive the L1 intermediate primitives from the CMS Phase-2 L1 trigger on the DAQ-800 custom boards, designed for the Phase-2 central DAQ. Firmware is being developed for this purpose on the Xilinx VCU128 board, with features similar to one half of the DAQ-800, and validated in a demonstrator for LHC Run-3. This contribution describes the firmware development in view of the target design for the DAQ-800.

Speaker: Mr Rocco Ardino (Universita e INFN, Padova (IT))

additional_figures.pdf

TWEPP-2023__l1scout__rardino_v1.pdf

10 Time and Clock Distribution Over a Hierarchy of Deterministic Optical Links

Accurate clock and time distribution is a key requirement for self-triggered streaming data acquisition in the CBM experiment. This distribution is handled by the Timing and Fast Control (TFC) system by clock forwarding and broadcasting the common time over latency-deterministic optical links in a hierarchical FPGA network. The point-to-point optical connections are served by the latency-optimized GBT-FPGA core, which has been developed at CERN. In the presented work, the performance of GBT-FPGA links for time and clock distribution in a scaled TFC system with multiple hops and endpoints has been investigated.

Speaker: Vladimir Sidorenko

twepp23_sidorenko.pdf

11 A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC

The RHIC interaction rate at sPHENIX reaches around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200. Critical measurements often require the analysis of particles produced at low momentum. This prohibits adopting the traditional approach, where data rates are reduced through triggering on rare high momentum probes. We propose a new approach based on real-time AI technology, adopt an FPGA-based implementation using a FELIX-712 board with the Xilinx Kintex Ultrascale FPGA, and deploy the system in the detector readout electronics loop for real-time trigger decision.

Speaker: Jakub Kvapil (Los Alamos National Laboratory (US))

TWEPP2023_JK_final.pdf

15:45 Coffee break

ASIC

Convener: Ping Gui (Southern Methodist University (US))

12 Design and characterization of RD53C production chips for ATLAS and CMS pixel upgrades at HL-LHC

The RD53 Collaboration, established in 2013 as a joint effort between ATLAS and CMS pixel ASIC communities on 65nm CMOS technology, is now in the phase of implementing final pixel readout chips, referred to as RD53C revisions, that will be used into upgraded pixel detectors at HL-LHC. The purpose of this work is to provide a comprehensive review of most important architectural design choices, enhancements, implementation details and verification flows adopted to submit final ATLAS and CMS production chips, along with preliminary test results and measurements.

Speaker: Luca Pacher (Universita e INFN Torino (IT))

LP_TWEPP2023.pdf

13 Performance of the COLUTA ADC ASIC for the ATLAS HL-LHC Liquid Argon Calorimeter Readout

The COLUTA ASIC is an 8-channel 15-bit 40 MSPS ADC fabricated in 65 nm CMOS for the upgrade of the readout of the ATLAS LAr calorimeter for the high luminosity LHC. The ADC architecture couples a 3.5-bit Multiplying-DAC (MDAC) stage to a successive approximation register (SAR) ADC with a digital back-end that outputs sample data continuously via 640 Mbps serial LVDS. The analog performance and radiation tolerance tests and measurements of the production COLUTA ADC will be presented, along with the robotic multi-chip test setup and procedures developed for the verification of 80,000 COLUTA ADC ASICs.

Speakers: Michael Himmelsbach (University of Texas at Austin (US)), Michael Himmelsbach (University of Texas at Austin (US))

Himmelsbach_Twepp_TA_v2.pdf

Himmelsbach_Twepp_TA_v2.pptx

14 Chips for calibration of the ATLAS LAr calorimeter

The LHC upgrade requires redoing the LAr calibration system which should provide a 16-bit range signal with 1‰ accuracy while being radiation tolerant. The former operating principle is used: a precise current is stored in an inductor, when it is switched off, a pulse is generated to be injected in the readout electronics. This is achieved by two chips: the first one, in TSMC 130nm, provides the 16-bit DAC as well as the calibration management system; the second one, in XFAB 180nm, embeds switches to generate the pulses. A description of both chips and measurement results will be presented.

Speaker: Mr Ludovic Raux (OMEGA (FR))

twepp_2023_lr.pdf

twepp_2023_lr.pptx

Trigger and Timing Distribution

Convener: Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))

15 Testing a Neural Network for Anomaly Detection in the CMS Global Trigger test crate during Run 3

We present the deployment and testing of an autoencoder trained for unbiased detection of new physics signatures in the CMS Global Trigger test crate during LHC Run 3. The GT test crate is a copy of the main GT system, receiving the same input data, but whose output is not used to trigger the readout of CMS, providing a platform for thorough testing of new trigger algorithms on live data, but without interrupting data taking. We describe the integration of the DNN into the GT test crate, and the monitoring, testing, and validation of the algorithm during proton collisions.

Speaker: Noah Alexander Zipper (University of Colorado Boulder (US))

TWEPP_AD@L1.pdf

TWEPP_Talk_Final_10_2_23.pdf

16 Real time data processing with FPGAs at LHCb

During the LHC Run-3 the LHCb software trigger is expected to reconstruct events at an average rate of 30 MHz. In view of future runs at even higher luminosities, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction within the current DAQ infrastructure. The most advanced of these sois a highly-parallelized custom tracking processor (“Artificial Retina”), implemented in state of the art FPGA devices connected by fast serial links. We describe the status of the development of a life-size demonstrator system for the reconstruction of pixel tracking detectors, that will run on real data during Run-3.

Speaker: Andrea Contu (INFN)

AContu_TWEPP2023.pdf

17 A full-function Global Common Module (GCM) prototype for ATLAS Phase-II upgrade

The baseline architecture for the ATLAS Phase-II upgrade has a single-level hardware trigger (Level-0 Trigger) with a maximum rate of 1 MHz and 10 μs latency. A full-function Global Common Module (GCM) prototype has been designed and implemented for the core part of the Level-0 Trigger, the Global Trigger. This GCM features two of the latest Adaptive Compute Acceleration Platform (ACAP) devices from Xilinx, the Versal Premium VP1802, plus twenty 12-channel 25.7 Gb/s FireFly optical engines. Presented here is the design process of this full-function GCM prototype hardware, with the focus on the technology choices and simulation results.

Speaker: Weiming Qian (Science and Technology Facilities Council STFC (GB))

ATL-COM-DAQ-2023-060.pdf

TWEPP2023award_ID81.pdf

FPGA Users Group

Convener: Ken Wyllie (CERN)

18 Experience with RFSoC for Beam Instrumentation applications

Speaker: Andrea Boccardi (CERN)

TWEPP_RFSoC.pdf

TWEPP_RFSoC.pptx

19 RFSoC used as a readout for Magnetic Microcalorimeters

Speakers: Luis Ardila (KIT-IPE), Luis E. Ardila

2023-10-02_TWEPP_RFSoC.pdf

20 Discussion

19:00 Reception

Tuesday 3 October

ASIC

Convener: Marcus Julian French (Science and Technology Facilities Council STFC (GB))

21 The Monolithic Stitched Sensor (MOSS) Prototype for the ALICE ITS3 and First Test Results

The MOSS (Monolithic Stitched Sensor) chip is a
monolithic pixel prototype chip measuring (\qty{25.9}{cm}\times\qty{1.4
}{cm}). It was designed to explore the stitching technique,
to investigate the achievable yield and as a proof of concepts for
the sensors for the ALICE ITS3 upgrade. It was manufactured in
early 2023.

This submission will focus on the MOSS chip and on its testing. It
will give an overview of the chip and describe the system developed
to characterize it. It will report on the early experience of
testing in the laboratory and include the first experimental results.

Speaker: Gianluca Aglieri Rinella (CERN)

abstract-summary.pdf

Aglieri-MOSS-Prototype-ITS3.pdf

Aglieri-MOSS-Prototype-ITS3.pptx

illustrations.pdf

TWEPP2023award_ID33.pdf

22 Validation of the 65 nm TPSCo CMOS imaging technology for the ALICE ITS3

During the next LHC Long Shutdown, the innermost three layers of the ALICE Inner Tracking System will be replaced by a new vertex detector composed of curved ultra-thin monolithic silicon sensors. The R&D initiative on monolithic sensors of the CERN Experimental Physics Department, in synergy with ALICE ITS3 upgrade project, prepared the first submission of chip designs in the TPSCo 65 nm technology, called MLR1. It contains four different test structures: CE-65, DPTS, APTS-SF and APTS-OPAMP, with different process splits and pixel designs. This work illustrates the validation of the technology in terms of pixel performance and radiation hardness.

Speaker: Chiara Ferrero (Universita e INFN Torino (IT))

TWEPP2023-ChiaraFerrero-03.10.2023.pdf

TWEPP-ChiaraFerrero.pdf

23 Development of monolithic pixel sensor prototypes for the CEPC vertex detector

The TaichuPix chip is a dedicated monolithic CMOS pixel sensor that is being developed for the first 6-layer silicon vertex detector prototype of the Circular Electron Positron Collider (CEPC) vertex detector R&D. Two small-scale demonstrator chips (25 mm$^2$) had been designed to optimize the in-pixel circuit and readout architecture, and to verify the radiation hardness. The positive results of the small-scale prototypes led to a submission of the first full-scale (2.6 cm × 1.6 cm) TaichuPix prototype in 2022. The design details and test results of TaichuPix prototypes and development of the readout electronics will be given.

Speaker: Wei Wei

TaichuPix_less.pdf

Programmable Logic, Design and Verification Tools and Methods

Convener: Johan Alme (University of Bergen (NO))

24 FLX-182, the hardware platform for ATLAS readout during High Luminosity LHC

FLX-182 is a PCIe card designed for the readout system of the ATLAS experiment for the High Luminosity phase of LHC starting in 2029. FLX-182 is responsible for decoding and transferring data from the front-ends into the host server memory, and receiving and distributing timing, trigger and control information. About six hundred FLX-182 will sustain 4.6 TB/s of total throughput at 1 MHz data rate. FLX-182 is equipped with a Xilinx Versal Prime VM1802 SoC, a PCIe Gen4x16 interface and can operate up to 24 optical links at 25 Gb/s. FLX-182 runs firmware capable of interfacing with all different subdetectors.

Speaker: Nikolina Ilic (University of Toronto (CA))

FELIXTwepp_Final.pdf

TWEPP2023award_ID78.pdf

25 The CMS HGCAL trigger data receiver

As part of the CMS Phase-2 upgrade, a prototype of the receiver of raw trigger data from the HGCAL endcap has been implemented using the Serenity ATCA platform. The receiver firmware was developed to test the unpacking of data from the front-end endcap trigger concentrator ASIC and measure its performance and stability. The firmware mainly consisted of unpacker blocks to decode ASIC packets, error detection mechanisms and online histogramming capability. The system was successfully used to achieve complete trigger path readout, involving several ASICs, and to test the stability of the system with online and offline monitoring.

Speaker: Raghunandan Shukla (Imperial College (GB))

HGCAL_Trigger_Readout_TWEPP2023_RSHUKLA.pdf

RAS_TWEPP2023_figures.pdf

26 Front-End RDMA Over Converged Ethernet, real-time firmware simulation

Several physics experiments are moving towards new acquisition models. In this work implementation of Remote Direct Memory Access (RDMA) directly on the front-end electronics has been explored, in this way is possible to free part of the computing farm's CPU resources. The work also introduces new verification techniques for verifying RDMA over Converged Ethernet (RoCE) firmware block developed at ETH, including real-time firmware simulation using Verilog Simulator. The result is a stripped down firmware version, allowing its implementation on smaller FPGAs, such as rad-hard parts.

Speaker: Gabriele Bortolato (Universita e INFN, Padova (IT))

TWEPP_2023_FERoCE.pdf

10:00 Coffee break

Invited

Convener: Alex Kluge (CERN)

27 Best Practices in Design Verification of ASICs for High Energy Physics Experiments

As the complexity and costs of ASICs designed for high-energy physics experiments continue to soar, verification emerges as a crucial factor in completing projects within reasonable timelines and budgets. Recognizing the escalating significance of verification, CERN and other high-energy physics institutes have invested significantly in enhancing the rigor of this essential process. In this talk, we emphasize the critical role of verification, delve into the unique challenges posed by ASIC designs in HEP, and discuss a set of best practices aimed at enhancing verification efficiency. By improving the quality of the verification process, these practices pave the way for predictable project execution and improved product outcomes. Drawing on successful experiences from ASIC verification at CERN and lessons learned from ineffective strategies, this talk provides valuable insights for achieving successful ASIC designs in high-energy physics experiments.

Speaker: Adithya Pulli (CERN)

hep_verification_maturity_model.pdf

invited_talk.pptx

ASIC

Convener: David Gascon (University of Barcelona (ES))

28 Characterization of the ATLAS Liquid Argon Front-End ASIC ALFE2 for the HL-LHC upgrade

ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC)2 shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution for small signals. ALFE2 is characterized using a Front-End Test Board (FETB) based on a Zynq UltraScale+ MPSoC and two octal-channel 16-bit high-speed ADCs. The test results indicate that ALFE2 fulfills or greatly exceeds all specifications on gain, noise, linearity, uniformity, and radiation tolerance.

Speaker: Dimitrios Matakias (Brookhaven National Laboratory (US))

Dimitrios_Matakias_03_10_2023_Twepp.pdf

29 Design and characterization of sub-10ps TDC ASIC in 28nm CMOS technology for future 4D trackers

4D tracking with ~10ps timing is crucial for reducing the combinatorial challenge of track reconstruction at high pileup densities, it offers completely new handles to detect and trigger on LLP and enables particle-ID capabilities at low transverse momentum. At the Muon Collider, the timing information will be essential for reduction of BIB. A high-precision TDC is a critical block necessary for enabling 4D tracking. We present the design and characterization of a 4-channel sub-10ps TDC ASIC in 28nm CMOS technology. The developed TDC is based on a novel 2D Vernier ring-oscillator structure with embedded sliding-scale technique for conversion linearity improvement.

Speaker: Larry Lou Jr Ruckman (SLAC National Accelerator Laboratory (US))

abstract figures.pdf

TWEPP 2023 - 28nm TDC .pdf

30 Recent developments in the IGNITE project on front-end design in CMOS 28-nm technology

The IGNITE project is developing solutions for the next generation of trackers at colliders. It plans to implement an integrated system module, comprising sensor, electronics, and fast readout, aimed at 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In the present paper we present recent advancements on the design of a prototype ASIC, exploring several circuital solutions on the front-end side, in view of the first IGNITE ASIC, featuring a 64x64 pixel matrix, which is being completed in the coming months.

Speaker: Sandro Cadeddu (Universita e INFN, Cagliari (IT))

23.10.03 - Recent developments in the IGNITE project.pdf

Programmable Logic, Design and Verification Tools and Methods

Convener: Alex Kluge (CERN)

31 SystemC framework for architecture modelling of electronic systems in future particle detectors

The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications.
This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, includes an event generator and interfaces with real physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy.
This contribution details the structure of the framework and describes a case study based on Velopix2.

Speaker: Davide Ceresa (CERN)

PixESL_twepp23.pdf

PixESL_twepp23.pptx

TWEPP2023award_ID123.pdf

32 Verification Environment for ALTIROC ASIC of the ATLAS High Granularity Timing Detector

ALTIROC3 is the second version of the ASIC for the ATLAS High Granularity Timing Detector to read out full size LGAD sensors (15x15 pixels of 1.3mm x 1.3mm). The ASIC, designed in 130nm technology, comprises around 250k flip-flops, more than 1000 8-bit configuration registers, and several clock domains and implements different analog IP-blocks critical for digital data acquisition and processing. This contribution presents the verification approach and tools employed, including a new System Verilog verification environment based on Universal Verification methodology (UVM) for functional, power and SEE verification, complemented with formal verification for Clock Domain Crossing (CDC) and Reset analysis.

Speaker: Simone Scarfi' (CERN)

Verification Environment for ALTIROC ASIC of the ATLAS High Granularity Timing Detector - Simone.pdf

Verification Environment for ALTIROC ASIC of the ATLAS High Granularity Timing Detector - Simone.pptx

33 Model and analysis of the data readout architecture for the ITS3 ALICE Inner Tracker System

The ALICE collaboration is developing the new Inner Tracker System 3 (ITS3), a novel detector that exploits the stitching technique to construct single-die monolithic pixel sensors of up-to 266 mm x 93 mm. ITS3 requires all hits from a particle flux of 4.4 MHz/cm2 to be transmitted on-chip to one of the sensor edges. This on-chip readout is limited by a power budget of 20 mW/cm2, a readout inefficiency of <2.5×10−3 and ≤10 % dead area. The model of ITS3 on-chip readout architecture will be presented, used to optimize the data flow implementation limited by physical and power budget constraints.

Speaker: Manuel Viqueira Rodriguez (Universidad Politecnica de Madrid (ES))

Abstrat_Summary_TWEPP2023_ManuelViqueiraRodriguez.pdf

Figures.pdf

SLIDES_Model_and_analysis_readout_architecture_ITS3.pdf

SLIDES_Model_and_analysis_readout_architecture_ITS3.pptx

12:20 Break

Tuesday posters session

34 Development of a multi-purpose DAQ system for Timepix4-based detectors.

We present the development of a data acquisition system dedicated to de-
tectors using the Timepix4 ASIC, developed in 65nm CMOS technology by the
Medipix4 Collaboration, as integrated front-end.
A control board is needed for system configuration and data acquisition,
up to the maximum bandwidth of 160 Gbps. To avoid the need for multiple
custom boards, we designed a system based on commercial hardware and a
user-configurable open-source firmware and software allowing for reusability and scalability of the system.

Speaker: Dr Nicolo Vladi Biesuz (Universita e INFN, Ferrara (IT))

Firmware_top_schema.png

35 28 nm front-end channels for the readout of pixel sensors in future high-rate applications

This work is concerned with the design and the characterization of front-end channels, developed in a 28 nm CMOS technology, conceived for the readout of pixel sensors in future, high-rate applications at the next generation of large particle accelerators.
Two front-end architectures are discussed. In the first one, an in-pixel flash ADC is exploited for the digitization of the signal, whereas the second one features a Time-over-Threshold (ToT) conversion. A prototype including the ADC-based front-end has been submitted and the characterization of the chip is discussed in the conference paper. Simulation results relevant to the ToT-based architecture are reported.

Speaker: Luigi Gaioni (University of Bergamo and INFN Pavia (IT))

36 32-channels mixed-signal processor for the tracking system of the GAPS dark matter experiment

This work aims to describe the experimental performance of a module consisting of four Lithium-drifted Silicon (Si(Li)) detectors and their readout electronics, which is the main component of a tracker in an upcoming balloon experiment. The activity is carried out within the GAPS (General AntiParticle Spectrometer) collaboration, whose scientific objective is the indirect detection of dark matter, through the detection of antiparticles present in low-energy cosmic-rays. The balloon flight is expected from McMurdo station in Antarctica in 2024. The main object of this study is the analysis of the readout electronic performance, with particular focus on the noise.

Speaker: Elisa RICEPUTI

37 40MHz trigger-less readout of the CMS Drift Tube muon detector

The Level-1 trigger scouting system of the CMS experiment aims at intercepting intermediate data produced by the L1 trigger processors, before the final trigger decision.
This system can be complemented by adding the raw stream of data collected from the detector front-end, where the throughput is manageable. An implementation of the triggerless readout is realized by reading a sector of the CMS Drift Tubes detector, which has been equipped with the preproduction of Phase-2 upgrade front-end boards. A Xilinx VCU118 acts as a concentrator of the Phase-2 demonstrator lpGBT links and transmits data to a server via 100G TCP/IP.

Speaker: Matteo Migliorini (Universita e INFN, Padova (IT))

PosterTWEPP2023.pdf

38 A high frequency radiation hardened DC/DC-converter with low volume air core inductor

The hfrh-buck (high frequency radiation hardened-buck) is a radiation hardened DC/DC-converter operating at a high switching frequency of 100MHz with a small air core inductor of 22nH. To ensure a high radiation dose, the circuit is designed with core transistors of a 65nm TSMC technology. By stacking the transistors of the power stage, the converter can be supplied with a voltage of up to 4.8V. Stable operation can be achieved at an output voltage of 1.2V with a maximum load current of 1A. The prototype demonstrates the ability to power parallel connected hybrid-pixel modules in the innermost layers.

Speaker: Jeremias Kampkötter

Twepp_2023_kampkoetter.pdf

39 A high time resolution and dynamic range monolithic pixel detector-ASIC for Micro Vertex Detector in PANDA experiment

A monolithic pixel sensor test chip for PANDA micro-vertex detector has been implemented in 180 nm HVCMOS technology on a high resistivity substrate. The sensor should have very high time resolution (1 ns sigma) and high dynamic range (up to 1000). The pixel electronics contains a Charge Sensitive Amplifier (CSA), a feedback circuit and two comparators. One comparator receives the fast signal and enables accurate time measurement. The other comparator receives the low pass filtered signal and is used for precise amplitude measurement. This publication presents several novel features of PANDA ASIC, its characterization and several measurement results.

Speaker: Hui Zhang

40 A prototype 4D-tracking demonstrator based on the TimeSPOT developments.

We present first results obtained with a prototype 4D-tracking demonstrator, using sensors and electronics developed within the TimeSPOT project, and tested on a positive charged pion beam at CERN SPS. The setup consists of six small tracking layers in a row, having area of about 3 mm squared each, three of which equipped with 3D-trench silicon sensors and three with 3D-column diamond sensors. The six layers are then read-out by a KC705 Xilinx board on a PC. We describe the demonstrator structure and operation and illustrate results on its tracking capabilities.

Speakers: Angelo Loi (Universita e INFN, Cagliari (IT)), Angelo Loi

4Dsetup.jpeg

A prototype 4D-tracking demonstrator based on the TimeSPOT.pdf

41 Adaptability and efficiency of the CMS Level-1 Global Trigger firmware implementation for Phase-2

We present details on the new Level-1 Global Trigger at CMS for the upcoming high-luminosity operation of the LHC. Our focus is on the newly developed firmware, which employs a bottom-up generic approach to enhance menu adaptability and accommodate the increase in upstream information. We also highlight our efficient pipelining strategy that ensures excellent routability at 480 MHz. Furthermore, we discuss the three Serenity boards for which a prototype exists, together with their current and future testing and validation endeavours.

Speaker: Benjamin Huber (Technische Universitaet Wien (AT))

Poster_TWEPP.pdf

42 An open-sorce IP-Core for Multi-Voltage Thresholding signal acquisition with FPGAs

High-speed multichannel ADCs are costly and require complex FPGA firmware to communicate with them. The Multi-Voltage Thresholding (MVT) approach can replace to some extent an external ADC with internal resources of an FPGA, thus reducing costs and complexity. The MVT approach needs only a few low-cost external components. The focus of the talk is presenting an open-source IP-Core that implements the MVT approach and simplifies implementation on a standard FPGA. The talk also provides an overview of characterization measurements and specific calibration methods. Our example application demonstrates the viability of the developed IP-Core for signal acquisition from multiple SiPMs.

Speakers: Dmitry Eliseev (Rheinisch Westfaelische Tech. Hoch. (DE)), Dr Dmitry Eliseev (Rheinisch Westfaelische Tech. Hoch. (DE))

2023-10-03-TWEPP-Poster-IP-Core_for_MVT.pdf

2023-10-03-TWEPP-Poster-Presentation-MVT-IP-Core.pdf

TWEPP2023_Eliseev_summary.pdf

43 AstroPix: A novel HV-CMOS pixel sensor for space-based experiments

A new application for monolithic pixel detectors is NASA’s AMEGO-X project [1], which is a low-orbit gamma ray observatory for multimessenger astrophysics, proposed as a 3 to 5 year mission. For the 40-layer gamma-ray telescope, which will consist of over 64000 sensors with a total area of more
than 25 m², a new low power < 2 mW/cm2 and high dynamic range 20 – 600 keV monolithic active pixel sensor with 500 um depletion thickness, named AstroPix, is currently being developed.

Speaker: Nicolas Striebig (KIT - Karlsruhe Institute of Technology (DE))

TEWPP2023_astropix_Nicolas_Striebig.pdf

twepp_2023_nicolas_striebig_references.txt

44 Characterization of the BigRock 28 nm Fast Timing Analog Front End

A full characterization of the BigRock high-speed, low-power analog front end (AFE) will be presented. The BigRock AFE previously described in [1] has been refined in a second generation testbed ASIC, Pebbles. The AFE utilizes a current-mode signal path that has been designed for 4D tracking applications with precision time resolution of order 50 ps. The preamplifier concept is based on a prior art current-feedback CMOS topology in [2]. An on-chip test bench comprised of a variable injection circuit and high-resolution TDC measures the AFE timing resolution. An array of integrated load capacitors and IO IPs enhance the characterization capability.

Speakers: Ms Amanda Simone Krieger (Lawrence Berkeley National Lab. (US)), Ms Amanda Simone Krieger (Lawrence Berkeley National Lab. (US))

TWEPP2022Poster_Krieger.pdf

TWEPP2023_Poster_Krieger_rev2.pdf

TWEPP2023_Poster_Krieger_rev2.pptx

45 CMS HGCAL Electronics Vertical Integration System Tests

In preparation for the High-Luminosity era of the LHC, the CMS experiment will replace the existing calorimeter endcaps with a novel device - the High Granularity Calorimeter (HGCAL), having around six million readout channels. The electronics system for this upgrade project is highly specialised and complex, involving multiple layers of data transfer, so testing must be carefully planned. The strategy has been to split the efforts between vertical (start-to-end) and horizontal (parallelisation) test systems. An important milestone for the former has been the development and operation of test systems to prototype one vertical slice of the future endcap electronics system.

Speaker: Milos Vojinovic (Imperial College (GB))

TestSystemBigPicture.png

TWEPP2023_Poster_MV_2.pdf

46 DC Power Circuit Evaluation for the Development of the Barrel Calorimeter Processor V2

The development of the CMS Barrel Calorimeter Processor (BCP) for the high-luminosity LHC poses a challenge due to strict power requirements. To minimize the risk of performance degradations or component damage, a project-specific and inexpensive evaluation board has been designed with multiple DC power circuits to safely test and evaluate them outside of the expensive BCP. The planned tests will verify several operating parameters of the power circuits, including output voltage, ripple voltage, and transient load. We will report on the results of these tests along with any roadblocks, their solutions, and lessons learned from this investigation.

Speaker: Stephen Goadhouse (University of Virginia (US))

Power Test Board TWEPP 2023 poster.pdf

47 Design and First Experience of the Prototype Pixel Layers for the ALICE FoCal

University of Bergen is involved in developing two calorimeters: (1) the pixel section of the Electromagnetic Forward Calorimeter (FoCal-E) for the ALICE Upgrade and (2) the Digital Tracking Calorimeter (DTC) for the proton Computed Tomography (pCT) prototype. Both designs utilize the ALPIDE sensors which are connected to aluminum-polyimide flexible cables applying Single-point Tape Automated Bonding (SpTAB). This contribution describes the development of the first multi-chip string prototypes, their performance, and the characterization of the high-speed links of the front-end electronics and towards the readout. Moreover, we present the experience with the prototypes both in the laboratory and test beam setups.

Speaker: Tea Bodova (University of Bergen (NO))

2023-04-21-18-01-figure.pdf

2023-04-21-18-01-TWEPP_abstract_2023_1.pdf

TWEPP_Poster_Bodova_Tea_Final.pdf

48 Design of a very low power 12 bits 40 MS/s ADC based on a time-interleaved SAR architecture

The paper describes a new figure of merit reachable in term of very low power dissipation for a 12 bit, 40MS/s Analog to Digital Converter in a CMOS 65nm process with 1V power supply. A differential time interleaved successive approximations register architecture is used. Each individual ADC channel is optimized regarding power consumption hence parallelizing 28 ADC channels in an analog memory like method, the total power consumption is only 280µW including all the reference voltage drivers and the digital sections. The total layout area of this converter is 0.87 mm2. Crosstalk simulations results will be discussed regarding channel-to-channel discrepancies.

Speakers: Bontems William, Daniel Dzahini (Tima Laboratory / CNRS)

Layout_28_channels.JPG

49 Design of the OBELIX monolithic CMOS pixel sensor for an upgrade of the Belle II vertex detector

The Belle II collaboration has initiated a program to upgrade its detector in order to address the challenges set by the increase of the SuperKEKB collider luminosity, targeting 6x1035 cm²s-1. A monolithic CMOS pixel sensor named OBELIX (Optimized BELLe II pIXel) is proposed to equip 5 detection layers upgrading the current vertex detector. Based on the existing TJ-Monopix2, OBELIX is currently designed in a CMOS 180 nm process. This new sensor introduces an extended pixel matrix, power regulators, fast hitOR information as inputs to the trigger system and a powerful readout logic matching the Belle II requirements.

Speaker: Dr Thanh Hung Pham (Centre National de la Recherche Scientifique (FR) - Université de Strasbourg)

OBELIX_Twepp_poster.pdf

50 Design Updates for HPSoC: A very high Channel Density Waveform Digitizer with sub-10ps resolution

We present the architectural design, prototype fabrication and and first results for the High Pitch digitizer System-on-Chip (HPSoC). The HPSoC is a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip is being fabricated in 65nm technology and targets the following features: picosecond-level timing resolution; 10 Gs/s waveform digitization rate to allow pulse shape discrimination; moderate data buffering (256 samples/chnl); autonomous chip triggering, readout control, calibration and storage virtualization; on-chip feature extraction and multi-channel data fusion.

Speaker: Dr Isar Mostafanezhad (Nalu Scientific, LLC)

avatar.svg

avatar.svg

51 Development and performance of a pixel chip for the readout of GEM detectors for high-rate particle tracking

In this talk we report the R&D program underway at CCNU to develop a pixel chip for the readout of GEM detectors appropriate for use in the CSR external-target experiment (CEE) at HIRFL for beam monitoring. The chip offers simultaneous Time over Threshold (ToT) and Time of Arrival (ToA) measurements, with an event-driven readout mode. The chips were tested with injected pulses and a Fe-ion beam of 350 MeV/u, coupled with single GEM. The position resolution, rate capability and reconstruction efficiency for the beam particles were characterized.

Speaker: Hulin Wang

Twepp2023_TopmetalCEE_poster_Hulin.pdf

52 Development of the Continuous Readout Digitising Imager Array Detector

The CoRDIA project aims to develop an X-ray imager capable of continuous operation in excess of 100 kframe/s. The goal is to provide a suitable instrument for Photon Science experiments at diffraction-limited Synchrotron Rings and Free Electron Lasers considering Continuous Wave operation.
Individual circuit blocks (adaptive-gain amplifier, analog-to-digital converter) were produced using a 65nm process and characterized, confirming expected performances.
A prototype has been designed, assembling said blocks in a pipelined, modular structure that can be replicated in a 2D pixel array.
Manufacturing is expected in spring 2023. Design architecture, expected performances and first test results will be reported.

Speaker: alessandro marras

Figure.png

poster_TWEPP2023_CoRDIA_v5.pdf

53 Electrical / piezo-resistive effects in bend Alpide - Monilitic Active Pixel (MAP) sensors

Upcoming upgrade of the ALICE Inner Tracking System (ITS3) foresees the use of wafer-scale MAPs bent into a cylindrical shape. Test beams employing the current ALICE Alpide chips, bent to foreseen ITS3 radii, showed that MAPs remain fully functional. However, some electrical effects, like (PS) power supply current changes and voltage shifts, were observed. The results suggest that these are caused by “piezo resistive effect” and FET threshold shifts, probably occurring in the pixel transistors. Some design architectures showed to be less susceptible to these effects and detailed investigations could help in design optimization. This contribution discusses latest test results.

Speaker: Marcus Johannes Rossewij (Nikhef National institute for subatomic physics (NL))

TWEPP2023E.pdf

54 GaN based DC-DC converters for high energy physics applications

This paper introduces a prototype of a GaN FET based 200 W DC-DC converter. Its design has been carried out to ensure optimal efficiency and minimal electromagnetic interference (EMI) issues that are commonly associated with the high switching frequency converters. To achieve this, hardware-in-the-loop (HIL) techniques have been used to enhance the control at high switching speed, and ANSYS HFSS-SiWave models have been developed to assess noise emissions based on the parasitic elements of PCB layout. Prototypes performance have been evaluated through extensive testing. This work offers insight into the potential of this technology in future physics detectors.

Speaker: Mr Guillermo Plumed Asensio (Aragon Institute of Technology Itainnova (ES))

TWEPP_2023_ITAINNOVA.pdf

55 HGTD PEB DC/DC Power Block in Low Temperature and Magnetic Field Operation

The High Granularity Timing Detector (HGTD) is an ATLAS Phase II upgrade project, the goal of which is to provide accurate time measurements for tracks to mitigate pile-up effect. DC/DC converters, BPOL12V, are implemented in the Peripheral Electronic Boards (PEB) and used to generate voltages for a bunch of ASICs. Due to the working environment constraints of HGTD, the BPOL12V will be operated in low temperature and under magnetic field. Therefore, it is essential to perform a comprehensive study of BPOL12V under different operation conditions. This report will present such study, including the BPOL12V efficiency, ripple and other.

Speaker: Mingjie Zhai (Chinese Academy of Sciences (CN))

DCDCconverter_Supporting_material.pdf

poster.pdf

56 Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are constantly challenged. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one is a full device with analog pixel circuitry suited for full-field fluorescence imaging, and the second one contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of EDWARD alone.

Speaker: Dominik Gorni (Brookhaven National Laboratory)

poster_TWEPP23_DG.pdf

TWEPP_23_FIGURES_AND_REFERENCES.pdf

57 Magnetic resilience studies for power supplies

In this poster we present our approach to design power supplies that are resilient to magnetic field that can reach up to 1 T, we will illustrate the engineering challenge to have a power supply that can safely operate in radiation and magnetic fields. We will summarize the test we have performed starting from basic components like inductors, then sub-parts and complete modules. We will illustrate the use case of the BRIC1 used by ATLAS-NSW as DC-DC intermediate converter stage and summarize its performance.

Speakers: Mr Alessandro Iovene (CAEN SpA), Dr Ferdinando Giordano, Simone Ivo Selmi

TWEPP23_PS-Magnetic-resilience-studies_FG.pdf

58 MIMOSIS2 validations using Cadence Protium platform and its Black Box flow

FPGA prototyping enables hardware acceleration for ASIC verification. Cadence Protium, an FPGA based platform, enables ASIC designers to prototype their RTL code in an easy and automatically way. As the RTL codes stay untouched during the process, the Protium provides a reliable model of the ASIC for early developments of DAQ and control systems. Protium advanced Blackbox flow allows in addition using external FPGA IP and running parts of the design at much higher speeds than what can be achieved by standard Protium flow. Its role in the validation of MIMOSIS2, an ASIC developed for CBM experiment, will be presented.

Speaker: Gregory Bertolone (Centre National de la Recherche Scientifique (FR))

Twepp23_GB - V2.pdf

59 Multi-Channel Radiation-Tolerant Humidity Monitoring System for the CMS Inner Cold Sub-detectors

In this presentation, we discuss a multi-channel radiation-tolerant and magnetic field-compatible humidity monitoring system developed for the needs of the CMS inner cold sub-detectors. The results of sensor irradiation tests, the tests conducted at different negative temperatures, and tests performed in the strong magnetic field are presented. Furthermore, a multi-channel readout unit has been designed, evaluated, and discussed. The proposed readout unit effectively nullifies both internal sensor parasitic effects and parasitic effects coming from long cables connecting the sensor to the readout electronics.

Speaker: Amar Kapic (EPFL/CERN)

Supplementary material - TWEPP 2023.pdf

60 On-beam system test of the new readout electronics for the CMS Electromagnetic Calorimeter upgrade

The High-Luminosity phase of the CERN Large Hadron Collider will pose new challenges for the detectors. The Electromagnetic Calorimeter (ECAL) of the CMS experiment will be equipped with a completely new readout electronics to cope with increase in the number of pp collisions per bunch crossing, as high as 200, and higher noise induced by radiation. Two on-beam vertical integration tests were performed at the CERN H4 facility using near-final components, installed in an ECAL Supermodule identical to the 36 Supermodules the barrel is made of. The data acquisition chain and the results of the test beam will be presented.

Speaker: Mattia Campana (Sapienza Universita e INFN, Roma I (IT))

On-beam system test of the new readout electronics for the CMS Electromagnetic Calorimeter upgrade_v2-6.pdf

61 Performance profiling and design choices of an RDMA implementation using FPGA devices

RDMA communication is an efficient choice for many applications, such as data acquisition systems, data center networking and any other networking application where high bandwidth and low latency are necessary. RDMA can be implemented using a large array of options which need to be tailored to the needed use case in order to get optimal results. Aspects such as the effects of using multiple simultaneous connections, using various transport functions such as RDMA Write and RDMA Send and communication models such as sending individual bursts or continuous streams of data will be investigated for implementing RDMA on FPGA devices.

Speaker: Matei Vasile (IFIN-HH (RO))

TWEPP_2023_poster-RDMA-performance.pdf

62 Prototype electronics for the silicon pad layers of the future Forward Calorimeter (FoCal) of the ALICE experiment at the LHC

A new Forward Calorimeter (FoCal) system has been proposed as part of the ALICE upgrades planned for LHC Run 4 which features a Si+W electromagnetic calorimeter. A first tower prototype corresponding to 1/5 of the nominal module of the electromagnetic calorimeter has been built in 2022. It is composed of 20 passive layers of tungsten absorber interleaved with 18 active layers of low-granularity silicon pads. Each pad layer is read out by 110 silicon pad sensors of 72 channels, amounting to a total of 1980 channels. This contribution describes the electronics developed from front-end to back-end.

Speaker: Olivier Bourrion (Centre National de la Recherche Scientifique (FR))

poster_focal_twepp_2023.pdf

Prototype electronics for the silicon pad layers of the future Forward Calorimeter (FoCal) of the ALICE experiment at the LHC

63 Prototype of a 10.24Gbps Data Serializer and Wireline Transmitter for the readout of the ALICE ITS3 detector.

A new silicon tracker detector (ITS3) will be installed in ALICE Inner Tracking System during the LHC long shutdown 3. We develop a 10.24Gbps Data Serializer and Wireline Transmitter (GWT-PSI) circuit for the readout of the detector. A 16-to-1 multiplexer architecture achieves low power consumption (28mW) and avoids high-frequency (> 640MHz) clock signals in the circuit. A clock-cleaning PLL and power-supply cleaning LDO will be built into the circuit making it immune to the noisy operation environment. A prototype has been submitted in the ER1 production run in the TPSCo 65nm ISC CMOS imaging technology.

Speakers: Arseniy Vitkovskiy (Nikhef National institute for subatomic physics (NL)), Dr Arseniy Vitkovskiy (Nikhef ( the Dutch National Institute for Subatomic Physics )), Mr Marcel Rossewij (Utrecht University), Vladimir Gromov (Nikhef National institute for subatomic physics (NL))

GWT_PSI_poster_26_09_23.pdf

GWT_PSI_poster_26_09_23.ppt

64 Radiation Tolerance Tests for SFP+ Transceivers

Results are presented for gamma and neutron irradiation tests for SFP+ transceivers. The radiation tolerance of the electronics components used in the detector area is a key of the electronics systems at high energy physics experiments. We tested four types of SFP+ transceivers from Ficer. Gamma rays were irradiated up to O(100) Gy at the Cobalt-60 facility of Nagoya University. Neutrons were irradiated up to O(10^12) cm^-2 using the tandem accelerator at Kobe University. The results can be referred to in selecting the SFP+ transceivers for high energy physics experiments.

Speaker: Daisuke Hashimoto (Nagoya University (JP))

TWEPP_poster_dhashimoto_final_submit.pdf

65 RD50-MPW: A monolithic High Voltage CMOS pixel chip with high granularity and high radiation tolerance

This contribution presents results from the RD50-MPW family of monolithic High Voltage CMOS (HV-CMOS) pixel chips, which are developed by the CERN-RD50 collaboration to study this technology in view of the harsh requirements imposed by future hadron colliders on tracking systems. Parameters especially considered in this programme are radiation tolerance, time resolution and granularity. This contribution reviews the design of RD50-MPW3, and presents its laboratory and test beam results. It also presents the design details of the latest prototype, RD50-MPW4. The prototypes developed so far are in the 150 nm High Voltage-CMOS (HV-CMOS) process from LFoundry S.r.l.

Speakers: Chenfan Zhang (University of Liverpool (GB)), Chenfan Zhang (University of Liverpool)

RD50_MPW_abstract_TWEPP_images_EV.pdf

TWEPP2023_Poster_Chenfan.jpg

66 SiC based beam monitoring system for particle rates from kHz to GHz

The extremely low dark current of silicon carbide (SiC) detectors, even after high-fluence irradiation, is utilized to develop a beam monitoring system for a wide range of particle range, i.e., from the kHz to the GHz regime. The system is completely built from off-the-shelve components and is focused on compactness and simple deployment. Beam tests on a 50 um thick SiC detector reveal, that even single particles of a 62.4 MeV proton beam (equivalent to 5.03 MIP) can be detected. Overall accurate results can be achieved up to a particle rate of $10^9$ particles per second.

Speaker: Simon Emanuel Waid (Austrian Academy of Sciences (AT))

twepp_main_p.pdf

67 Software mitigation scheme to increase availability under the radiation of microcontroller-based design for LHC accelerator environment

This paper addresses the challenge of mitigating the effects of radiation on the electronic systems of the Large Hadron Collider (LHC) by introducing BatMon, a battery-powered, MCU-based wireless radiation monitoring system. The paper proposes software mitigation schemes that can be used alongside an external watchdog to guarantee higher availability of the application without impacting the system performance. Tests conducted at the CHARM facility show that the proposed schemes enable BatMon to achieve 99.9996% availability in the harsh environment of the LHC. The manuscript highlights that the result obtained will also allow the system to be used for critical tasks.

Speaker: Alessandro Zimmaro (Universite Montpellier II (FR))

JINST_Using Software Mitigation Schemes to improve the availability of IoT applications in harsh radiation environment_rf_FS.pdf

TWEPP_2023_Software_mitigation_scheme_to_increase_availability_under_the_radiation_of_microcontroller-based_design_for_LHC_accelerator_environment.pdf

68 Status of the MDT Trigger Processor for the ATLAS Level-0 Muon Trigger at the HL-LHC

The MDT Trigger Processor (MDTTP) is a key ATLAS Level-0 Muon trigger upgrade component designed to meet High-Luminosity LHC requirements. The MDTTP will use MDT hits in the trigger for the first in ATLAS to improve the momentum resolution of muon candidates provided by RPC and TGC detectors and reduce fake muon trigger rate.

The MDTTP hardware is based on the Apollo ATCA platform. The pre-production prototype includes a VU13P-FPGA, high-speed FireFly optical transceivers, peripherals, and other improvements learned from using the previous hardware demonstrator. We present the prototype status, firmware implementation, core algorithm, slow-control software, and first integration tests.

Speaker: Rimsky Alejandro Rojas Caballero (University of Massachusetts (US))

MDTTP_TWEPP2023_v2.pdf

69 System Design and Prototyping for the CMS Level-1 Trigger at the High-Luminosity LHC

For the High-Luminosity Large Hadron Collider era, the trigger and data acquisition system of the Compact Muon Solenoid experiment will be entirely replaced. Novel design choices have been explored, including ATCA platforms with SoC controllers and newly available interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger data analysis will be performed through sophisticated algorithms, including widespread use of Machine Learning, in Xilinx UltraScale+ FPGAs. The system will process over 50 Tb/s of detector data with an event rate of 750 kHz. The system design and prototyping are described and examples of trigger algorithms reviewed.

Speaker: Tom Williams (Rutherford Appleton Laboratory (GB))

TWEPP2023-L1T-poster-TWilliams-v1.pdf

70 System level tests of large-scale multi-module prototype structures of the ATLAS ITk pixel detector

The ATLAS collaboration will replace its inner detector by an all-silicon tracker (ITk) for the HL-LHC. The new pixel detector will cover a sensitive area of 13m$^2$. The pixel modules are loaded on light-weight carbon structures in the form of (half)rings and staves. Electrically functional prototypes of these local supports based on the RD53A readout chip were built and extensive system-level tests of these structures were carried out evaluating serial powering, grounding and shielding, system monitoring, and the overall performance of the multi-module detector systems.
In this contribution, the results of these system tests will be presented.

Speaker: Sanha Cheong (SLAC National Accelerator Laboratory (US))

ATLAS_ITk_system_tests_TWEPP_20231003.pdf

71 Test and performance of the LiTE-DTU ASIC for the HL-LHC upgrade of the CMS ECAL barrel

A data conversion and compression ASIC, named LiTE-DTU, has been developed for the upgrade of the CMS electromagnetic calorimeter (ECAL) for the High-Luminosity phase of LHC. The ASIC integrates two 12-bit 160 MS/s ADCs, a data processing unit for gain selection and data compression, and a 1.28 Gb/s serializer.
The ASIC has been extensively tested in laboratory and in beam tests showing excellent yield and performance. The radiation tolerance has been verified with dedicated test campaigns for both total ionizing dose and single event effects. Results from these tests, showing the design readiness for mass production, will be presented.

Speaker: Fabio Cossio (INFN Torino (IT))

TWEPP2023_CossioFabio.pdf

72 Test Result of the New ASD2 Chips for Phase-II Upgrade of the ATLAS MDT Chambers at HL-LHC

For the
-II upgrade of the ATLAS Muon Spectrometer to the High Luminosity LHC
(HL-LHC), a new first-level muon track trigger is needed to make use of the high momentum
resolution of the Monitored Drift Tube (MDT). The current front-end electronics of the MDT
chambers do not meet these conditions, they have to be replaced. Therefore, a new ASD2
ASIC chip has been developed. Finally, 50000 ASD2 chips are needed for the ATLAS
experiment. The development of the final testing procedure and the reliability of a first batch
ASD2 chips will be presented.

Speaker: Katrin Elisabeth Penski (Ludwig Maximilians Universitat (DE))

poster_ATLAS_ASDchips_KPenski.pdf

73 The CMOS Pseudo-Thyristor: A Zero-Static Current Circuit for Pixelized Detector Front-End Stage

A novel ultra-low-power front-end discriminator circuit for pixelized detectors, named pseudo-thyristor, is described. It is based on a positive feedback topology using regular CMOS transistors with zero static current, rather than constantly drawing current in typical discriminators. When a small charge is injected at the input, the circuit flips rapidly due to the positive feedback and output a logic transition for further digitization. Simulation shows that in 65 nm process, it is capable of detecting at a threshold of 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40MHz operation.

Speaker: Dr Jinyuan Wu (Fermi National Accelerator Lab. (US))

PseudoThyristor2023f.pdf

74 The first full size full functionality ETROC2 (16x16) prototype for CMS MTD Endcap Timing Layer (ETL) upgrade

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

Speaker: Tiehui Ted Liu (Fermi National Accelerator Lab. (US))

ETROC2-TWEPP-2023-poster-v5.pdf

75 The Prototype Design of PEB - a Component of the HGTD In-detector Electronics for the ATLAS Phase-II Upgrade

The HGTD is a novel detector introduced to augment the new all-silicon Inner Tracker in the pseudo-rapidity range from 2.4 to 4.0, adding the capability to measure charged-particle trajectories in time as well as space.
A prototype of Peripheral Electronics Board (PEB), which supports up to 55 front-end modules with 12 lpGBT, 9 VTRx+ and 52 bPOL12v, is developed to work as a bridge between the front-end modules and the off-detector TDAQ.
The on-going R&D effort carried out to study the readout and transmission chips, and the other components, supported by laboratory results, will also be presented.

Speaker: Jie Zhang (Institute of High Energy Physics(IHEP), Chinese Academy of Sciences(CAS))

Zhangj's poster For TWEPP2023 1.2x0.9.pdf

76 The status of the Back-end card for the JUNO experiment

The Jiangmen Underground Neutrino Observatory (JUNO) aims to determine the neutrino mass hierarchy by detecting antineutrinos from nuclear reactors using a large liquid scintillator volume. The detector uses around 20,000 20-inch photomultiplier tubes powered and read out by two electronics readout systems: underwater and above water. The back-end card (BEC) is a crucial component of the latter and links 7,000 underwater electronics boxes to the trigger system. 180 BECs have been installed and tested at the JUNO site, including self-tests and combined tests. This presentation reports on the current status of the BEC and on the various test results.

Speakers: Yifan Yang (Universite Libre de Bruxelles (BE)), Dr Yifan Yang (iihe, ULB)

TWEPP_The status of Back-end card for JUNO experiment-20230430.pdf

77 Upgrade of the ATLAS Level-0 TGC Endcap Muon Trigger

The status of the development of the Level-0 endcap muon trigger system for the ATLAS experiment at the HL-LHC is presented. Integrations of the new trigger algorithms and the implementation with firmware on a new prototype of the trigger board (Sector Logic, SL) are also presented. Results from hardware tests of the SL prototype board and integration tests with the newly developed front-end board are also shown.

Speaker: Chihiro Kawamoto (Kyoto University (JP))

TWEPP2023kawamoto_v5.pdf

ASIC

Convener: Angelo Rivetti (INFN - National Institute for Nuclear Physics)

78 Digital on Top methodology for Monolithic Active Pixel Sensor, feedback from MIMOSIS sensors for CBM Micro-Vertex Detector

The CMOS Monolithic Active Pixel Sensor MIMOSIS being developed for the CBM experiment at FAIR will combine a spatial resolution of 5 µm with a time stamp of 5 µs and operate at peak rates of 80 MHz/cm². The full-scale prototype MIMOSIS-1 met these specifications , and the recently submitted MIMOSIS-2 has addressed shortcomings identified during the dense test campaign. Both complex mixed-signal circuits were developed using the Digital on Top methodology. We present the sensor design, introduce our design methodology and discuss the lessons learned during the design process.

Speaker: Frederic Morel (Centre National de la Recherche Scientifique (FR))

dot_maps_twepp2023.pdf

dot_maps_twepp2023.pptx

79 Tri-axis 5µm hexagon pixel-strip matrix combining 3*852 current comparator in a 180nm node

We present a new kind of sensors made of 5µm pixels using 6-metal TJ 180 nm technology. The pixels are interconnected among themselves to conducting lines with three directions 0°, 120° and -120°. Two neighbouring pixels are connected to different lines with different directions. The lines are connected to readout cells hosting current amplifier with its current comparator, together with the digital readout circuitry. In a 400 ns frame, the circuit can output the address position of up to 16 hits. The sensor of 0.5cm2 is intended to reduce the number of electronic channels while preserving the spatial resolution.

Speaker: Edouard Bechetoille (Centre National de la Recherche Scientifique (FR))

Twepp_PICMIC0_Appendix.docx

Twepp_PICMIC_2023_08_03.pdf

Twepp_PICMIC_2023_08_03.pptx

80 Lab measurement of UKRI-MPW0 after irradiation: an HV-CMOS prototype detector with a large breakdown voltage

An HV-CMOS (High-Voltage CMOS) prototype detector for particle detection in high energy physics experiments, named UKRI-MPW0, has been developed. This chip implements a novel sensor cross-section optimised for biasing the chip from the backside only and achieves an unprecedented breakdown voltage (> 600 V). With such a high breakdown voltage, UKRI-MPW0 is expected to achieve much improved radiation tolerance. The chip contains test structures for edge-TCT measurements and a matrix of monolithic pixels with integrated readout electronics. The design and detailed lab measurements of its pixel matrix after irradiation is presented in this contribution.

Speaker: Chenfan Zhang (University of Liverpool (GB))

attachment.pdf

TWEPP2023_Chenfan.pdf

Programmable Logic, Design and Verification Tools and Methods

Convener: Johan Alme (University of Bergen (NO))

81 Towards Single-Event Upset detection in Hardware Secure RISC-V processors

An increasing interest is growing towards reconfigurable processing systems embedded on the detector ASICs. Explorative work has been carried out to investigate Single-Event Upset (SEU) rates in open source RISC-V processors. The Ibex RISC-V core includes hardware security features that could detect SEUs in the core and alert the System-on-Chip (SoC) for possible malfunctions. This research addresses the possibility to rely on such hardware secure extensions for radiation hardness assurance.

Speaker: Prof. Jeffrey Prinzie (KU Leuven)

Towards Single-Event Upset Detection in Hardware Secure RISC-V Processors.pdf

Towards Single-Event Upset Detection in Hardware Secure RISC-V Processors.pptx

82 Fault Tolerance Evaluation Study of a RISC-V Microprocessor for HEP Applications

The use of a radiation-hard microprocessor or the application of a System-on-Chip (SoC) design methodology has a considerable beneficial impact on the future design of ASICs within the HEP community. The STRV (SEU-tolerant-RISC-V) is a Triple Modular Redundancy (TMR) protected RSIC-V microprocessor designed to withstand Single Event Effects (SEE) and operate close to a beamline or interaction point.
The results of evaluation studies on the impact of SEEs on the reliability of a RISC-V microprocessor-based system are presented. These evaluation studies include information derived from extended fault injection simulation and heavy ion testing of STRV-R1 samples.

Speaker: Alexander Walsemann

twepp_2023_strv-r1.pdf

83 Integrating lpGBT into the Common Readout Units (CRU) of the ALICE Experiment

In the ALICE read-out and trigger system, the present GBT and CRU based solution will also serve for Run4 without major modifications. By now, the GBT protocol has been superseded by lpGBT, and the GBT ASIC is not available for new productions. Extensions of the ALICE system (e.g. the planned FoCal detector) will therefore require to use lpGBT while keeping the compatibility with the existing system. In this presentation we show the implementation and testing of a possible integration of the lpGBT-FPGA IP into the CRU firmware, allowing the extension of the present system, keeping it more versatile and future-proof.

Speaker: Erno David (Wigner Research Centre for Physics (Wigner RCP) (HU))

TWEPP_2023_lpGBT_ALICE_CRU.pdf

16:20 Coffee break

Invited

Convener: Alex Kluge (CERN)

84 FPGA Firmware design with High Level Synthesis: Methodology, gains, and pitfalls

High Level Synthesis (HLS) of FPGA firmware using C/C++ has been popular in the design of upgrade trigger systems in High Energy Physics, allowing physicists with no previous firmware expertise to efficiently design digital systems. This presentation will describe the methodology of HLS designs, including comparison of basic building block design of HLS and Hardware Description language (HDL).
Design examples from the CMS L1 trigger system will be presented along with pitfalls to provide a proposed efficient approach to system design with these methods

Speaker: Dr Michalis Bachtis (UCLA)

TWEPP23_Bachtis.pdf

ASIC

Convener: Ping Gui (Southern Methodist University (US))

85 3D-integrated pixel circuit for a low power and small pitch SOI sensor

Targeting on low power consumption and high spatial resolution, the CPV-4 SOI pixel sensor requires about 100 transistors to implement the analog-digital mixed circuit functionality within a given pixel area around 16 um x 20 um. By utilizing 3D vertical integration, signal amplification and threshold discrimination are achieved in the lower-level circuitry, while hit information storage and sparse readout are achieved in the upper-level circuitry, thereby maximizing pixel size reduction and power consumption reduction. This work will present the pixel circuit design and the test results on the completed 3D chips.

Speaker: Yunpeng Lu (Institute of High Energy Physics, Chinese Academy of Sciences)

SOI-3D_YunpengLu.pdf

86 NAPA-P1: NANOSECOND TIMING PIXEL FOR LARGE AREA SENSORS

NAPA-p1 is a prototype Monolithic Active Pixel Sensor designed in 65 nm CMOS imaging technology, developed to meet requirements for future e+e- colliders. The prototype has dimensions of 1.5 mm × 1.5 mm with a pixel pitch of 25 μm. In nominal conditions, simulations show a pixel jitter of 350 ps-rms and an Equivalent Noise Charge (ENC) of 12 e-rms. The prototype will be characterized this summer, and the results shall be available soon. A discussion will be presented on future strategies to allow the scalability of this design into a large-scale sensor of 10 cm × 10 cm.

Speaker: Alexandre Habib

TWEPP_NAPA1_Presentation.pdf

Production, Testing and Reliability

Convener: Francois Vasey (CERN)

87 Reliability of Power Conversion Card for CMS MTD-BTL

The Minimum Ionizing Particle (MIP) Timing Detector (MTD) is introduced in the CMS experiment to measure the time of MIPs. The MTD consists of 432 Readout Units (RUs) in its barrel region (BTL), each powered by two Power Conversion Cards (PCC). PCCs host three radiation and magnetic field tolerant DC-DC converters. More than 1,000 PCCs will be produced to satisfy the assembly needs of BTL with sufficient margins. A reliability study has been conducted on a prototype batch of 80 cards to demonstrate the design and assembly robustness for up to 20 years of operation in BTL’s conditions.

Speaker: Tomasz Gadek (ETH Zurich (CH))

88 CMS ECAL VFE design, production and testing

Maintaining the required performance of the CMS electromagnetic calorimeter (ECAL) barrel at the High-Luminosity Large Hadron Collider (HL-LHC) requires the replacement of the entire on-detector electronics. 12240 new very front end (VFE) cards will amplify and digitize the signals of 62100 lead-tungstate crystals instrumented with avalanche photodiodes. The VFE cards host five channels of CATIA pre-amplifier ASICs followed by LiTE-DTU ASICs, which digitize signals with 160MS/s and 12bit resolution. We present the strategy and infrastructure developed for the testing, burn-in, calibration and assembly of the VFE cards. Moreover, we summarize the test results obtained with 60 prototype cards.

Speaker: Werner Lustermann (ETH Zurich (CH))

TWEPP_2023_VFE_W_Lustermann_v4.pdf

19:00 Committee dinner

Wednesday 4 October

ASIC

Convener: Adriano Lai (Universita e INFN, Cagliari (IT))

89 A low crosstalk 768-channel of 14-bit analog to digital converters for high resolution array of detectors.

This paper reports the design and measurement results of a 768-channel of 14-bit analog to digital converters. Each channel’s layout pitch is only 8.5µm with a sampling rate from 40KS/s up to 100KS/s. Testing results show a crosstalk about only +/- 1 LSB. The architecture of the circuit and the structure of the layout make it extensible to exceptionally large format of detectors beyond 1000 channels. The circuit is produced to be used as a side element for multi-channel readout systems or alternatively as an IP to be transferred inside very dense integrated circuits.

Speaker: Dr Daniel Dzahini (Tima Laboratory / CNRS)

TWEPP_2023_MASSAR_V2 [Enregistrement automatique].pdf

twepp_2023.pdf

90 Dual use driver for high speed links transmitters in the future high energy physics experiments

The paper presents a Dual Use Driver (DUDE) that is a component designed for the “Demonstrator ASIC for Radiation-Tolerant Transmitter” in 28nm (DART28) and is developed in R&D programme on technologies for future experiments. The driver operates at 25.6Gbps and it allows to drive either 100Ω transmission lines and optical ring modulators in a Photonics Integrated Circuit. The driver includes configurable pre-emphasis. The device will allow to demonstrate the feasibility of wavelength division multiplexing optical links operating with bandwidths in excess of 100Gbps per fiber that are capable of sustaining total ionizing radiation doses up to 10MGy.

Speaker: Mateusz Karol Baszczyk (CERN)

TWEPP2023award_ID151.pdf

TWEPP2023_dart28_output_driver_04102023.pdf

91 SET sensitivity study of a VCRO-based PLL for HL-LHC ATLAS HGTD

We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase-Locked Loop under a 63 MeV proton beam of instantaneous fluence 10^10 protons/cm²/s. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) for the High-Luminosity Large Hadron Collider (HL-LHC). Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. Results are extrapolated to the HL-LHC radiation conditions.

Speaker: Mr Maxime Morenas (OMEGA (FR))

twepp_pll_morenas.pptx

Production, Testing and Reliability

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

92 Reliability Run and Data Analysis of the Accelerated Aging of Present and Future Electrolytic Capacitors Installed in the Protection Systems of Superconducting Magnets of the Large Hadron Collider at CERN

This study evaluates the lifetime and aging process of the aluminium electrolytic capacitors to be used in the new protection systems of the High Luminosity LHC superconducting magnets. The accelerated testing and analysis of several groups of capacitors aged for more than one year provided insights into their expected lifespan and aging process. The results obtained have practical implications for maintenance and replacement schedules, as well as for selection and acceptance of capacitors for new Heater Discharge power Supplies (HDS) equipment. The knowledge gained from this study ensures the safety and reliability of the LHC and its electronic components.

Speaker: Josep Guasch Martinez (CERN)

2023_TWEPP_DQHDS_Slides.pdf

93 Overview of the production and qualification tests of the lpGBT

The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. Almost 200,000 chips have been tested with a production test system capable of exercising the majority of the ASIC functionality to ensure its correct operation.
Furthermore, specific individual qualification tests were carried out beyond the production tester limits, including radiation, multi-drop bus topology, inter-chip communication through different types of electrical links and jitter characterization.
In this paper, an overview of the production and qualification tests is given together with their results demonstrating the robustness and flexibility of the lpGBT.

Speaker: Daniel Hernandez Montesinos (CERN)

TWEPP2023award_ID160.pdf

TWEPP23_lpGBT_testing.pptx

94 Hybrid designs and kick-off production experience for the CMS Phase-2 Upgrade

The CMS Tracker Phase-2 Upgrade requires the production of new sensor modules to cope with the requirements of the HL-LHC. The two main building blocks of the Outer Tracker are the Strip-Strip (2S) and Pixel-Strip (PS) modules. All-together 47520 hybrid circuits will be produced to construct 8000 2S and 5880 PS modules. The circuit designs for the mass production were fine tuned and the kick-off batches were manufactured. The presentation will focus on lessons learned from the prototyping stage, design optimization details for the mass production, test results and yield from the kick-off batches.

Speaker: Mark Istvan Kovacs (CERN)

TWEPP_23_presentation_v1_compressed.pdf

TWEPP_23_presentation_v1_compressed.pptx

10:00 Coffee break

Invited

Convener: Francois Vasey (CERN)

95 Accelerators overview, outlook, differences, why do we need the different concepts, FCC/e+-/muon..., impact on detector R&D and electronics

Speaker: Prof. Dave Newbold (STFC Rutherford Appleton Laboratory (GB))

Electronics_for_colliders.pdf

ASIC

Convener: Christine Guo Hu (Centre National de la Recherche Scientifique (FR))

96 Design and Characterization of a precision tunable time delay integrated circuit.

Authors:
Akshay Naik, Erich Frahm, Roger Rusack, Diba Dehmeshki, Rohith Saradhy, Yahya Tousi

We present a design of a time delay circuit that we have developed for future applications in particle physics experiments. Our circuit has a dynamic range of 250 ps achieved in steps of 270 fs. The chip was fabricated in TSMC's 65 nm LP process and consists of an array of planar waveguides for fine control and LC lumped circuits for large scale delays. We will report on detailed characterization of the device including some recent results from radiation tests.

Speaker: Yahya Tousi

image001.png

TWEPP2023award_ID126.pdf

97 In-pixel AI for lossy data compression at source for X-ray detectors

This work introduces AI-In-Pixel-65, an ROIC test chip designed for pixelated X-ray detectors using a 65nm Low Power CMOS process. The study compares two data compression techniques, Principal Component Analysis (PCA) and AutoEncoder (AE), implemented within the chip's pixelated area to address I/O bottlenecks. Our design methodology utilizes high-level synthesis (HLS) and hls4ml, offering shorter design cycles and similar quality results compared to register-transfer level (RTL) flows. Results show PCA achieves 50-fold compression with a 21% pixel area increase, while AE offers 70-fold compression and similar area increase.

Speaker: Danny Noonan (Fermi National Accelerator Lab. (US))

Slides_InPixelAI_TWEPP.pdf

98 A simulation methodology for establishing IR-drop-induced clock jitter for high precision timing ASICs.

The combination of 3D tracking and high-precision timing measurements has been identified by the European Committee for Future Accelerators as a fundamental requirement to increase detection capabilities for future applications. Among others, on-chip high-quality clock is a key factor determining the overall resolution of Timing ASICs. However, in large and dense chips, power-grid drops can severely affect the non-deterministic jitter of the clock, representing a limit to the performances. This contribution aims at presenting a simulation framework based on commercial tools to evaluate power supply-induced jitter, providing a pre-silicon methodology to assess its impact on timing indeterminism.

Speaker: Gianmario Bergamin (CERN)

bergamin_presentation_twepp.pdf

bergamin_presentation_twepp.pptx

TWEPP2023award_ID55.pdf

Power, Grounding and Shielding

Convener: Hucheng Chen (Brookhaven National Laboratory (US))

99 Prototyping during pre-production: the re-design of ATLAS ITk strip tracker powerboards for the end-cap

For the construction of the future ATLAS strip tracker end-caps, six geometries of silicon strip detector modules were designed. Each module comprises one or two silicon strip sensors and several flexes holding the required readout electronics, designed to match the geometry of each module. Due to the large number of designs, two module geometries using two sensors per ring module were prototyped for the first time in 2022, and showed excessively high noise. This contribution presents an overview of the follow-up investigation to diagnose the issue, the subsequent powerboard re-design and results from the first prototypes in 2023.

Speaker: Dennis Sperlich (Albert Ludwigs Universitaet Freiburg (DE))

ATLAS-ITk-EC-Powerboards.pdf

100 CMS Outer Tracker Phase-2 Upgrade on-module powering

The Compact Muon Solenoid (CMS) Tracker Phase 2 Upgrade for the High Luminosity Large Hadron Collider (HL-LHC) will use two module types, 2S and PS, which contain different sensor configurations and custom ASICs. Guaranteeing the power integrity of all the built modules and for the full lifetime of the detector is crucial for the detector performance. This article describes the historical evolution of the powering architecture, the problems encountered, and the solutions implemented for the 2S and PS modules, as well as the final on-module powering strategy along with the data and modelling that led to it.

Speaker: Angelos Zografos (CERN)

CMS Outer Tracker Phase-2 Upgrade on-module powering.pdf

101 NEW GENERATION B-FIELD AND RAD-TOLERANT DC/DC POWER CONVERTER FOR ON-DETECTOR OPERATION

The design of a new DC/DC power converter capable of being integrated with a detector is described. It works in harsh environment and can supply up to 170 W per channel. Up to four modules, each one equipped with 8 channels, can be accommodated in a water-cooled compact crate with a small volume of 24 dm^3. Its electrical, environmental and thermal performance is detailed here.

Speaker: Emanuele Romano (Pavia University and INFN (IT))

New generation B-Field and RAD-tolerant DCDC power converter for on-detector operation.pdf

12:20 Break

14:00 Social activity

Thursday 5 October

Module, PCB and Component Design

Convener: Ken Wyllie (CERN)

102 Real-time Signal Processing and Data Acquisition for the Electric Field Detector (EFD-02) on the CSES-02 satellite

The Electric Field Detector (EFD-02) on board of the second China Seismo-Electromagnetic Satellite (CSES-02) will measure the ionospheric electric field components at a Low Earth Orbit (LEO) over a wide frequency band (DC - 3.75 MHz) and with less than 1 \muV/m/\sqrt{Hz} sensitivity. EFD-02 will measure the voltage differences between pairs of probes installed at the tips of four booms deployed from the satellite. In this work we describe the digital hardware section based on a Zynq SoC device in charge of signal processing and data acquisition and we show the instrument overall performances.

Speakers: GIammaria Rebustini (INFN Roma Tor Vergata), Gianmaria Rebustini (INFN Rome "Tor Vergata")

TWEPP 2023_Gianmaria.pdf

TWEPP 2023_Gianmaria.pptx

103 The OBDT-theta board: time digitization for the theta view of Drift Tubes chambers.

We present the design and performance of the new On-Board electronic for the Drift Tubes (OBDT) for the superlayer theta along the direction parallel to the beam-line, built to substitute part of CMS DT Muon on-detector electronics. The OBDT-theta is responsible of the time digitization of DT chamber signals for the theta view, allowing further barrel muons tracking and triggering. It's also in charge of part of the slow-control of the DT chamber systems. A prototype is being tested in the laboratory and in a demonstrator inside CMS, as well as the full functionality in real conditions, showing satisfactorily results.

Speaker: Javier Sastre Alvaro (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))

TWEPP_presentation_JavierSastre.pdf

104 The Trigger & Data Acquisition interface module of the Tile Calorimeter for the ATLAS Phase- II Upgrade

For the High Luminosity-Large Hadron Colider (HL-LHC) phase, the ATLAS Tile Calorimeter (TileCal) is undergoing a major upgrade with a complete redesign of the on- and off-detector electronics. In the new readout architecture, the calorimeter signals are digitised every 25 ns directly on-detector and transferred to the off-detector Tile PreProcessor (TilePPr) via high-speed optical links. The TilePPr reconstructs the energies from the digitised samples and transfers them through its Trigger & Data Acquisition interface (TDAQi) module to the ATLAS Trigger & DAQ system via fixed and deterministic high-speed optical links at speeds of 11.2 Gbps.

Speaker: Tigran Mkrtchyan (Heidelberg University (DE))

Tdaqi_Twepp23.pdf

TWEPP2023award_ID85.pdf

System Design, Description and Operation

Convener: Andrea Boccardi (CERN)

105 Design and implementation of the Hybrid Detector for Microdosimetry (HDM): Challenges in readout architecture and experimental results

This talk presents the Hybrid Detector for Microdosimetry (HDM), capable of providing a superior characterization of the radiation fiend. This is of critical importance in radiation therapy, where a better description of the radiation field can lead to a better treatment plan and, therefore, a better treatment outcome.
HDM is composed of a commercial gas microdosimeter, TEPC, and a tracker made of 4 silicon LGADs layers. This presentation will cover the challenges in implementing the HDM readout architecture, including synchronization and triggering, and will show first measurements obtained with clinical protons.

Speaker: Enrico Pierobon

TWEPP_Pierobon_2023_extended.pdf

TWEPP_Pierobon_2023.pptx

106 HEPS-BPIX40: the upgrade of the hybrid pixel detector for the High Energy Photon Source

HEPS-BPIX40 is a new hybrid pixel detector for the High Energy Photon Source in China. It is a full upgrade from BPIX20, with a 128 x 96 pixel matrix and 140 μm x 140 μm pixel size. The circuit operates in single photon counting mode with dual thresholds and programmable gains. The tested frame rate is 2 kHz in continuous readout mode. A detector module covers 3.7 cm x 8.1 cm and consists of 2 x 6 chips. The full system will have 40 modules and approximately six million pixels. This paper presents the detector's design and test results.

Speaker: Jie Zhang (Institute of High Energy Physics(IHEP), Chinese Academy of Sciences(CAS))

TWEPP2023-BPIX.pdf

107 A readout system based on SiPM for the dRICH detector at the EIC

The ePIC experiment at the future Electron-Ion Collider aims to use silicon photomultipliers as the photodetector technology for the dual-radiator ring-imaging Cherenkov detector (d-RICH). Despite their advantages for this low light application in high magnetic fields, SiPMs are sensitive to radiation and require rigorous testing to ensure that their single-photon counting capabilities and dark count rate are kept under control over the years. The presented results show the successful use of a complete prototype readout chain based on the ALCOR chip for SiPM characterization measurements and test-beam measurements using the d-RICH prototype.

Speaker: Luigi Pio Rignanese (INFN-BO)

Twepp 2023_Rignanese.pdf

10:00 Coffee break

Invited

Convener: Alex Kluge (CERN)

108 Advancing fusion energy: Meeting the challenges of diagnostics and electronics for the ITER project

In the pursuit of clean and sustainable energy, the International Thermonuclear Experimental Reactor (ITER) project has emerged as a beacon of hope. As the world's largest experimental fusion reactor, ITER aims to demonstrate the feasibility of fusion as a viable energy source. However, operating in a challenging nuclear environment presents numerous technical and engineering obstacles that must be overcome to ensure safe and reliable operation.
The diagnostic systems are critical to the successful and safe operation of ITER. They provide the means to observe, monitor and maintain plasma performance over extended periods of time. They provide accurate measurements of plasma behaviour and performance, including those required for protection of the machine and its control, as well as measurements required for physics studies. In total, about 50 diagnostic systems will be installed on ITER.
This presentation focuses on the development of diagnostics systems and the utilization of electronics within the ITER project. The harsh environment, characterized by high temperatures, intense neutron fluxes, and strong magnetic fields, poses significant challenges for electronics and instrumentation.
The first part of the presentation discusses the design and development of diagnostic systems for ITER. These systems encompass a wide range of measurements, including plasma temperature, density, and impurity content.
The second part of the presentation delves into the unique requirements and challenges associated with electronics used in the nuclear environment of ITER. The radiation effects, including total ionizing dose, displacement damage, and single-event effects, pose serious reliability concerns for electronic components. Radiation-hardened designs, materials, and techniques are discussed, along with strategies for mitigating radiation-induced failures and ensuring the longevity of electronic systems.
Finally, this presentation provides an overview of the research and development efforts underway in the field of diagnostics and electronics as part of the ITER project. By addressing the technical challenges and presenting the progress made, it aims to encourage the exchange of knowledge, collaboration and innovation in the field of electronics for nuclear fusion. The knowledge gained from this research will not only contribute to the success of ITER, but will also pave the way for future advances in fusion energy technologies.

Disclaimer: The views and opinions expressed herein do not necessarily reflect those of the ITER Organization

Speaker: Raphael Tieulent

TWEPP_2023_TIEULENT.pptx

Module, PCB and Component Design

Convener: David Gascon (University of Barcelona (ES))

109 Lessons from integrating CMS Phase-2 back-end electronics and first results from Serenity-S1, a production optimised ATCA blade.

The Serenity-S1 is a Xilinx VU13P based Advanced Telecommunications Computing Architecture (ATCA) processing blade that has been optimised for production. It incorporates many developments from prototype cards and where possible adopts solutions being used across CERN. It uses many new parts because commonly used parts have disappeared from the market during the semiconductor crisis with only some returning.

We discuss improvements to simplify manufacture, the performance of new components, some of the more difficult aspects of procurement, the performance of production-grade Samtec 25 Gb/s optical firefly parts and issues with the rack cooling infrastructure.

Speaker: Torben Mehner (KIT - Karlsruhe Institute of Technology (DE))

2023_10_05_Lessons from Serenity-S1.pdf

TWEPP2023award_ID218.pdf

110 Design, production and irradiation results of the new advanced front end electronics of CMS iRPC

New advanced front end electronics are designed for the improved RPCs of CMS experiment for data taking during HL-LHC era. This electronics is developed to read out the RPC detectors from both ends of a signal strip, using a new ASIC, iRPCROC, which triggers the Cyclone V FPGA to record the timing information, allowing the correct identification of the position along it. The on-chamber results of the test beams and commissioning at CMS with focus on performance of the electronics will be presented.

Speaker: Maxime Gouzevitch (Centre National de la Recherche Scientifique (FR))

Maxime_Gouzevitch_TWEPP_Design_Prd_IrradTests_iRPC.pdf

111 Constant Fraction Discriminator for NA62 experiment at CERN

The newly build Constant Fraction Discriminator (CFD) with an additional
Time over Threshold (ToT) measurement capabilities designed by Peter Lichard, CERN, will be presented. It operates in a wide dynamic range 1:150, with an excellent time resolution better than 70 ps over one order of magnitude. It is highly customizable for a different signal shapes and thresholds, thanks to a remotely programmable parameters through the DCS commands. Two outputs, each in NIM and LVDS standard, provide ToT information with programmable thresholds. The technical specification and performance measured with cosmic rays and in the high-intensity experiment will be shown.

Speaker: Michal Zamkovsky (CERN)

CFDillustration.png

TWEPP_2023.pdf

System Design, Description and Operation

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

112 ALICE ITS3: a bent stitched MAPS-based vertex detector

ALICE ITS3 is a novel vertex detector replacing the innermost layers of ITS2 during LS3. Composed of three truly cylindrical layers of wafer-sized 65 nm stitched Monolithic Active Pixel Sensors, ITS3 provides high-resolution tracking of charged particles generated in heavy-ion collisions. This contribution presents an overview of the ITS3 detector, highlighting its design features, integration and cooling, and the latest results from the ongoing development towards the final sensor. Furthermore, the presentation introduces the off-detector service electronics, which play an essential role in the readout, control, and power supply of the detector.

Speaker: Ola Slettevoll Groettvik (CERN)

2023-04-20-15-18-TWEPP__ALICE_ITS3.pdf

2023_10_05-TWEPP23-ITS3 - final.pdf

2023_10_05-TWEPP23-ITS3 - final.pptx

TWEPP2023award_ID26.pdf

113 The LHCb VELO Upgrade II: design and development of the readout electronics

The the LHCb collaboration proposes a Phase-II Upgrade of the detector, to be installed during the LHC Long Shutdown 4. Currently, the VELO collaboration is exploring new sensor technologies, and the benefits that would derive from adding a time stamp to the track reconstruction. The most recent advances in this field, and the potential candidates that can meet the VELO Upgrade-II requirements, will be presented. In particular, the current state-of-the-art prototypes in the development of ASICs with TDC-per-pixel architecture, the PicoPix ASIC (which is an evolution of the Timepix4 design) and the TIMESPOT ASIC, will be discussed.

Speaker: Antonio Fernandez Prieto (Instituto Galego de Física de Altas Enerxías (IGFAE) Universidade de Santiago de Compostela (ES))

TWEPP23_VELO_UII_readout.pdf

114 SciFi Front-End Electronics: Calibration and Results on detector performance

The LHCb Experiment is commissioning its first upgrade to cope with increased luminosities of LHC Run3, being able to improve on many world-best physics measurements. A new tracker based on scintillating fibers (SciFi) replaced Outer and Inner Trackers delivering an improved spatial resolution for the new LHCb trigger-less era, with a readout capable of reading ~524k channels at 40MHz. Fully automated calibration of SciFi Front-End Electronics is based on dedicated software tools and operational procedures, validated during SciFi commissioning. This oral presentation describes the SciFi electronics design, implementation, and calibration and presents results showing the detector's performance after commissioning.

Speaker: Ulisses de Freitas Carneiro da Graca (CBPF - Brazilian Center for Physics Research (BR))

SciFi Twepp23 Ulisses v5.pdf

SciFi Twepp23 Ulisses v5.pptx

12:20 Break

Link Users Group

Convener: Francois Vasey (CERN)

115 Introduction

Speaker: Francois Vasey (CERN)

116 lpGBT calibration

Speaker: Stefan Biereigel (CERN)

lpgbt_calibration_twepp2023.pdf

117 VTRx+ production ramp up challenges and status

Speaker: Csaba Soos (CERN)

VLplus_OptoWG_TWEPP2023.pdf

118 VL+ optical fibre plant preproduction status and production plans

Speaker: Dr Stefano Meroli (CERN)

OPTIFIB_TWEPP2023_USERGROUP_WP5_Oct2023_v1_0.pdf

OPTIFIB_TWEPP2023_USERGROUP_WP5_Oct2023_v1_0.pptx

119 The Design and Packaging Challenges of a High Density 25G Optical Engine

Speaker: Kevin Burt (Samtec Inc)

Micro electronics Users Group

120 Welcome

Speaker: Kostas Kloukinas (CERN)

MUG TWEPP2023 Kloukinas agenda.pdf

MUG TWEPP2023 Kloukinas agenda.pptx

121 EUROPRACTICE IC services and foundry news

Speaker: Mr Paul Malisse (Business Manager, imec IC-link (Europractice service))

231005_TWEPP23.pdf

122 EUROPRACTICE EDA tools for the HEP community

Speaker: Mr Mark Willoughby (STFC, Rutherford Appleton Laboratory)

123 CERN ASIC support and Foundry services news

Speaker: Alessandro Caratelli (CERN, EPFL)

2023.10.3_MUG_ASIC-Support_SoC.pdf

124 Open discussion

Radiation-Tolerant Components and Systems

Convener: Alessandro Cardini (INFN Cagliari, Italy)

125 Prototype measurement results in a 65nm technology and TCAD simulations towards more radiation tolerant monolithic pixel sensors

Early measurements on monolithic pixel sensor prototypes in the TPSCo 65nm technology indicate a different response and radiation tolerance (up to $5\times10^{15}~1\text{MeV}~\text{n}_{\text{eq}}/\text{cm}^2$) for different sensor layout and process variants, illustrating the importance of layout and process in the path towards increased sensor radiation tolerance. Using these measurement results, TCAD simulations provide more insight to link the macroscopic behaviour of specific sensor variants to the details of its structure. With this insight we can propose a new variant combining the advantages of several measured variants as a path to even better radiation tolerance for the next iteration.

Speaker: Corentin Lemoine (CERN / IPHC)

TCAD_towards_radiation_tolerant_MAPS_TWEPP23_Lemoine_bck.pdf

TWEPP2023award_ID144.pdf

126 Single Event Effects characterization of a commercial 28 nm CMOS technology

In the context of the Strategic R&D on Technologies for Future Experiments, the sensitivity to single-event-effects of a commercial 28nm CMOS technology was investigated through heavy-ion and proton tests. Two chips were designed to study single- and multi-bit-upset, single-event-transient and single-event-latch-up. Bit upsets were studied on both D-Flip-Flops and foundry SRAMs. LET of heavy ions ranged from 1.3 to 88.39 MeV/mg/cm2, with fluences of 5e6 ions/cm2 for each LET. Protons at 350 and 480-MeV were used. These results provide a comprehensive overview of the SEU sensitivity of the selected 28nm node, representing a milestone in its qualification for HEP applications.

Speaker: Giulio Borghello (CERN)

Single Event Effects characterization of a commercial 28 nm CMOS technology.pdf

Single Event Effects characterization of a commercial 28 nm CMOS technology.pptx

127 Characteristics and total ionizing dose response of 22nm Fully Depleted Silicon-on-Insulator

The radiation hardness of transistors in a 22nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2 ) with different back-gate bias configurations, up to 2 V. The investigation revealed that the performance is significantly affected by TID with their radiation response being dominated by the charge trapped in the buried oxide. Interestingly, the application of a back-bias of 2 V was not enough to compensate the TID-induced damage.

Speaker: Mr Gennaro Termo (École Polytechnique Fédérale de Lausanne (EPFL))

Characteristics_and_Radiation_Response_of_22nm_Fully_Depleted_Silicon_On_Insulator.pdf

Characteristics_and_Radiation_Response_of_22nm_Fully_Depleted_Silicon_On_Insulator.pptx

System Design, Description and Operation

Convener: Hucheng Chen (Brookhaven National Laboratory (US))

128 Outer Barrel services chain characterization for the ATLAS ITk Pixel Detector

For the high-luminosity upgrade of the ATLAS Inner Tracking detector, a new pixel detector will be installed to allow for a bigger bandwidth and cope with the increased radiation among other challenges. This contribution will present the evaluation of the Outer Barrel Pixel layer services chains. A full data transmission study covering data merging will be presented from the pixel module all the way to the FELIX data acquisition system, using most of the components foreseen for the detector. Challenges and results of the services chain of the Outer Barrel will be highlighted.

Speaker: Leyre Flores Sanz De Acedo (CERN)

Outer_Barrel_services_chain_characterization_for_the_ATLAS_ITk_Pixel_Detector_TWEPP2023_Leyre_Flores_final.pdf

129 ATLAS LAr Calorimeter Commissioning for LHC Run-3

To cope with the increase of the LHC instantaneous luminosity, new trigger readout electronics were installed on the ATLAS Liquid Argon Calorimeters.

On the detector, 124 new electronic boards digitise 10 times more signals than the legacy system. Downstream, large FPGAs are processing up to 20 Tbps of data to compute the deposited energies. Moreover, a new control and monitoring infrastructure has been developed.

This contribution will present the challenges of the commissioning, the first steps in operation, and the milestones still to be completed towards the operation of both the legacy and the new trigger readout for LHC Run-3.

Speakers: Florent Bernon (Aix Marseille Universite (FR)), LAr speaker committee

LAr-Calorimeter-Commissioning-Run-3-TWEPP2023.pdf

130 Cryogenic Charge Readout Electronics for the ProtoDUNE-II Program and DUNE

The upcoming ProtoDUNE-II program at the CERN neutrino platform will consist of 2 liquid argon time projection chambers, which will serve as demonstrators of the technologies that will be used in the first 2 far detectors of the Deep Underground Neutrino Experiment (DUNE). A core component of these detectors is the cryogenic charge readout electronics, which are immersed in liquid argon along with the detectors and are responsible for reading out charge signals from the anodes of the time projection chamber. This talk will discuss the design of these electronics and preliminary performance results from the ProtoDUNE-II assembly experience.

Speakers: Roger Guo Huang (Lawrence Berkeley National Lab. (US)), Roger Huang (Lawrence Berkeley National Lab. (US))

RogerHuang_TWEPP23_DUNECE.pdf

16:20 Coffee break

Invited

Convener: Hucheng Chen (Brookhaven National Laboratory (US))

131 How the discovery of Cold Noise delayed the production of ATLAS ITk strip tracker modules by a year

The construction of the ATLAS strip tracker barrel will require the assembly of 12,000 barrel detector modules over the course of 3.5 years. In 2022, during the module pre-production phase, modules were found to display clusters of noisy channels outside required specifications when tested at operating temperatures (-40 ºC), called “Cold Noise”. Extensive investigations into the cause and mechanism of Cold Noise interrupted pre-production and occupied most barrel module assembly sites. This contribution presents an overview of the year-long investigations into Cold Noise, the final identification of the underlying mechanism and necessary changes for the transition to production.

Speakers: Ian Dyckes (Lawrence Berkeley National Lab. (US)), Dr Matthew Glenn Kurth (Institute of High Energy Physics (CN))

TWEPP_Dyckes_Kurth.pptx

Thursday posters session

132 Development of quad-channel high resolution digital picoammeter for beam diagnostics

In particle physics applications the photon beam interaction with various materials can produce electric charge which can be measured as current and be used to diagnose particle trajectories, beam intensity, beam profile, position, and stability. SIRIUS, the new 3 GeV fourth-generation Brazilian light source, will make use of hundreds of low-intensity measurement instruments. This work aims at showing up and discussing the design details, challenges and test results of a four-channel high-performance digital ammeter, applied for general-purpose beam diagnostics.

Speaker: Mauricio Donatti (LNLS)

Poster193-Donatti-Development Quad-Channel Picoammeter.pdf

Diagrams

• BlockDiagram.SVG
• FirmwareArchitecture.SVG
• PowerSupply.svg

Pictures

• assembly.jpg
• mounted_pcb.JPG
• mounted_pcb_top_view.jpg

Results

• bandwidth_quad_channel.svg
• bandwidth_single_channel.svg
• noise_quad_channel.svg
• noise_single_channel.svg
• normalized-gain_quad_channel.svg
• normalized-gain_single_channel.svg
• statistics-gain-offset-error-log.svg

133 Evaluating the RFSoC as a Software-Defined Radio Readout System for Magnetic Microcalorimeters

Arrays of superconducting sensors enable particle spectrum analysis with superior energy resolution. To efficiently acquire data from these sensors, the readout electronics operating at room temperature must perform multiple tasks, such as real-time frequency demodulation. We designed a Software-Defined Radio (SDR) system composed of an MPSoC board, an analog-to-digital conversion stage, and a radio frequency front-end mixing stage to meet the system requirements. Nevertheless, utilizing an Radio Frequency System-on-Chip (RFSoC) could simplify the overall system by integrating the conversion stage and potentially eliminating the mixing stage. This work investigates the applicability of RFSoCs for the aforementioned use case.

Speaker: Robert Gartmann

Gartmann_TWEPP_Workshop_2023_v4.pdf

134 A common readout unit for multichannel array detectors at HIRFL-CSR

The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics, atomic physics, interdisciplinary science, and relative applications. A Common Readout Unit (CRU) has been designed for HIRFL-CSR to reduce the development time, production cost, and maintenance difficulties of the data transmission at HIRFL. With the Xilinx the Virtex 7 as its main FPGA, the CRU has 32 high-speed fiber optic interfaces to receive the data and two 10 Gigabit Ethernet links to transmit the data out. This paper will discuss the design and performance of the CRU.

Speaker: Xianqin Li (Institute of modern physics, Chinese Academy of Sciences)

A common readout unit for multichannel array detectors at HIRFL-CSR-Poster.pdf

135 A Charge-integration Pixel Detector Readout Chip Features High Frame Rate with in-pixel ADCs.

HYLITE (High dYmamic range free electron Laser Imaging deTEctor) is a charge-integration pixel detector readout chip designed for SHINE (Shanghai high repetition rate XFEL and extreme light facility). The chip features a frame rate of 10kHz and a successive readout mode. HYLITE200S is the third prototype chip in the HYLITE series, including correlated double sampling circuits to improve noise performances. The signal-to-noise ratio of the chip with a single 12keV photon injection is 9.31. To achieve high-speed data output, HYLITE200S incorporated a clock management block. Tests demonstrated that the data transmission can be achieved steadily at a speed of 3.125Gbit/s.

Speaker: Mujin Li (IHEP)

Poster_HYLITE.pdf

TWEPP2023_appendix.pdf

136 A Custom Discrete Amplifier-Shaper-Discriminator Circuit for the Drift Chambers of the R3B Experiment at GSI

This contribution presents a pragmatic approach to read-out electronics for drift chambers used in particle physics experiments, specifically for the R3B experiment at GSI. The proposed circuit design uses discrete miniature SMD components and LVDS inputs of a low-cost FPGA to achieve a performance similar to the classic ASD8 ASIC. The presented approach offers an attractive solution for small to medium sized detector systems that require specialized read-out electronics but cannot afford the high cost and development effort associated with ASICs.

Speaker: Michael Wiebusch (GSI Helmholtzzentrum für Schwerionerforschung GmbH)

20230426_111033.jpg

MWiebusch_poster_TWEPP23_printed.pdf

137 A High Time Resolution Monolithic Active Pixel Sensor with Node-Based, Data Driven and Parallel Readout for Vertex Detector in particle physics Experiments

We present the design of a high-time resolution MAPS sensor prototype MIC6_V1 based on a 55nm Quad-well CMOS Image Sensor process for the high energy physics experiment vertex detector application. In order to achieve high-spatial resolution, fast readout, and low power consumption, MIC6_V1 has implemented a new node-based, data-driven parallel readout architecture. The integration time is 5us, and by sharing VCO in the pixel group, the hit arrival time resolution can reach 10ns. The pixel size of MIC6_V1 is 23.6μm × 20μm. The pixel matrix is 64 rows by 64 columns, and the size of MIC6_V1 is 2.8mm × 2.8mm.

Speaker: Dr Le Xiao

138 A Low-Power Gated-Vernier Ring Oscillator TDC for Cryogenic Detectors

High-resolution time-to-digital converters (TDCs) are required for time-of-flight measurements in many applications, including particle identification for high-energy physics. FPGA-based TDCs are popular for such applications but suffer from limited resolution and high power consumption compared to custom ASICs. Full-custom TDC designs can also be integrated within multi-channel or pixelated front-end ASICs, thus eliminating power-hungry low-latency links to external FPGAs. Several applications for such integrated TDCs, such as photon time stamping in rare-event searches, also require cooled detectors and front-end electronics. Here we describe a full-custom TDC in 90nm CMOS technology designed for high-resolution and low-power operation in such cryogenic environments.

Speaker: Soumyajit Mandal

TWEPP_2023_Poster_TDC_rev.pdf

TWEPP_2023_Poster_TDC_rev.pptx

TWEPP_2023_TDC_figures.pdf

139 A novel Front-End for Monolithic Active Pixel Detectors ASICs

In this work, a low-power low-noise readout circuit for monolithic pixel detectors is presented. The design focuses on robustness and scalability for both reticle sized chips and stitched designs. The front-end includes a differential charge sensitive amplifier, a reset network and a two-stage discriminator. Threshold trimming is performed with a 3-bit DAC. The feedback capacitance is kept at 0.3 fF to boost the gain for low input charges. The gain is 0.4 mV/e-, the noise is 19 e- r.m.s. and the threshold dispersion after equalization is 68 e- r.m.s. Simulations at schematic level and post-layout extraction are presented.

Speaker: Ana Dorda (KIT - Karlsruhe Institute of Technology (DE))

140 A prototype readout system for the beam monitor at the CSR external-target experiment

Beam monitor is a sub detector for the CSR external-target experiment (CEE) at HIRFL, which is designed to monitor the beam status. A custom-designed pixel chip Topmetal-CEEv1 acts as the sensor for locating the position of each particle. In this paper, we present a prototype readout system for beam monitor. Injected pulse test and 241Am alpha test in the laboratory as well as beam test at HIRFL has been done to validate the functionality of the system. The results show that the system could control and configure the pixel chips and read out data from the front end electronics.

Speaker: Jun Liu (Central China Normal University CCNU (CN))

141 A Radiation Hardened IP Development Programme for 28nm CMOS Technology

The ASIC Design Group at RAL has commenced a three-year programme developing radiation-hardened 28nm circuits intended to provide verified building blocks for future projects. The aim of this programme is to complement and add to the CERN common IP library for 28nm. Our programme includes a range of utility circuits such as high precision amplifiers, a low power 12bit ADC for housekeeping, bandgaps, reference drivers, DACs, a 1Gbps Serializer for low-complexity readout, and more. To explore the benefits of the 28nm technology, a high-resolution LGAD front-end including a 20ps resolution TDC is also under development.

Speakers: Oliver Bowett, Stephen Bell (Science and Technology Facilities Council), Thomas Gardiner

MD28_Poster_841x1189mm_v1.pdf

142 An FPGA-based Data Aggregator for ATLAS ITK Pixel DCS System

During the ATLAS phase II upgrade, the tracking system of the ATLAS experiment will be replaced by an all-silicon detector called the inner tracker (ITK) with a pixel detector as the most inner part. The monitoring data of the new system will be aggregated from an on-detector ASIC called Monitoring Of Pixel System (MOPS) and sent to the Detector Control System (DCS) using a new interface called MOPS-HUB.
The hardware implementation and experimental results of the MOPS-HUB will be presented. In addition, mitigation techniques including Single-Event Upset (SEU) and Single-Event Transients (SET) for the new system will be introduced.

Speaker: Ahmed Qamesh (Bergische Universitaet Wuppertal (DE))

mopshub_test_setup_simple.png

143 An FPGA-based Front-end Module Emulator for the High Granularity Timing Detector Readout Module

The HGTD aims to mitigate the effect of large pile-up interactions in the ATLAS Phase II upgrade project by providing accurate time measurements for tracks. However, since HGTD readout modules are unavailable during early stage, an FPGA-based front-end module emulator is designed as a substitute for system testing. This emulator also provides a flexible and cost-effective means to verify the digital logic of the ASIC chip used in the HGTD readout module. This presentation offers a solution for replacing ASIC chips with FPGAs during system test, and also provides a method for verifying the design of an ASIC chip.

Speaker: Zhenwu Ge (Nanjing University (CN))

An FPGA-based Front-end Module Emulator for the High Granularity Timing Detector_V1_TWEPP2023.pdf

144 Beam test of a baseline vertex detector for the CEPC

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype, TaichuPix, based on a column drain readout architecture, has been implemented to achieve high spatial resolution and fast readout. A 6-layer telescope made by TaichuPix-3 chips and baseline vertex detector were tested at the DESY II TB21 beamline. This presentation proposes to show the architecture and beam test results of the baseline vertex detector prototype.

Speaker: Mr Tianya Wu (Chinese Academy of Sciences (CN))

Twepp_TaichuPix3_final0919.pdf

145 CMS ECAL Upgrade Front End card. Design and performance.

Upgraded version of the CMS electromagnetic calorimeter (ECAL) Front-End (FE) card is designed to provide the lossless data streaming and reliable control and synchronization of the on-detector Very-Front-End (VFE) units.
The initial card design, validated in the beam tests in 2018-2019, was significantly modified to support the fast and reliable access to the VFE cards components for initialization, calibration and optimization of the data flow. Details of this updated design, performance of the final version of the card as well as the quality control and quality assurance plane for the mass production stage will be discussed.

Speaker: Alexander Singovski (University of Notre Dame (US))

CMS_ECAL_FE_card.pdf

CMS_ECAL_FE_poster.pdf

146 Commissioning of the Test System for the Phase-2 Upgrade of the CMS Outer Tracker

The Phase-2 Upgrade of the CMS Outer Tracker requires the production of 8000 Strip-Strip and 5880 Pixel-Strip modules, altogether incorporating 47520 hybrid circuits of 15 variants. Module design makes the potential repairs unfeasible; therefore, performing production-scale testing of the hybrids is essential. Accordingly, a scalable, crate-based test system was designed and manufactured, allowing for parallel, high-throughput testing. To reproduce the operating conditions, the system was integrated within a climatic chamber, including the development of a remote control interface and the calibration of thermal cycles. The results and lessons learned from the system integration and commissioning will be presented.

Speaker: Mr Patryk Szydlik (Wroclaw University of Science and Technology (PL))

TWEPP_2023_Comissioning_of_test_system.pdf

147 Commissioning of the Upstream Tracker for the LHCb upgrade

This contribution presents the latest advancements in integrating the Upstream Tracker in LHCb, including deploying control software, data acquisition firmware, decoding algorithm, and data analysis software. Additionally, the progress of different tasks is detailed, along with plans for the immediate future. The main focus of this talk is on the assessment of detector performance, including environmental conditions, electronics performance at the nominal operating temperature, and efficiency and noise hits at the nominal detector operation conditions. Various quality-control tests and component performance verification is described, as data captured with the dedicated firmware, showing the steps of the detector integration in LHCb.

Speaker: Carlos Abellan Beteta (University of Zurich (CH))

148 Data acquisition system of the PANDA Micro-Vertex Detector (MVD)

The Micro Vertex Detector is a key component of the PANDA experiment at FAIR. This contribution focuses on the development of the Module Data Concentrator (MDC) ASIC for the configuration, time distribution and readout of the silicon microstrip subdetector system of the PANDA Micro-Vertex Detector (MVD). A first version of the MDC architecture has been developed on FPGA and integrated with the microstrip sensor and the front-end ASIC. The detector module has been integrated into the DAQ framework. The overall description of the MDC and the data acquisition system is presented and the first test results are discussed.

Speaker: Mrs Olena Manzhura (KIT - Karlsruhe Institute of Technology (DE))

TWEPP23_Poster_final.pdf

149 Demonstration of the digital readout chain in the NνDEx experiment

NνDEx is a proposed experiment to hunt for the neutrinoless double beta decay of 82Se, with a high pressure SeF6 gaseous TPC. The readout and DAQ system are important parts of the experiment. The readout plane placed in one endcap of the TPC consists of around 15,000 sensors for charge measurement. It is crucial to read out data from all of these sensors efficiently. This paper will introduce the design of the demonstrator system for the digital readout chain, including the front-end digital sensor array, the data aggregation module and the DAQ system in the back-end.

Speakers: Lei Lang (Central China Normal University), Kai Chen (Central China Normal University)

Diagram.pdf

150 Design and implementation of Neural Network based conditions for the CMS Level-1 Global Trigger upgrade for the HL-LHC

The High-Luminosity LHC upgrade will have a new trigger system that utilizes detailed information from sub-detectors at the bunch crossing rate, which enables the Global Trigger (GT) to use high-precision trigger objects. Novel machine learning-based algorithms will also be included in the trigger system to achieve higher selection efficiency and detect unexpected signals. The focus of this study is on optimizing the implementation of these novel algorithms, in particular software-based to more hardware-based optimizations are studied in detail. Finally, the study will analyse how the applied optimizations affect performance degradation and the model's resource footprint.

Speaker: Gabriele Bortolato (Universita e INFN, Padova (IT))

Poster_TWEPP2023_GabrieleBortolato.pdf

151 Design and measurements of SMAUG1, a prototype ASIC for voltage measurement using noise distribution

In this work, we present the design, test system, and measurement results of the SMAUG_ND_1 ASIC. The described circuit implements an indirect energy measurement algorithm based on noise distribution measurement. The algorithm is similar to the threshold scan procedure but is done with a single pulse. The chip implements the matrix of 7x7 pixels each with 8 independent comparators and a size of 75x75um. The work describes the measurement process and the results of the algorithm as well as a brief discussion of what can be improved in the next version of the ASIC.

Speakers: Grzegorz Jan Wegrzyn (CERN), Grzegorz Jan Wegrzyn (AGH University of Cracow)

Fig1.pdf

Fig2.jpg

Fig3.jpg

Fig4.png

SMAUG1_Twepp2023_poster.pdf

152 Design of the ASIC readout scheme for the JUNO-TAO experiment

One of the main objectives of the Taishan Antineutrino Observatory (TAO) is to accurately measure the reactor neutrino energy spectrum to provide precise input to the Jiangmen Underground Neutrino Observatory (JUNO). In this study, we designed a full potential readout system for TAO based on the Klaus6 chip.We also developed a mockup prototype based on the design, which includes 4 chips (up to 128 channels). The performance of the prototype has been carefully evaluated both at room temperature and at -50 ℃. Good performance is obtained on gain uniformity, charge linearity, equivalent charge noise, dynamic range, and recovery time.

Speaker: Jie Zhang (Institute of High Energy Physics(IHEP), Chinese Academy of Sciences(CAS))

Qumh‘s poster For TWEPP2023 1.2x0.9.pdf

153 Design updates for AARDVARCv4: Waveform Sampling System On Chip with Picosecond Timing Resolution

In this article we describe the measurement results on an “AARDVARC” prototype in 130 nm. AARDVARC is a multi-channel waveform digitizing and processing Application Specific Integrated Circuit (ASIC) front-end. We report on various performance metrics: fast sampling (10-14 Gsa/s), deep storage (32K samples), timing resolution (better than 5ps), low power consumption (<100mW/channel).

Speaker: Dr Isar Mostafanezhad (Nalu Scientific, LLC)

154 Development of FABulous: An Embedded FPGA Framework in 28nm CMOS

FABulous is an open-source eFPGA framework developed by the University of Manchester, enabling programmable digital logic to be integrated into ASIC designs. In 2023, our team plans to submit a 28nm CMOS ASIC and explore flatten versus hierarchical design using HVT devices for radiation hardening. This 28nm eFPGA design will use SUGOI and PGPv4 to program and move data in and out of the eFPGA. Post-PnR simulation results will be presented, along with full chip co-simulation with firmware/software for pre-tape out validation results.

Speaker: Larry Lou Jr Ruckman (SLAC National Accelerator Laboratory (US))

TWEPP2023-Fab28.pdf

155 Development of the data transmission architecture of the stitched sensor prototype towards the ALICE ITS3 upgrade

The ALICE experiment at the CERN LHC will replace the three innermost layers of the Inner Tracker System (ITS) with an innovative vertexing detector. A single-die stitched monolithic pixel detector of 1.8 cm x 26 cm designed in 65 nm CMOS imaging technology will be used to build these layers. The data communication is done via the 1.8 cm edge of the detector. This contribution will focus on the architecture, challenges and techniques used to aggregate and send off chip up to 46 Gb/s of data flux.

Speaker: Piotr Andrzej Dorosz (CERN)

Figure_PDorosz_LEC.pdf

TWEPP2023_Poster_PDorosz.pdf

156 Digital duty cycle correction system for clock paths in radiation-tolerant high-speed wireline transmitters

Ongoing developments in the field of radiation-tolerant high-speed transmitters (HST) aim to increase data rates above 25 Gb/s while increasing total ionizing dose (TID) tolerance above 1 Grad. The use of half-rate architecture imposes tight constraints on clock signal quality, in particular its duty cycle. Radiation degradation of transistors in the clock path causes duty cycle distortion (DCD), affecting the output signal quality of the HST. In this contribution, a digitally controlled duty cycle correction system suitable for HST is presented, which compensates for process, voltage, and temperature variation as well as radiation-induced duty cycle distortion of the clock.

Speaker: Adam Klekotko

poster_twepp2023.pdf

157 Digital processing and BLMASIC control prototype for the Beam Loss Monitor system in the SPS at CERN.

The Beam Loss Monitoring system plays a crucial role in the CERN's Super Proton Synchrotron beam monitoring and machine protection. With the upcoming renovation of the system, the acquisition electronics can be based on an innovative ASIC designed by CERN. This paper presents the development of the control and digital processing electronics for this BLMASIC, reviews the architecture and design choices, discusses implementation details, including the controls and redundancy schemes, and highlights some preliminary results. The conclusion outlines the future development steps, and emphasises the interest of this simple and robust architecture using LpGBT and VTRx for critical systems.

Speaker: Mathieu Saccani (CERN)

BLMASIC_control_and_processing_in_SPS_poster.pdf

158 Electronics Upgrade for the HADES MDC Drift Chambers

The drift chambers of the HADES spectrometer at GSI, Darmstadt/Germany, form its main tracking system. Designed more than twenty years ago, the whole front-end electronics chain is being replaced with state-of-the-art electronics.

The new analog signal processing is based on the PASTTREC ASIC, developed for the PANDA Straw Tube Tracker. The digitization of data happens in FPGA-based TDCs.

The main challenges of the project are the strict spatial constraints given by the experiment setup and the noise sensitivity of the large area gas detectors. In addition, the power consumption needed to be kept low due to thermal constraints.

Speakers: Jan Michel (Goethe University Frankfurt (DE)), Jan Michel (Goethe University Frankfurt (DE))

HADES_MDC_Electronics_TWEPP2023.pdf

159 FastRICH: a readout ASIC with precise time stamping for the LHCb RICH detector

The FastRICH is a readout chip designed by CERN and the University of Barcelona for the LS3 enhancements and the Upgrade II of the LHCb RICH detector. The 16-channel radiation-hard FastRICH will be capable of reading out MAPMTs, MCPs, and SiPMs, with peak hit rates up to 40MHz. The low-power readout, with 4 lpGBT/VTRx-compatible 1.28GHz SLVS output links, is optimized for bandwidth reduction, allowed by the use of a Constant Fraction Discriminator for timewalk compensation, a programmable hardware shutter, and a custom readout protocol. Preliminary simulations show ~7ps timing resolution, with a total power consumption of <10mW per channel.

Speaker: Andrea Paterno (CERN)

160 High-speed front-end electronics and digitisation system for the Crilin calorimeter with enhanced timing performance

Crilin – a semi-homogeneous, longitudinally segmented highly granular electromagnetic calorimeter with Cherenkov PbF2 crystals has excellent timing and improved radiation resistance. A two-channel front-end prototype was tested at CERN-H2 with 120 GeV e- using PbF2 and PWO-UF crystals, yielding a single-cel timing resolution <30 ps for energy deposits <3 GeV. Crilin prototype consists of two sub-modules, housing a 3-by-3 crystal matrices and layers surface-mount 10 um pixel-size UV-extended SiPMs, handled via a fully custom microprocessor-controlled front-end, providing signal amplification/shaping and all slow control functions. The relative CAEN-V1742 based 5Gsps digitisation system employs a custom ultra-low-jitter trigger distribution electronics.

Speaker: Daniele Paesani (LNF-INFN)

elec1.png

figproto1.png

161 Implementation and performance comparision of MMC firmware on RISC-V and ARM-based MCUs

The MicroTCA standard is widely used in the field of particle physics, and Advanced Mezzanine Card is the basic component of the MicroTCA system that requires module management control (MMC) for management. RISC-V is an open source ISA (Instruction Set Architecture) with extensive use. In this paper, we implement the MMC firmware on the MCU with RISC-V architecture. We build a universal standard library that is compatible with both the STM32F1XX and GD32VF1XX series MCU based on ARM and RISC-V architecture respectively. Interrupt response time is tested to compare real-time transaction processing performance of two popular processor architectures.

Speaker: Jie Zhang (Institute of High Energy Physics(IHEP), Chinese Academy of Sciences(CAS))

Suaq‘s poster For TWEPP2023 1.2x0.9v3.pdf

162 Ionizing Radiation Influence on 28-nm MOS Transistor’s Low-Frequency Noise Characteristics

In this paper, we explore Total Ionizing Dose (TID) effects on low-frequency noise characteristics of 28-nm bulk CMOS transistors. In order to better understand the bias dependence of noise characteristics, measurements were performed at several operating points, both in linear and saturation regions. The challenge of differentiating between DC-induced shifts and newly generated Random Telegraph Noise (RTN) centers contribution to the Power Spectral Density (PSD) curve change demonstrates the insufficiencies of current analysis methods. We present examples of irradiation-generated RTN defects as well as various TID effects on noise PSD curves with pre-existing RTN sources.

Speaker: Martin Apro

Figure 1 - Time domain and PSD example of RTN.png

Figure 2 - Absolute and normalized PSD of same-sized transistors (Variability).png

Figure 3 - Example of normalized PSD decrease caused by TID.png

Figure 4 - Irradiation-generated RTN defect (PSD and time domain).png

163 Method for extracting the single event upset cross section from error counts in triplicated error-correction code registers

Digital circuits exposed to radiation, e.g. at HL-LHC, are equipped with radiation-hardening features such as triple modular redundancy and error-correction codes. A method is developed to measure the single-event-upset cross section from error rate measurements in register banks that are protected by both ECC and TMR, taking into account the non-linear relationship between the cross section and the error rate. The method is employed to measure this cross section using data from irradiation tests of the ECON-T, an ASIC developed for the CMS experiment, and then to predict the error rate in the ECON-T during operation on the CMS detector.

Speaker: Jon Wilson (Baylor University (US))

164 MightyPix at the LHCb Mighty Tracker – Verification of an HV-CMOS pixel chip’s digital readout

A new HV-CMOS pixel chip, called MightyPix, is being developed for the Mighty Tracker, an upgrade planned for LHCb in anticipation of the HL-LHC. Extensive research is ongoing to study the tracks and occupancy at the Mighty Tracker. This data is now used to simulate MightyPix’s performance in the LHCb environment, with focus on the digital readout. First results show an efficiency of 99.7% for MightyPix for the highest hit rates expected at the Mighty Tracker, which reach 17 MHz/cm$^2$. The bottleneck was found to be the readout speed, which yielded new design ideas to further improve the digital readout.

Speaker: Sigrid Scherl (University of Liverpool (GB))

Poster_TWEPP_SigridScherl_MightyPix1.pdf

TWEPP_Abstract_SigridScherl_Figures.pdf

165 Mu2e calorimeter readout electronics: design, characterisation, and radiation hardness

The Mu2e CsI crystal calorimeter has high granularity, 10% energy and 500 ps timing resolution for 100 MeV electrons, and will achieve extremely high levels of reliability and stability and in a harsh operating environment. Each crystal is readout by two custom UV-extended SiPMs, with independent readout channels, coupled to custom front-end electronics boards, to provide individually programmable bias voltages, perform signal amplification and shaping, while monitoring currents and temperatures. The FEE design was validated for operation in high-vacuum and under 1T B-field. An extensive radiation-hardness campaign certified the FEE design for ionizing dose, displacement damage dose and single-event effects.

Speaker: Daniele Paesani (LNF-INFN)

f1.pdf

f2.pdf

166 Novel developments on the OpenIPMC project

In this contribution, we present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics experiments at CERN. We show the addition of new functions and support for new protocols in the controller mezzanine firmware. Finally, the latest changes and improvements to the board design are presented.

Speaker: Luigi Calligaris (UNESP - Universidade Estadual Paulista (BR))

twepp23_poster180_luigicalligaris_openipmc-pdfx4-v005.pdf

167 Performance of a novel charge sensor on the ion detection for the development of a high-pressure avalancheless ion TPC

We will report the performance of Topmetal-S chip, a charge sensor specifically designed to directly sense ions for the high-pressure ion TPC of N$\nu$DEx experiment for neutrinoless double-beta decay search.The signal waveforms were investigated with various experiments and chip configurations.The equivalent noise charge of Topmetal-S is measured to be 120 e$^{-}$.Different ions species, both with negative or positive charges, could be detected by the sensor.The mobilities of majority ion charge carriers are measured for negative (positive) species in air and SF$_6$ respectively.The expected precision of the drift distance reconstruction using different velocities of ion species are discussed for N$\nu$DEx experiment.

Speaker: Tianyu Liang (Central China Normal University)

Attach.pdf

168 Proof of principle for a novel PET detector

The interplay between High Energy Physics and Positron Emission Tomography detector development keeps providing encouraging outcomes of mutual interest, most notably observed in the development of scintillators, photon detectors, as well as the physics simulation tools. Our group develops PET detectors with the time of flight ability. In this work we present the 16-channel prototype which uses FBK SiPMs and the FastIC ASIC. The prototype has a 3mm pixel pitch and uses LYSO crystals for gamma detection. We present the construction, calibration, measured results and discuss future development
directions.

Speaker: Andrej Seljak (Jozef Stefan Institute (SI))

TWEPP2023.pdf

TWEPP2023v2.pdf

169 Radiation test of commercial of the shelf (COTS) optical transceivers in the frame of the beam position monitor (BPM) consolidation project for the Large Hadron Collider (LHC)

The consolidation of the Large Hadron Collider (LHC) beam position monitor (BPM) requires the deployment of about 5000 single-mode radiation-tolerant optical transmitters, working at 10 Gbps during 20 years of operation. While the use of the custom devices being designed at CERN remains the baseline for the project, 8 commercial of the shelf (COTS) optical transceivers have been evaluated as an alternative. This paper presents the results of the full characterization in radiation of these COTS devices, including cumulative effects and single event effects (SEE), evaluated during both data transmission and reception.

Speaker: Manoel Barros Marin (CERN)

cots_sfp-qsfp_radtest_twepp23_poster.pdf

170 Radiation Tolerance of the MUX64 for the High Granularity Timing Detector of ATLAS

The MUX64 ASIC is a 64-to-1 analog multiplexer developed to expand the ADC input channels in the peripheral electronics of HGTD for the ATLAS Phase-II upgrade. The MUX64 chips will be used in the radiation field of high-luminosity pp collisions at LHC to an integrated luminosity of 4000 fb^-1. The radiation hardness of MUX64 have been tested with 80 MeV protons and X-ray exposures for damages caused by NIEL and TID, respectively. The irradiated samples have shown tolerance to withstand the NIEL to a fluence of 3.21 × 10¹⁵ (Si 1 MeV neq/cm²), and the TID of 0.746 MGy (Si).

Speaker: Jie Zhang (Institute of High Energy Physics(IHEP), Chinese Academy of Sciences(CAS))

TWEPP2023_poster-rev0920_20230923144046.pdf

171 RD53A Quad Modules Production and QC for the ATLAS Inner Tracker Outer Barrel (OB) Demonstrator.

Thirty-four RD53a Pixel detector modules arriving from different assembly sites are received at CERN in order to be integrated into the ITk demonstrator. The modules will go through different production validation stages, to monitor any performance degradation before the last stage with a full system test on the demonstrator. To mimic real detector services, multiple modules integrated on special mechanical loading supports and cooled down with a Co2 plant are tested. The objective of the demonstrator is to study the module's performance between the reception stage to the final integration operation and to develop the necessary infrastructure needed for testing.

Speaker: Mr Yahya A R Khwaira (Université Paris-Saclay (FR))

172 SAQRADC: An on-demand, low-power, minimal footprint, 10-bit resolution charge-redistribution ADC with internal clock generation

A charge-redistribution ADC with 10-bit resolution is implemented in the TPSCo 65nm CMOS process. The design is intended for flexible on-demand monitoring of vital system signals, such as temperature, in MAPS detectors. The successive approximation principle is implemented using only two matched capacitors and a trimming DAC, while an internal clock generator and digital sequencer are used to generate control signals for stepping through the conversion phases. The clock generator has a programmable output frequency, allowing sampling rates of 50–500 kS/s. Layout area is minimized by optimizing the transistor count within the sequencer as well as careful full-custom layout.

Speaker: Nicholas St. John (Brookhaven National Laboratory)

TWEPP_2023_Figures.pdf

173 SiGe integrated chip readout for fast timing

Advances in timing detector technology require new specialized readout electronics. Applications demand high rep rates, below 10 ps time of arrival resolution and, low power. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc. in collaboration with UC Santa Cruz has developed a prototype SiGe front end readout chip optimized for low power and timing resolution (0.6 mW/channel, 10 ps of timing resolution for 8 fC). In this contribution the ASIC performance simulation and the results from the first prototype run will be shown.

Speaker: Dr Simone Michele Mazza (University of California,Santa Cruz (US))

160423_TWEPP_abstract.pdf

poster_TWEPP_2023.pdf

174 Silicon photonic, planar coupled, 4-channel WDM transmitter

We report on our current developments towards a silicon photonic, 4-channel wavelength division multiplexed transmitter system with planar fiber chip coupling. The optical core components consisting of the photonic chip and the connecting V-groove mounted glass fibers were assembled with sub-micrometer accuracy on a glass plate with low thermal expansion for a stable fiber chip coupling. This setup is ready to attach the DC-biasing and termination board as well as a fan-out board for 4x10 Gb/s drivers or a 4x32 Gb/s driver board. Experimental results of the optical and optoelectrical performance will be presented.

Speaker: Dr Marc Schneider (KIT - Karlsruhe Institute of Technology (DE))

CoupledWDMSystem_FanOutBiasBoards.jpg

TWEPP2023Indico_Schneider_SiliconPhotonicPlanarCoupled4ChannelWDMTransmitter.pdf

175 The Optosystem: validation and testing of the high-speed optical-to-electrical conversion system for the readout of the ATLAS ITk Pixel upgrade

After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the High Luminosity-LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs optical- to-electrical conversion of signals from the pixel modules. We present recent results related to the performance of the data transmission chain pivoted on the Optoboards and to the design, testing and production of the Optopanels.

Speaker: Silke Mobius (Universitaet Bern (CH))

Poster_TWEPP23_SilkeMobius_2.pdf

176 The Analog Front End for FastRICH: an ASIC for the LHCb RICH Detector Upgrade

This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout a wide range of detectors like Photomultiplier Tubes, to be used at the LHC Run 4 or SiPMs, candidates for Run 5. The front-end (FE) stage has an input impedance (Zin) below 50 Ω and an input dynamic range from 5 µA to 5 mA with a power consumption of ~5 mW/channel. The chip includes a Constant Fraction Discriminator (CFD) and a Time-to-Digital Converter (TDC) for digitization.

Speakers: Mr Rafel Manera Escalero (University of Barcelona (ES)), Rafel Manera Escalero (University of Barcelona (ES))

177 The End-of-Substructure (EoS) card for the ATLAS Strip Tracker Upgrade – from Design to Production

The ATLAS Strip Tracker for HL-LHC consists of individual modules that host silicon sensors and front-end electronics. The modules are then mounted on carbon-fiber substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card connects up to 28 data lines to the lpGBT and VL+ ASICs that provide data serialization and 10 GBit/s optical data transmission to the off-detector systems respectively. The EoS is powered by a dedicated Dual-Stage DC-DC converter. With the EoS now moving into production we report on first experiences from production and also give a few lessons learned during the project duration.

Speaker: Sara Ruiz Daza (Deutsches Elektronen-Synchrotron (DE))

ruizdaza_TWEPP23.pdf

178 The optimization, design and performance of the FBCM23 ASIC for the upgraded CMS beam monitoring system

We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment. The FBCM system should provide reliable luminosity measurement with 1ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises six channels of fast preamplifier working in transimpedance configuration followed with CR-RC3 shaper and leading edge discriminator. The paper will show the optimization of the design, overall architecture and the detailed implementation in a CMOS 65nm process as well as preliminary electrical performance.

Speaker: Grzegorz Jan Wegrzyn (CERN)

ENC3D6pF8.pdf

FBCM23_Twepp2023_poster.pdf

FBCMchanTWP.pdf

FBCMpreampTWP.pdf

179 The phase-1 upgrade of the ATLAS level-1 calorimeter trigger

The ATLAS level-1 calorimeter trigger is a custom-built hardware system
that identifies events containing calorimeter-based physics objects,
including electrons, photons, taus, jets, and missing transverse energy.
In Run 3, L1Calo has been upgraded to process higher granularity
input data. The new trigger, currently running in parallel with the
legacy system, comprises several FPGA-based feature extractor modules,
which process the new digital information from the calorimeters and
execute more sophisticated trigger algorithms. The design of the
system will be presented along with an analysis of the improved
performance of the upgrade in the increasingly challenging Run-3
LHC pile-up environment.

Speaker: Tigran Mkrtchyan (Heidelberg University (DE))

180 The quality control programme for ITk strip tracker module assembly

The assembly of the ATLAS Inner Tracker requires the construction of 19,000 silicon strip sensor detector modules in eight different geometries. Modules will be assembled and tested at 31 institutes on four continents, from sensors, readout chips and flexes. In order to adhere to the module specifications defined for sufficient tracking performance, a rigorous programme of quality control and assurance was established to cover components at every stage of assembly. This contribution presents an overview of the QA/QC programme for ITk strip tracker modules, results from the pre-production phase (5% of the production volume) and proposed adjustments for production.

Speaker: Abraham Tishelman-Charny (Brookhaven National Laboratory (US))

ATL-COM-ITK-2023-069.pdf

181 Time-Delay-Based Analog Front-End for Monitored Drift Tubes in 65 nm CMOS with < 200 ns Baseline Recovery Time and Coherent Time-over-Threshold

Monitored Drift Tube (MDT) chambers for muons detection at ATLAS Experiment adopt analog front-end read-out electronics for precise-tracking/momentum measurements of detected particles [1]. State-of-the-art has historically used bipolar shaping electronics (at approximately 800 ns baseline recovery time [2]) that scarcely fits with High-Luminosity (HL) requirements where small-MDT (sMDT [3]) are used at 180 ns input signal time-width. This brief presents 4-channels Application Specified Integrated Circuit in 65 nm CMOS for sMDT signal amplification and shaping that performs < 200 ns baseline recovery time and avoids distortion of Time-over-Threshold (ToT) characteristic due to multiple close input charge pulses composing sMDT signal.

Speaker: Syed Adeel Ali Shah

TimeDelayBased_ASD_Twepp_2023.pdf

182 Two HVCMOS active pixel ASIC designs for the Measuring GCR and SEP with a combined dynamic range of >80dB

The design of HVCMOS pixel detectors for measuring Galactic Cosmic Rays (GCR) and Solar Energetic Particles (SEP) in space is presented. The design goals are: (a) cover a very wide dynamic range (from ~0.5fC to pC) and (b) minimize the power consumption. Two pixel designs were implemented, one tailored to the measurement of high energy depositions due to impinging ions and one with high gain for the low energy depositions resulting from minimum ionizing particles. Both designs have been fabricated in the LFoundry 0.15μm technology. The design choices are backed by simulation results and preliminary measurements.

Speaker: Dr Elena Papadomanolaki (ADVEOS Microelectronic Systems P.C.)

twepp_2023_papadomanolaki.pdf

183 Universal test system for boards hosting bPOL12V DC-DC converters.

ECAL Barrel (EB) and MTD Barrel Timing Layer (BTL) subdetectors of the CMS are approaching series production of electronic boards, including voltage conditioning PCBs: LVR and PCC respectively. 2448 LVRs and 864 PCCs will be installed during LS3 of the LHC. These boards are hosting radiation-tolerant bPOL12V ASICs which convert a broad input voltage range into required voltage levels for microelectronics between 1.2 – 2.5V. Each card must be tested multiple times at various production stages to ensure its quality. This contribution describes a methodology of testing bPOL12V conversion quality including the detection of instability regions at certain load levels.

Speaker: Krzysztof Stachon (ETH Zurich (CH))

TWEPP23_Abstract_KS.pdf

TWEPP23_Abstract_KS_supplementary_materials.pdf

19:00 Committee meeting

20:30 Conference dinner

Friday 6 October

Radiation-Tolerant Components and Systems

Convener: Hucheng Chen (Brookhaven National Laboratory (US))

184 CERN Radiation Hardness Assurance: Challenges and Solutions for Large-Scale Distributed System Exposed to High-Energy Particle Accelerator Environments

The electronic systems at CERN, exposed to the harsh radiation environments of particle accelerators and experiments, require specific qualification procedures to ensure reliability under radiation. A large number of distributed systems, thermal neutron fluences in shielded areas, and spectra composed mainly of neutrons are some of the unique challenges that the LHC presents. CERN has developed its own radiation hardness assurance procedure that addresses them through specific test methodologies. Based on lessons learned from component and system qualification, this paper presents CERN's system qualification procedure, these test methods, and lessons learned.

Speaker: Alessandro Zimmaro (Universite Montpellier II (FR))

CERN_Radiation_Hardness_Assurance_Challenges_and_Solutions_for_Large-Scale_Distributed_System_Exposed_to_High-Energy_Particle_Accelerator_Environme.pdf

CERN Radiation Hardness Assurance Challenges and Solutions for Large-Scale Distributed System Exposed to High-Energy Particle A.pdf

CERN Radiation Hardness Assurance Challenges and Solutions for Large-Scale Distributed System Exposed to High-Energy Particle A.pptx

185 CRATEBO: A High-speed, Radiation-Tolerant and Versatile Testing Platform for FPGA Radiation Qualification for High-Energy Particle Accelerator applications

The CHARM Radiation Tolerant Tester Board (CRATEBO) is a testing platform for the CERN High-energy Accelerator (CHARM) irradiation facility. It is meant to ease the radiation testing of FPGA-based systems by providing users with a radiation-tolerant carrier card for the Device Under Test (DUT). It provides a high-speed communication interface, a flexible power supply, and DUT connections via a System-On-Module socket and an HPC-FMC connector. It is a permanent installation in the CHARM facility at CERN that gives the possibility to users to perform radiation tests of their system with minimum development effort on the test setup.

Speaker: Antonio Scialdone (Universite Montpellier II (FR))

CRATEBO A High-speed Radiation-Tolerant and Versatile Platform for FPGA testing.pdf

CRaTeBo_A_High_Speed_Radiation_Tolerant_and_Versatile_Platform_for_FPGA_Testing.pdf

CRaTeBo_A_High_Speed_Radiation_Tolerant_and_Versatile_Platform_for_FPGA_Testing.pptx

System Design, Description and Operation

Convener: Andrea Boccardi (CERN)

186 Design and performance of the front-end electronics of the charged particle detectors of PADME experiment

The PADME experiment at LNF-INFN employs positron-on-target-annihilation technique to search for new light particles. Crucial part of the experiment are the charged particle detectors, composed of plastic scintillator bars with light transmitted by wavelength shifting fibers to silicon photomultipliers (SiPM). The location of the detector – close to a turbomolecular pump, inside a vacuum tank, and exposed to 0.5 T magnetic field – has driven the design of custom modular SiPM front-end and power supply electronics. The design of the system and its performance, confirming the desired sub-ns resolution on the reconstructed particle times, will be shown and discussed.

Speaker: Simeon Ivanov (Sofia University, Bulgaria)

TWEPP2023_presentation.pdf

187 From 3D to 5D tracking: SMX ASIC-based Double-Sided Micro-Strip detectors for comprehensive space, time, and energy measurements

We present the recent development of a lightweight detector capable of accurate spatial, timing, and amplitude resolution of charged particles. The technology is based on double-sided double-metal p+-n-n+ micro-strip silicon sensors, ultra-light long aluminum-polyimide micro-cables for the analogue signal transfer, and a custom-developed SMX read-out ASIC capable of measurement of the time ($\Delta t\simeq 5\,\mathrm{ns}$) and amplitude. Dense detector integration enables material budget $>0.3\%,X_0$. The sophisticated powering and grounding keeps the noise under control.

In addition to its primary application in Silicon Tracking System of the future CBM experiment in Darmstadt, our detector will be utilized in other research applications.

Speaker: Maksym Teklishyn

smx_5d_tracking_teklishyn_06OCT2023.pdf

TWEPP2023award_ID198.pdf

09:40 Coffee break

Module, PCB and Component Design

Convener: Ken Wyllie (CERN)

188 The development of a laser system for use in the timing performance measurements of CMS HGCAL silicon modules

For optimal operations in the high radiation and pileup environment of the HL-LHC, the CMS-HGCAL requires precise timing information at the level of 30ps (RMS) for a particle shower. The time measurement in Silicon detector modules is performed using a per-channel time-of-arrival discriminator coupled with charge measurement to correct for the time-walk. The module design includes access holes in the PCB and in the sensor passivation to enable infrared laser light to be injected directly into the sensor cells. We present the calibration and timing-in of the system used to perform measurements as well as the module time performance results.

Speaker: Fakhri Alam Khan (Universite Libre de Bruxelles (BE))

The Laser system for silicon module timing performance validation study.pdf

TWEPP-Fakhri_timing performance validation of CMS-HGCAL silicon detector.pdf

189 Front End Board for Large Area SiPM Detector

Silicon photomultipliers (SiPMs) are widely used for several applications, such as High Energy Physics experiments, as well as other research and industrial fields. SiPMs working at low temperature, in particular, are the most interesting application for the newly large particle detectors for neutrinos and dark matter experiments. In this work we present a low-noise, high-speed front-end electronics (Front-End Boards, FEBs) for large area SiPMs to be used in the JUNO-TAO experiment. The FEBs are able to manage the signals coming from a 25 cm^2 tile, showing single photoelectron resolution better than 13% and dynamic range up to 250 p.e.

Speaker: Carlo Venettacci

FEB for large area SiPM detector - CarloVenettacci.pdf

TWEPP_summary.pdf

Optoelectronics and Electrical Data Links

Convener: Francois Vasey (CERN)

190 Test Bench of a 100G Radiation Hardened Link for Future Particle Accelerators

Pioneering physics experiments require increasingly faster data transfers and high-throughput electronics, which drives the research towards a new class of serialisers and optical links. In this framework, the DART28, a $100\,Gbps$ radiation tolerant serialiser and driver, has been designed in $28\,nm$ CMOS technology and submitted in April 2023. The development has been coupled with an FPGA based emulation, which provided an early assessment of its behaviour, a scalable system-level demonstrator and an effective evaluation tool for compatible commercial solutions. The challenges faced in this research and the architecture of both the hardware setup and the firmware will be described.

Speaker: Francesco Martina (CERN)

TWEPP2023award_ID142.pdf

TWEPP23_FMartina.pdf

191 Compact Silicon Photonic Mach-Zehnder Modulators for High-Energy Physics

The characterization of compact non-traveling-wave Mach-Zehnder modulators (NTW-MZMs) for optical readout in high-energy physics experiments will be presented to provide power-efficient alternatives to conventional traveling-wave devices and a more resilient operation compared to ring modulators. Electro-optical small-signal and large-signal measurements will be reported to show the performances of a custom NTW-MZM designed and fabricated in iSiPP50G IMEC’s technology in the framework of INFN's FALAPHEL project. Bit-error-rate results will demonstrate its potential suitability for data links up to 25 Gb/s when being driven by voltage levels compatible with integrated CMOS drivers.

Speaker: Simone Cammarata (Universita & INFN Pisa (IT))

abstract_images_twepp2023_30-04-2023.pdf

s-cammarata_twepp2023.pdf

TWEPP2023award_ID181.pdf

Closing

20231006TWEPPclosing.pdf

20231006TWEPPclosing.pptx

TWEPP-2023-Sardegna_Closeout-small.pdf

TWEPP-2023-Sardegna_Closeout-small.pptx

11:30 Break

Tutorial - Digital Verification for FPGA and ASIC Designers

Digital Verification for FPGA and ASIC Designers v1.0 Workbook(A4 Book).pdf